DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 4/27/2026 have been fully considered but they are not persuasive.
In response to applicant’s argument against the 112(a) written description rejection, applicant argues that the terms “scalar” and “vector” are well known in the art and the specification describes separate scalar/vector data paths and identify specific units. However, while the specification lists labels and arbitrary names for certain execution blocks, it fails to set forth the specific hardware boundaries, internal structure, or architectural distinctions that constitute a “scalar functional unit” versus a “vector functional unit” across all the claimed embodiments. Mere functional naming or labeling in the specification without disclosing the underlying structural hardware features does not demonstrate that the inventor possessed the full scope of the claimed structural arrangement as the time of filing. Therefore, the rejection of claims 7, 8, 12,13, 17, 18 under 35 USC 112(a) is maintained.
In response to applicant’s argument against the 112(b) indefiniteness rejection, applicant argues that “de-assert” is a well-established term of the art in digital logic, meaning driving a signal to its inactive state, regardless of whether the logic is active high or active low. However, while “de-assert” can refer broadly to an inactive state in logic design, its usage in the context of the claims creates ambiguity regarding the precise signal conditions required to cause register clearing. The claim recites that functional units “de-assert the respective write enable output” to “cause the register to be cleared”. Because the claim language leaves it unclear whether the clearing is driven by a specific logic level or an absence of driving voltage, one skilled in the art cannot determine the scope of the claim with reasonable certainty. Accordingly, the rejection of claims 1, 9, 11, 14, and 16 under 35 USC 112(b) is maintained.
Regarding claims 1, 9, and 14, applicant argues that Ferguson teaches register clearing by asserting write enables, where the claims recite de-asserting respective write enable outputs. Under BRI, “de-asserting” refers to placing an output control signal into its inactive state relative to normal data write operations. In Ferguson, when entering data cleansing mode, normal functional unit writes area overridden and inhibited. By forcing the registers to take cleansing values via clock gating rather than functional instruction execution, the write enable outputs of the functional units during normal operation are held inactive/de-asserted relative to the register write ports.
Regarding Claim 5, applicant argues that Ferguson does not explicitly disclose the claimed AND/OR logic gate arrangement. However, Ferguson discloses logic circuitry that combines address signals, write enables, and clock signals to route data to register write inputs. Conventional multiplexing and gating circuitry that combines multiple inputs to a single register write port inherently consists of AND/OR gate logic trees under BRI.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 9, 11, 14, 16, the limitations drawn to functional units being de-asserted render the claims indefinite since it is not clear what logic level constitute de-assertion and the term is ambiguous without a clear definition.
All other claims are equally rejected as having the same deficiencies as their corresponding parent claims.
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 7, 8, 12, 13, 17, 18 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The specification does not provide structural support for “scalar functional units” or “vector functional units”. The two terms are not properly distinguished and therefore, it is not clear what makes a functional unit scalar or vector. The difference is not specified.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 9-11, 14-16 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ferguson [US 20220019437].
Claim 1, Ferguson discloses a device [processing unit, abstract] comprising: a register file that includes a register that includes a data input [par. 0042]; a set of functional units that each include a data output coupled to the data input of the register file [par. 0038] and a write enable output coupled to the data input of the register file [par. 0042-0043]; and an instruction decode circuit configured to: receive an instruction that specifies the register [par. 0029-0031]; and based on the instruction: cause each of the set of functional units to de-assert the respective write enable output; and cause the register to be cleared [cleansing mode, par. 0050-0055; write zeros, par. 0045].
Claim 2, Ferguson discloses the device of claim 1, wherein: the register includes an enable input [40, par. 0042]; and the instruction decode circuit is configured to, based on the instruction, cause a clock signal to be provided to the enable input of the register [par. 0034].
Claim 3, Ferguson discloses the device of claim 1, wherein the set of functional units is configured such that no more than one of the respective write enable outputs of the set of functional units is asserted at a time [par. 0042 “… only one of which will have its write enable input 40 enabled at any given time”].
Claim 4, Ferguson discloses the device of claim 1 further comprising a set of circuitry that includes: a set of data inputs coupled to the respective data outputs of the set of functional units; a set of write enable inputs coupled to the respective write enable outputs of the set of functional units; and a data output coupled to the data input of the register [Fig. 1, par. 0042].
Claim 5, Ferguson discloses he device of claim 4, wherein the set of circuitry includes: a set of AND circuitry that includes the set of data inputs of the set of circuitry and the set of write enable inputs of the set of circuitry; and a set of OR circuitry that includes the data output and that is coupled to the set of AND circuitry [wherein the logic behavior is described within the functions of the invention, par. 0043-0048].
Claim 6, Ferguson discloses the device of claim 1, wherein: the register is a first register; the register file includes a second register; the instruction specifies the second register; and the instruction decode circuit is configured to, based on the instruction, cause the second register to be cleared [par. 0050-0051].
Claims 9-11 are rejected using the same rationale as claims 1-6 above.
Claims 14-16 are rejected using the same rationale as claims 1-6 above.
Claim 19, Ferguson discloses the device of claim 6, wherein in addition to the first register and the second register, the register file includes one or more additional registers [par. 0044, Fig 2]; the instruction does not specify any of the one or more additional registers [par. 0050]; and the instruction decode circuit is configured to, based on the instruction, not cause the one or more additional registers to be cleared [par. 0050 and 0057].
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/MIDYS ROJAS/Primary Examiner, Art Unit 2133
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