DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/21/2024 was considered by the examiner.
Drawings
The drawings received on 10/21/2024 have been accepted by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 9, 11, 14, 16, the limitations drawn to functional units being de-asserted render the claims indefinite since it is not clear what logic level constitute de-assertion and the term is ambiguous without a clear definition.
All other claims are equally rejected as having the same deficiencies as their corresponding parent claims.
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 7, 8, 12, 13, 17, 18 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The specification does not provide structural support for “scalar functional units” or “vector functional units”. The two terms are not properly distinguished and therefore, it is not clear what makes a functional unit scalar or vector. The difference is not specified.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 9-11, 14-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ferguson [US 20220019437].
Claim 1, Ferguson discloses a device [processing unit, abstract] comprising: a register file that includes a register that includes a data input [par. 0042]; a set of functional units that each include a data output coupled to the data input of the register file [par. 0038] and a write enable output coupled to the data input of the register file [par. 0042-0043]; and an instruction decode circuit configured to: receive an instruction that specifies the register [par. 0029-0031]; and based on the instruction: cause each of the set of functional units to de-assert the respective write enable output; and cause the register to be cleared [cleansing mode, par. 0050-0055; write zeros, par. 0045].
Claim 2, Ferguson discloses the device of claim 1, wherein: the register includes an enable input [40, par. 0042]; and the instruction decode circuit is configured to, based on the instruction, cause a clock signal to be provided to the enable input of the register [par. 0034].
Claim 3, Ferguson discloses the device of claim 1, wherein the set of functional units is configured such that no more than one of the respective write enable outputs of the set of functional units is asserted at a time [par. 0042 “… only one of which will have its write enable input 40 enabled at any given time”].
Claim 4, Ferguson discloses the device of claim 1 further comprising a set of circuitry that includes: a set of data inputs coupled to the respective data outputs of the set of functional units; a set of write enable inputs coupled to the respective write enable outputs of the set of functional units; and a data output coupled to the data input of the register [Fig. 1, par. 0042].
Claim 5, Ferguson discloses he device of claim 4, wherein the set of circuitry includes: a set of AND circuitry that includes the set of data inputs of the set of circuitry and the set of write enable inputs of the set of circuitry; and a set of OR circuitry that includes the data output and that is coupled to the set of AND circuitry [wherein the logic behavior is described within the functions of the invention, par. 0043-0048].
Claim 6, Ferguson discloses the device of claim 1, wherein: the register is a first register; the register file includes a second register; the instruction specifies the second register; and the instruction decode circuit is configured to, based on the instruction, cause the second register to be cleared [par. 0050-0051].
Claims 9-11 are rejected using the same rationale as claims 1-6 above.
Claims 14-16 are rejected using the same rationale as claims 1-6 above. Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Craske [US 8,583,897]; Register File with Circuitry for Setting Register Entries to a Predetermined Value. See Abstract.
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/MIDYS ROJAS/Primary Examiner, Art Unit 2133