DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities: Please update related application data.
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 1, 2, 7 ,8, 11, 15, 16 and 19 (of current application ‘121)are rejected on the ground of non-statutory double patenting as being unpatentable over claims 1-19 of U.S. Patent No. 12,166,493.
Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the current application are broader in scope, for example, The current application independent claims for A PLL system(cls. 1 and 8) and method claim 15, for the application, are merely broader in scope than the patented claims 1 and 16, for PFD, and with claim 11 claiming a current source in the charge pump. The patented claims reciting a PFD, phase/ frequency detector and charge pump details that are main elements of conventional PLL loop systems. Common to both sets of claims are charge pump and current adjusting circuit that is configurable to increase the bias current by a first amount responsive to the control voltage being in a first range, and decrease the bias current by a second amount responsive to the control voltage being in a second range; wherein the chirp signal has a bandwidth defined by a first bandwidth segment that corresponds to the control voltage being in the first range and a second bandwidth segment that corresponds to the control voltage being in the second range.
The present application claims, claims 1 8 and 15 , for example, do not recite a particular detector such as the phase/frequency detector and current source for charge pump that are conventional in a PLL.
Current application: 18/921,121
US Patent 12,166,493
A system comprising: a phase-locked loop including a charge pump, and a voltage-controlled oscillator (VCO) coupled to the charge pump, wherein the VCO is configured to receive a control voltage, and the phase-locked loop is configured to output a chirp signal based on the control voltage; and current adjusting circuitry configured to receive the control voltage and control a bias current provided to the charge pump, wherein the current adjusting circuitry is configurable to increase the bias current by a first amount responsive to the control voltage being in a first range, and decrease the bias current by a second amount responsive to the control voltage being in a second range; wherein the chirp signal has a bandwidth defined by a first bandwidth segment that corresponds to the control voltage being in the first range and a second bandwidth segment that corresponds to the control voltage being in the second range.
The system of claim 1, wherein the current adjusting circuitry is further configured to increase the bias current by a third amount responsive to the control voltage being in a third range.
3. The system of claim 1, wherein the current adjusting circuitry includes: a first current-steering digital-to-analog converter (DAC) configurable to receive the control voltage and source a first current of the first amount responsive to the control voltage being in the first range; and a second current-steering DAC configurable to receive the control voltage and sink a second current of the second amount responsive to the control voltage being in the second range.
4. The system of claim 2, wherein the current adjusting circuitry includes: a first current-steering digital-to-analog converter (DAC) configurable to receive the control voltage and source a first current of the first amount responsive to the control voltage being in the first range; a second current-steering DAC configurable to receive the control voltage and sink a second current of the second amount responsive to the control voltage being in the second range; and a third current-steering DAC configurable to receive the control voltage and source a third current of the third amount responsive to the control voltage being in the third range.
5. The system of claim 4, further comprising a voltage threshold circuit configurable to provide respective threshold values to the first, second and third current-steering DACs.
6. The system of claim 4, further comprising a current generator configurable to output a constant current, wherein the bias current is: a sum of the constant current and the first current when the control voltage is in the first range; a difference of the constant current and the second current when the control voltage is in the second range; and a sum of the constant current and the third current when the control voltage is in the third range.
7. The system of claim 1, wherein the chirp signal varies in frequency responsive to the control voltage, and a gain of the VCO varies with the control voltage.
8. A system comprising: a phase-locked loop including a charge pump, and a voltage-controlled oscillator (VCO) coupled to the charge pump, wherein the VCO is configured to receive a control voltage, and the phase-locked loop is configured to output a chirp signal based on the control voltage; and current adjusting circuitry configured to receive the control voltage and control a charge pump current output by the charge pump, wherein the current adjusting circuitry is configurable to cause the charge pump current to increase by a first amount responsive to the control voltage being in a first range, and cause the charge pump current to decrease by a second amount responsive to the control voltage being in a second range; wherein the chirp signal has a bandwidth defined by a first bandwidth segment that corresponds to the control voltage being in the first range and a second bandwidth segment that corresponds to the control voltage being in the second range.
9. The system of claim 8, wherein the current adjusting circuitry includes: a current-steering digital-to-analog converter (DAC) having a voltage input coupled to receive the control voltage, the current-steering DAC having a current output; and a current source having a current input coupled to the current output of the current-steering DAC, the current source having a current output configured to output a bias current to the charge pump.
10. The system of claim 9, wherein the current-steering DAC is configurable to source or sink a current to control the bias current output to the charge pump based on the control voltage.
11. The system of claim 8, wherein the current adjusting circuitry is further configurable to cause the charge pump current to increase by a third amount responsive to the control voltage being in a third range.
12. The system of claim 11, wherein the current adjusting circuitry includes: a first current-steering digital-to-analog converter (DAC) configurable to receive the control voltage and source a first current of the first amount responsive to the control voltage being in the first range; a second current-steering DAC configurable to receive the control voltage and sink a second current of the second amount responsive to the control voltage being in the second range; and a third current-steering DAC configurable to receive the control voltage and source a third current of the third amount responsive to the control voltage being in the third range.
13. The system of claim 8, wherein the current adjusting circuitry includes a current source having a current output configured to provide a bias current to the charge pump, a plurality of attenuation current-steering digital-to-analog converters (DACs), each coupled to the current output, and a plurality of boost current-steering DACs, each coupled to the current output.
14. The system of claim 13, wherein each attenuation current-steering DAC of the plurality of attenuation current-steering DACs is configured to activate to decrease the bias current based the control voltage, and each boost current-steering DAC of the plurality of boost current-steering DACs is configured to activate to increase the bias current based on the control voltage.
15. A method comprising: outputting, by a charge pump in a phase-locked loop, a charge pump current; providing a control voltage to a voltage-controlled oscillator (VCO) in the phase-locked loop; causing, by current adjusting circuitry, the charge pump current to increase by a first amount, responsive to the control voltage being within a first range; causing, by the current adjusting circuitry, the charge pump current to decrease by a second amount responsive to the control voltage being within a second range; and causing, by current adjusting circuitry, the charge pump current to increase by a third amount, responsive to the control voltage being within a third range.
16. The method of claim 15, further comprising: providing a bias current to the charge pump, wherein the amount of bias current provided is based on the control voltage.
17. The method of claim 16, further comprising: providing, by a current generator, a constant current; sourcing a first adjusting current of a first amount, by the current adjusting circuitry, responsive to the control voltage being within the first range; sinking a second adjusting current of a second amount, by the current adjusting circuitry, responsive to the control voltage being within the second range; and sourcing a third adjusting current of a third amount, by the current adjusting circuitry, in a first amount responsive to the control voltage being within the third range.
18. The method of claim 17, wherein the bias current is: a sum of the constant current and the first adjusting current when the control voltage is within the first range; a difference between the constant current and the second adjusting current when the control voltage is within the second range; and a sum of the constant current and the third adjusting current when the control voltage is within the third range.
19. The method of claim 16, wherein increasing the bias current increases a bandwidth of the phase-locked loop, and decreasing the bias current decreases the bandwidth of the phase-locked loop.
1. A system, comprising: a phase-locked loop including a charge pump coupled to a phase frequency detector, and a voltage-controlled oscillator (VCO) coupled to the charge pump, the charge pump having a current input, wherein the charge pump is configured to receive a first signal or a second signal from the phase frequency detector and output a charge pump current based which of the first signal or the second signal is received, wherein the phase-locked loop is configured to output a chirp signal; and current adjusting circuitry having an input configured to receive a control voltage provided to the VCO and having an output coupled to the current input of the charge pump, the current adjusting circuitry configured to output an adjusting current to the current input of the charge pump, wherein the current adjusting circuitry is configured to increase the adjusting current responsive to the control voltage being within a first range and configured to decrease the adjusting current responsive to the control voltage being within a second range, wherein the the chirp signal has a bandwidth defined by a first bandwidth segment corresponding to the control voltage being in the first range and a second bandwidth segment corresponding to the control voltage being in the second range.
2. The system of claim 1, wherein: the current adjusting circuitry is further configured to increase the adjusting current responsive to the control voltage being within a third range.
3. The system of claim 1, wherein the the output of the current adjusting circuitry is a first output, the current adjusting circuitry including one or more current-steering digital-to-analog converters (DACs) each having an individual output which together form the first output, and a current source having a second output coupled to the first output.
4. The system of claim 1, further comprising: a voltage threshold generator circuit configured to provide the first range and the second range.
5. The system of claim 1, wherein the chirp signal varies in frequency responsive to the control voltage.
6. The system of claim 1, wherein a gain of the VCO varies with the control voltage.
7. The system of claim 6, wherein the current adjusting circuitry includes a first compensation circuit configured to increase the adjusting current to compensate for the gain of the VCO.
8. The system of claim 6, wherein the current adjusting circuitry includes a second compensation circuit configured to decrease the adjusting current to compensate for the gain of the VCO.
9. The system of claim 1, wherein increasing the adjusting current increases the charge pump current, and decreasing the adjusting current decreases the charge pump current.
10. The system of claim 1, wherein increasing the adjusting current increases a bandwidth of the phase-locked loop, and decreasing the adjusting current decreases the bandwidth of the phase-locked loop.
11. A method, comprising: providing, with a current source, a bias current to a charge pump in a phase-locked loop; providing a control voltage to a voltage-controlled oscillator (VCO) in the phase-locked loop, wherein the control voltage is provided responsive to a charge pump current from the charge pump; responsive to the control voltage being within a first range, increasing the bias current provided to the charge pump with a first bias compensation circuit; responsive to the control voltage being within a second range, decreasing the bias current provided to the charge pump with a second bias compensation circuit; and generating, by the phase-locked loop, a chirp signal that varies in frequency responsive to the control voltage, wherein the chirp signal has a bandwidth defined by a first bandwidth segment corresponding to the control voltage being in the first range and a second bandwidth segment corresponding to the control voltage being in the second range.
12. The method of claim 11, further comprising: responsive to the control voltage being within a third range, increasing the bias current provided to the charge pump with a third bias compensation circuit.
13. The method of claim 11, wherein the first bias compensation circuit is a current-steering digital-to-analog converter (DAC).
14. The method of claim 11, wherein increasing the bias current increases a bandwidth of the phase-locked loop.
15. The method of claim 11, wherein decreasing the bias current decreases a bandwidth of the phase-locked loop.
16. A system, comprising: a phase-locked loop including a charge pump coupled to a phase frequency detector, and a voltage-controlled oscillator (VCO) coupled to the charge pump, the charge pump having a current input, wherein the charge pump is configured to receive a first signal or a second signal from the phase frequency detector and output a charge pump current based on which of the first signal or the second signal is received, wherein a control voltage is provided to the VCO, and a gain of the VCO varies with the control voltage; a voltage threshold generator configured to provide a first voltage range and a second voltage range; and current adjusting circuitry having an input configured to receive the control voltage and having an output coupled to the current input of the charge pump, the current adjusting circuitry configured to output an adjusting current to the current input of the charge pump, wherein the current adjusting circuitry is configured to increase the adjusting current responsive to the control voltage being within the first voltage range and configured to decrease the adjusting current responsive to the control voltage being within the second voltage range, wherein the chirp signal has a bandwidth defined by a first bandwidth segment corresponding to the first voltage range and a second bandwidth segment corresponding to the second voltage range.
17. The system of claim 16, wherein increasing the adjusting current increases a bandwidth of the phase-locked loop.
18. The system of claim 16, wherein decreasing the adjusting current decreases a bandwidth of the phase-locked loop.
19. The system of claim 16, wherein: the current adjusting circuitry is further configured to increase the adjusting current responsive to the control voltage provided to the VCO being within a third voltage range.
The PFD detector allows for the PLL to lock on to phase and/or frequency, a simple matter of design consideration, notoriously well known in the art, and are part and parcel of these systems.. The charge pump is designed conventionally with current source for up/down biasing to allow inc/dec of current to LPF. The examiner takes official notice with regards these elements.
In light of the above it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have recognized that the claims now presented in the application are merely broader in scope as outlined above with regards the PLL with a PFD and charge pump biasing, as recited in the patented claims , as conventional and well known features of these PLL loops, to achieve rapid phase and/or frequency lock with the appropriate Vc, control voltage via the charge pump as simple matters of design consideration.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 15, 16 and 19 are is/are rejected under 35 U.S.C. 103 as being unpatentable over Fujita, US 20050215221(cited by applicant).
The reference to Fujita shows a charge pump(figure 11), that is part of a PLL loop to supply current to a loop filter where a control voltage is developed for the VCO input.
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The charge pump(131) develops a current through the loop filter which then provides a control voltage(Vc) to a voltage-controlled oscillator (VCO) in the phase-locked loop;
The Vc is then feedback to the charge pump current adjust mechanism.
A current adjusting circuitry( including 138,139,140, 141,142,143), allows the charge pump current to increase by a first amount, responsive to the control voltage being within a first range;
See ¶ [0146] “ If V0 + ΔV2<=VC when the latch circuit 137 latches the signals output from the comparators 135 and 136, analog switch 141 is placed in the conducting state and analog switch 142 is placed in the non-conducting state, so the current flowing through n-channel MOS transistor 143 increases from 20 .mu.A to 21 .mu.A. The current flowing through each of the current source transistors in the current source circuit 100 or 120 then increases to twenty-one twentieths ({fraction (21/20)}) of the current that flows when V0-ΔV1</=VC<=V0 + Δ.V2.”
AND
causes by the current adjusting circuitry, the charge pump current to decrease by a second amount responsive to the control voltage being within a second range;
See ¶[0145] “ If VC</=V0-ΔV1 when the latch circuit 137 latches the signals output from the comparators 135 and 136, analog switch 141 is placed in the non-conducting state and analog switch 142 is placed in the conducting state, so the current flowing through n-channel MOS transistor 143 decreases from 20 .mu.A to 19 .mu.A. The current flowing through each of the current source transistors in the current source circuit 100 or 120 then decreases to nineteen twentieths ({fraction (19/20)}) of the current that flows when V0 - ΔV1< VC<V0 + ΔV2.”
The reference does not show an increase in the charge pump current for a third amount, responsive to the control voltage, in a third range, however, this is simply a matter of design consideration that allows an expanded range of control for the PLL particular bandwidth operations and response. That is, specifying different ranges for Vc, see for example, figure 16, where a more complex resistive divider is shown and additional comparator that could be designed as such.
In light of the above it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have recognized that the Fujita reference may be used with multiple Vc ranges of operation where current is increased, for example, albeit at a different rate, and thus achieve a varied response of the PLL as desired. A simple matter of design consideration.
Re claim 16: As shown in figure and noted above, a bias current is provided in the charge pump, the amount of bias current provided is based on the control voltage Vc feedback to the pump and current source.
Re claim 19: The increase of the bias current inherently increases a bandwidth of the phase-locked loop, as the gain is increased, while decreasing the bias current inherently decreases the bandwidth of the phase-locked loop.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The references cited by examiner to Maxim and Kumar, show conventional PLL systems with current adjustment, however, the voltage control range(s) and current adjust details are not suggested. Also, no chirp signal is suggested.
Allowable Subject Matter
Claims 3, 4, 5, 6, 9, 10, 12, 13, 14, 17 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARNOLD M KINKEAD whose telephone number is (571)272-1763. The examiner can normally be reached M-F 7am-5:30pm(Fri-Flex).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at 571-270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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ARNOLD M. KINKEAD
Primary Examiner
Art Unit 2849
/ARNOLD M KINKEAD/Primary Examiner, Art Unit 2849