DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 21, 28-31, 33, and 38-40 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (CN 109428670 A; hereinafter Huang) in view of Kern et al. (US 2015/0007001 A1; hereinafter Kern).
Regarding claims 21 and 39, Huang teaches a communication apparatus (¶ [0260] The base station sends a transport block.), comprising at:
at least one processor (¶ [0290] This invention also provides a computer device, which includes at least one processor.); and
at least one memory coupled to the at least one processor, wherein the at least one processor is configured to execute a computer program or instructions stored in the at least one memory, to perform (¶ [0220] This computer software product is stored in a storage medium and includes several instructions to cause a computer device to execute all or part of the methods described in the various embodiments of the present invention.; ¶ [0292] Memory stores executable modules or data structures, or subsets thereof, or extended sets thereof.):
sending, by a communication apparatus (read as base station), a first bit sequence (read as transport block A) to a receiving device (read as terminal), wherein the first bit sequence is an information bit sequence (¶ [0260] The base station sends a transport block A with a length of 842,376 bits to the terminal. The transport block A is encoded using a 24-bit transport block-level CRC to generate a data block B with a length of 842,400 bits.);
receiving, by the communication apparatus, a second bit sequence from the receiving device (¶ [0266] The terminal generates a 10-bit CBG reception indication, indicating whether the reception is correct or incorrect, with each bit corresponding to one CBG. The terminal will send an indication message to the base station indicating whether CBG reception was correct or incorrect.); and
sending, by the communication apparatus, a first code block to the receiving device (¶ [0272] If the base station receives an indication from the terminal that the CBG reception was correct or incorrect, it will retransmit the data. When the receiving end receives the retransmitted CBG data, it only performs HARQ merging and decoding on the code blocks that were received incorrectly in the previous CBG transmission.),
wherein the first code block is obtained based on a first error pattern and a first check matrix (¶ [0114] An LDPC code can be uniquely defined by its parity check matrix H.; ¶ [0262] Each code block X is LDPC encoded.; ¶ [0272] If the base station receives an indication from the terminal that the CBG reception was correct or incorrect, it will retransmit the data from CBG#2 and CBG#6.; ¶ [0277] The terminal and base station can predefine a lookup table, which includes a set of CBG error patterns that may be received incorrectly for a specific total number of CBGs. The base station obtains an index value from the received CBG indication information, and looks up the lookup table based on the index value to obtain the location index of the incorrectly received CBG.),
Huang does not explicitly teach wherein the first error pattern is determined based on the second bit sequence and the first bit sequence.
In analogous art, Kern teaches wherein the first error pattern (read as ƒ) is determined based on the second bit sequence (read as u’) and the first bit sequence (read as u) (¶ [0436] An error can be described by an error vector.
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine error correction and error detection as taught by Kern with data error verification as taught by Huang. One would have been motivated to do so in order to increase reliability and reduce unnecessary retransmissions by Kern’s syndrome based processing to identify and correct correctable bit errors and Huang’s verification and feedback to identify code block groups requiring retransmission (Kern: ¶¶ [0003-0008]).
Regarding claim 28, Huang does not explicitly teach wherein when the first bit sequence is obtained through first encoding, and the first code block is obtained based on the first error pattern, the first check matrix, and an error correction capability of the first encoding.
In analogous art, Kern teaches wherein when the first bit sequence (read as codeword v) is obtained through first encoding (¶ [0469] If C is a linear code, then a codeword v may be determined by v=u*G, wherein G is the generator matrix of the code, G is here a (k, n) matrix with n-k=m.), and
the first code block (read as error syndrome S) is obtained based on the first error pattern (read as e), the first check matrix (read as H) (¶ [0472] The error syndrome S of a sequence v’=v’1,…,v’n is determined by ST=H*[v’1,…,v’n]T=H*[e1,…,en]T, and
an error correction capability of the first encoding (¶ [0570] An error correction is in principle possible, up to t bit errors within said set of k+m bits.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine error correction and error detection as taught by Kern with data error verification as taught by Huang. One would have been motivated to do so in order to increase reliability and reduce unnecessary retransmissions by Kern’s syndrome based processing to identify and correct correctable bit errors and Huang’s verification and feedback to identify code block groups requiring retransmission (Kern: ¶¶ [0003-0008]).
Regarding claim 29, Huang does not explicitly teach wherein the first check matrix is a check matrix of a Bose Ray-Chaudhuri Hocquenghem (BCH) code.
In analogous art, Kern teaches wherein the first check matrix (read as H) is a check matrix of a Bose Ray-Chaudhuri Hocquenghem (BCH) code (¶ [0511] An H matrix of BCH code).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine error correction and error detection as taught by Kern with data error verification as taught by Huang. One would have been motivated to do so in order to increase reliability and reduce unnecessary retransmissions by Kern’s syndrome based processing to identify and correct correctable bit errors and Huang’s verification and feedback to identify code block groups requiring retransmission (Kern: ¶¶ [0003-0008]).
Regarding claim 30, Huang teaches wherein the first bit sequence is obtained through first encoding (read as LDPC encoding), and the first encoding is cyclic redundancy check (CRC) encoding, BCH encoding, Reed-Solomon (RS) encoding, Reed-Muller (RM) encoding, polar code encoding, or low-density parity check (LDPC) encoding (¶ [0262] An 8/9 rate LDPC encoder is used to generate a codeword bit sequence Y of 9504 bits per code block.; Note: MPEP 2143.03: When a claim requires selection of an element from a list of alternatives, the prior art teaches the element if one of the alternatives is taught by the prior art. See, e.g., Fresenius USA, Inc. v. Baxter Int’l, Inc., 582 F.3d 1288, 92 USPQ2d 1163, 1171 (Fed. Cir. 2009).).
Regarding claims 31 and 40, Huang teaches a communication apparatus (¶ [0008] The terminal (User Equipment, UE).):
at least one processor (¶ [0290] This invention also provides a computer device, which includes at least one processor.); and
at least one memory coupled to the at least one processor, wherein the at least one processor is configured to execute a computer program or instructions stored in the at least one memory, to perform (¶ [0220] This computer software product is stored in a storage medium and includes several instructions to cause a computer device to execute all or part of the methods described in the various embodiments of the present invention.; ¶ [0292] Memory stores executable modules or data structures, or subsets thereof, or extended sets thereof.):
receiving, by a communication apparatus, a third bit sequence (read as information bits U) from a sending device, wherein the third bit sequence is an information bit sequence (¶ [0120] The receiving end receives a transmission signal including TB sent by the sending end, and obtains the TB based on the transmission signal.; ¶ [0121] Data block U consists of information bits.);
sending, by the communication apparatus, a second bit sequence (read as 8 bit index value of the error pattern) to the sending device (¶ [0277] The index value of the 175 CBG reception error patterns can be represented using 8 bits. Based on the CBG error verification results, the terminal refers to the lookup table and feeds back the index value of the corresponding error pattern.); and
receiving, by the communication apparatus, a fourth code block (read as an LDPC coded block within the retransmitted CBG data) from the sending device, wherein the fourth code block is obtained based on a first error pattern (read as ) and a first check matrix (read as H), wherein the first error pattern is determined based on the second bit sequence (read as index value) (¶ [0114] An LDPC code can be uniquely defined by its parity check matrix H.; ¶ [0262] Each code block X is LDPC encoded in units of code blocks.; ¶ [0272] If the base station receives an indication from the terminal that the CBG reception was correct or incorrect, it will retransmit the data from CBG#2 and CBG#6. When the receiving end receives the retransmitted CBG data, it only performs HARQ merging and decoding on the code blocks that were received incorrectly in the previous CBG transmission.; ¶ [0277] Based on the CBG error verification results, the terminal refers to the lookup table and feeds back the index value of the corresponding error pattern. The base station obtains an index value and looks up the lookup table based on the index value to obtain the location index of the incorrectly received CBG.).
Regarding claim 33, Huang does not explicitly teach decoding, by the communication apparatus, the fourth code block based on the first check matrix, to obtain the first error pattern; and correcting, by the communication apparatus, the third bit sequence based on the first error pattern.
In analogous art, Kern teaches decoding, by the communication apparatus, the fourth code block (read as syndrome s) based on the first check matrix (read as H), to obtain the first error pattern (read as correction signal) (¶ [0441] The syndrome corresponds to the 15-th column of the matrix H, that is to column vector that corresponds to the 7-th data bit. The decoder determines correction signals to the check bits and the data bits on the basis of the error syndrome s.); and
correcting, by the communication apparatus, the third bit sequence (read as erroneous data bits) based on the first error pattern (read as correction signal/values) (¶ [0334] The k first output lines of the decoder, which carry the correction values for the possibly erroneous data bits are fed to a first k bit wide input of a XOR circuit. The XOR circuit provides at its k bit wide output the corrected data bits.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine error correction and error detection as taught by Kern with data error verification as taught by Huang. One would have been motivated to do so in order to increase reliability and reduce unnecessary retransmissions by Kern’s syndrome based processing to identify and correct correctable bit errors and Huang’s verification and feedback to identify code block groups requiring retransmission (Kern: ¶¶ [0003-0008]).
Regarding claim 38, Huang does not explicitly teach wherein when the third bit sequence is obtained through first encoding, and the fourth code block is obtained based on the first error pattern, the first check matrix, and an error correction capability of the first encoding.
In analogous art, Kern teaches wherein when the third bit sequence is obtained through first encoding, and the fourth code block is obtained based on the first error pattern, the first check matrix, and an error correction capability of the first encoding (¶ [0472] The error syndrome s of a sequence v’=v’1,…,v’n is determined by ST=H*[v’1,…,v’n]T=H*[e1,…,en]T.; ¶ [0567] An n-component word v’=v’1,…,v’n is applied which consists of a codeword v=v1,…,vn of a linear code C of the length n with t*M=m check bits.; ¶ [0568] An error syndrome S determined by the syndrome generator according to the H matrix of the code C.; ¶ [0570] The t*M outputs of the syndrome generator Synd are connected to t*M inputs of a corrector Cor for correction up to t bit errors within said set of k+m bits.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine error correction and error detection as taught by Kern with data error verification as taught by Huang. One would have been motivated to do so in order to increase reliability and reduce unnecessary retransmissions by Kern’s syndrome based processing to identify and correct correctable bit errors and Huang’s verification and feedback to identify code block groups requiring retransmission (Kern: ¶¶ [0003-0008]).
Claims 22 and 32 are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Kern further in view of Lin et al. (US 2019/0132086 A1; hereinafter Lin).
Regarding claims 22 and 32, Huang and Kern do not explicitly teach wherein the second bit sequence is obtained based on a second check matrix.
In analogous art, Lin teaches wherein the second bit sequence (read as sub check codeword with 400 bits) is obtained based on a second check matrix (¶ [0163] When a codeword group is 100 bits, if the transmitting apparatus encodes the codeword group by using the second check matrix, a sub check codeword with 400 bits may be obtained.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the data retransmission method as taught by Lin with error correction and error detection as taught by Kern and data error verification as taught by Huang. One would have been motivated to do so in order to increase reliability and reduce retransmission overhead by using Kern’s syndrome based processing to detect and correct bit errors, Huang’s verification to identify groups containing remaining errors, and Lin’s partial check codeword retransmission to recover those groups with less transmitted data (Lin: ¶¶ [0002]-[0006]).
Allowable Subject Matter
Claims 23-27 and 34-37 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chen et al. (US 2016/0043829 A1) discloses “Devices and Methods for Data Recovery of Control Channels in Wireless Communications”
Song et al. (US 2017/0134051 A1) discloses “Decoding Method, Decoding Apparatus, and Decoder”
Watanabe (US 2006/0059403 A1) discloses “Quantum Key Distribution Method and Communication Device”
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID M KAYAL whose telephone number is (703)756-4576. The examiner can normally be reached M-F 8:30-5:30 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ricky Ngo can be reached at 571-272-3139. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.M.K./Examiner, Art Unit 2464
/RICKY Q NGO/Supervisory Patent Examiner, Art Unit 2464
