DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The 112 rejection of Claims 1-7 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention has been withdrawn in view of Applicant’s amendments.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over Shimizu [US 10,249,381] in view of Dubois et al. [“Memory Access Dependencies in Shared Memory Multiprocessors”, IEEE TSE Vol .16, No. 6, June 1990]
Claim 1, Shimizu discloses a semiconductor device [Fig 1] comprising: a decoder circuit [11] determining a write-source processor [Col. 2, lines 44-58]; a write-enable setting storage circuit storing a write-enable setting that indicates a processor enabled to execute writing into each bit of a write-destination register [Col. 9, line 65- Col. 10, line 65]; a masking/merging circuit [data merged in buffer, Col. 9, line 65-Col. 10, line 18]; and a write-back circuit writing back the value to be written back into the write-destination register [Col. 9, line 29-48 and Col. 10, line 19-23]. Shimizu does not teach but Dubois et al. discloses a performing a masking process to generate for each bit of the write destination register, a value to be written back into the write destination register by selecting, based on the write enable setting and the determined write source processor, between i)write data supplied by the write source processor and ii) data already written in the corresponding bit of the write destination register [Dubois et al. “Hardware Synchronization and Communication Primitives”]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Shimizu to incorporate Dubois’ processor dependent write enable control in order to prevent unauthorized writes and ensure correct multiprocessor behavior.
Claim 2, Shimizu in view of Dubois et al. discloses the semiconductor device according to claim 1, wherein the decoder circuit receives a bus address and a bus slave selecting signal corresponding to the write-source processor as an input, the bus address includes a bit indicating the write-source processor, and the decoder circuit determines whether the bit included in the bus address and the bus slave selecting signal are equal to each other [Col. 9, line 65-Col. 10, line 23].
Claim 3, Shimizu in view of Dubois et al.discloses the semiconductor device according to claim 1, wherein, if a masking process on each bit of the write-destination register is invalid, the decoder circuit replaces the bit with a predetermined bit to generate a decode signal, or if the masking process on the bit is valid, the decoder circuit replaces the bit with a bit indicating the write-source processor to generate the decode signal [read data corrected or not corrected, Col. 6, lines 24-28]. Shimizu does not teach but Dubois et al. discloses that for each bit of the write destination register if the masking process is not to be executed, the decoder circuit generates a corresponding portion of a decode signal replacing information associated with the bit with a predetermined pattern or if the masking process is to be executed, it generates the corresponding portion of the decode signal by replacing the information associated with the bit with bit patten [A. strong ordering of memory accesses].
Claim 4, Shimizu discloses the semiconductor device according to claim 3, wherein, if a condition in which the bit is equal to the predetermined bit or in which the bit indicating the write-source processor is equal to the write-enable setting is satisfied, the masking/merging circuit generates the value to be written back, on the basis of write data supplied from the write-source processor [Col. 7, lines 7-26], or if the condition is not satisfied, the masking/merging circuit generates the value to be written back, on the basis of data written in the write-destination register [Col. 7, lines 27-47]. Dubois et al. teaches processor dependent access control [B. Multiprocessor System with Distributed Global Memory].
Claim 5, Shimizu discloses the semiconductor device according to claim 1. Dubois et al. discloses the write source processor being privileged such that the marking process is not to be executed, a bus address and write data from the write source processor are output to a write-destination module without passing through the masking merging circuit [D. Multiprocessor Systems with Combining Networks].
Claim 6 is rejected using the same rationale as Claim 1.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
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/MIDYS ROJAS/ Primary Examiner, Art Unit 2133
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