DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/21/2024 was considered by the examiner.
Drawings
The drawings received on 10/21/2024 have been accepted by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, the claimed “determining a write-source processor” renders the claim indefinite because it is not clear what about the processor is being determined. Is this refereeing to the act of determining something about the processor, the act of identifying the processor, the act of selecting a processor or some other action? Clarification is required. Additionally, the claimed “masking/merging circuit” is also indefinite since it is not clear what this element’s function is. It is not clear at what point this circuit is masking or merging. Further Clarification is required.
Claim 3, the claimed limitations regarding valid or invalid bits is unclear since it is not clearly defined what is being evaluated for validity nor is it clear what constitutes validity. Is this determination being made at the register level or the per bit level? Clarification is required.
Claim 4, the limitations drawn to a condition being satisfied are indefinite because the condition itself is not clear. It is not clear what bit is being evaluated or what it is being compared to. Clarification is required.
Claim 5, the claimed “if the write source processor is privilege” is indefinite because in this case the term privilege is ambiguous. It is not clear what privilege means in this instance, how privilege is being determined nor the specifics of said privilege. Additionally, the claimed “…are output without through the masking/merging circuit” is unclear and it is not understood what this limitation refers to. Clarification is required.
Claim 6, the claimed “determining a write-source processor” renders the claim indefinite because it is not clear what about the processor is being determined. Is this refereeing to the act of determining something about the processor, the act of identifying the processor, the act of selecting a processor or some other action? Clarification is required.
Claim 7, the claimed “if the write source processor is privilege” is indefinite because in this case the term privilege is ambiguous. It is not clear what privilege means in this instance, how privilege is being determined nor the specifics of said privilege. Additionally, the claimed “…are output without through the step of generating the value to be written back” is unclear and it is not understood what this limitation refers to. Clarification is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, and 6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shimizu [US 10,249,381].
Claim 1, Shimizu discloses a semiconductor device [Fig 1] comprising: a decoder circuit [11] determining a write-source processor [Col. 2, lines 44-58]; a write-enable setting storage circuit storing a write-enable setting that indicates a processor enabled to execute writing into each bit of a write-destination register [Col. 9, line 65- Col. 10, line 65]; a masking/merging circuit generating a value to be written back into the write-destination register on the basis of the write-enable setting and the write-source processor [data merged in buffer, Col. 9, line 65-Col. 10, line 18]; and a write-back circuit writing back the value to be written back into the write-destination register [Col. 9, line 29-48 and Col. 10, line 19-23].
Claim 2, Shimizu discloses the semiconductor device according to claim 1, wherein the decoder circuit receives a bus address and a bus slave selecting signal corresponding to the write-source processor as an input, the bus address includes a bit indicating the write-source processor, and the decoder circuit determines whether the bit included in the bus address and the bus slave selecting signal are equal to each other [Col. 9, line 65-Col. 10, line 23].
Claim 3, Shimizu discloses the semiconductor device according to claim 1, wherein, if a masking process on each bit of the write-destination register is invalid, the decoder circuit replaces the bit with a predetermined bit to generate a decode signal, or if the masking process on the bit is valid, the decoder circuit replaces the bit with a bit indicating the write-source processor to generate the decode signal [read data corrected or not corrected, Col. 6, lines 24-28].
Claim 4, Shimizu discloses the semiconductor device according to claim 3, wherein, if a condition in which the bit is equal to the predetermined bit or in which the bit indicating the write-source processor is equal to the write-enable setting is satisfied, the masking/merging circuit generates the value to be written back, on the basis of write data supplied from the write-source processor [Col. 7, lines 7-26], or if the condition is not satisfied, the masking/merging circuit generates the value to be written back, on the basis of data written in the write-destination register [Col. 7, lines 27-47].
Claim 6 is rejected using the same rationale as Claim 1.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Takeda et al. [US 2020/0089567]; Memory System. Abstract and Fig 1.
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/MIDYS ROJAS/ Primary Examiner, Art Unit 2133