DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-6, 11, 15-17, and 23 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Stevenson et al. [US 20190290920 A1].
Regarding Claim 1, Stevenson discloses a hermetically sealed filtered feedthrough for an active implantable medical device AIMD, the filtered feedthrough comprising: a) an electrically conductive ferrule (112, Fig 21A) comprising a ferrule opening (306) extending to a ferrule device side spaced from a ferrule body fluid side [0038]; b) an electrically non-conductive insulator (160) comprising an insulator outer surface extending to an insulator device side (314) spaced from an insulator body fluid side (312) [0038], wherein the insulator (160) disposed in the ferrule opening (306) is hermetically sealed to the ferrule (112) by a first gold braze (150, Fig 22) so that when the ferrule (112) is attached to an opening in a housing (116) of an AIMD (100), the ferrule (112) and insulator body fluid sides (312), and the ferrule (112) and insulator device sides (314) reside outside and inside the AIMD (100), respectively, and wherein at least two insulator via holes (316) extend to the insulator device and body fluid sides (314 and 312); c) an insulator metallization (142, 144) disposed in the two insulator via holes (316); d) first and second terminal pins (active conductive pathways 111,114,117,185, and 186, synonymous to pin, see [0005]) residing in a respective one of the at least two insulator via holes (316) where a second gold braze (162) hermetically seals the terminal pin to the insulator metallization (the active conductive pathways are hermetically sealed to the insulator by a gold braze, see [0025, 0051]), wherein the first and second terminal pins (active conductive pathways 111,114,117,185, and 186) extend to a terminal pin first end spaced from a terminal pin second end, and wherein at least the first and second terminal pin first ends extend outwardly beyond the insulator device side (see Fig 21F, pins 111); e) a filter capacitor (132) disposed at or adjacent to the insulator device side, the filter capacitor (132) comprising: i) a capacitor dielectric (147) comprising a dielectric outer surface (322) extending to a dielectric first major face (326) spaced from a dielectric second major face (324) [see, 0038]; ii) at least one active electrode plate (148) and at least one ground electrode plate (146) supported in the capacitor dielectric (147) in an interleaved, partially overlapping capacitive relationship [see, 0038]; iii) first and second dielectric passageways (at least one passageway 134) extending through the capacitor dielectric (147); iv) a capacitor internal metallization (144) disposed in the first and second dielectric passageways (134), wherein the at least one active electrode plate (148) is connected to the capacitor internal metallization (144) in the first and second dielectric passageways (134), and wherein the outwardly extending first and second terminal pin (111) first ends reside in the respective first and second dielectric passageways (134) where the terminal pins (111) are conductively connected to the capacitor internal metallization (144) connected to the at least one active electrode plate (148) by a first conductive material (156), and wherein the at least one ground electrode plate (146) is in a non- conductive relation with the capacitor internal metallization (144) in the first and second dielectric passageways (134; see, [0020]); and v) a capacitor external metallization (142) disposed on a terminated dielectric outer surface portion (see Fig 33), but not on an unterminated dielectric outer surface portion of the dielectric outer surface (see Fig 33), wherein the at least one ground electrode plate (146) is conductively connected to the capacitor external metallization (142) at the terminated dielectric outer surface portion, and wherein the at least one active electrode plate (148) is in a non-conductive relation with the capacitor external metallization (four active electrodes 148 that are each individually associated with one of the four passageways, the ground electrode layer 146 extends in non-conductive relationship with the active passageways to the feedthrough capacitors outside diameter; see [0020]; and f) a second conductive material (152) connecting the capacitor external metallization (142) at the terminated dielectric outer surface portion to a gold bond pad (248, 250; see Fig 24) supported on the ferrule device side (see [0041]) or to the first braze sealing the insulator (160) to the ferrule (112) at the ferrule device side to provide a system ground for the filtered feedthrough (see [0038-0041].
Regarding Claim 2, Stevenson discloses all the limitations of claim 1, Stevenson further discloses the at least one ground electrode plate (146) does not extend to the unterminated dielectric outer surface portion of the capacitor dielectric (147, see Fig 22B).
Regarding Claim 3, Stevenson discloses all the limitations of claim 1, Stevenson further discloses the at least one active electrode plate (148) does not extend to the dielectric outer surface.
Regarding Claim 4, Stevenson discloses all the limitations of claim 1, Stevenson further discloses a) the ferrule (112) has a rectangular shape (Fig 21A) so that in a plan view looking at the ferrule device side, opposed ferrule (112) first and second longitudinal side walls extend to and meet with opposed ferrule third and fourth end walls, wherein the first and second longitudinal sidewalls are aligned parallel to and on opposite sides of a ferrule center line that bisects the opposed third and fourth end walls (see Fig 21A); and b) the insulator (160) hermetically sealed to the ferrule (112) in the ferrule opening (306) has opposed insulator first and second longitudinal side walls that extend to and meet with opposed insulator third and fourth end walls so that in a plan view, the shape of the insulator (160) matches the shape of the ferrule opening (306), wherein the at least two insulator via holes (316) supporting the insulator metallization (142, 144) connected to the first and second terminal pins (111) reside between the insulator (160) second longitudinal side wall and the ferrule (112) center line (see Fig 21A-21F).
Regarding Claim 5, Stevenson discloses all the limitations of claim 4, Stevenson further discloses the first and second terminal pins (111) in a respective one of the at least two insulator via holes (316) are aligned parallel to the insulator (160) second longitudinal side wall and the ferrule (112) center line.
Regarding Claim 6, Stevenson discloses all the limitations of claim 1, Stevenson further discloses the ferrule (112) could be an oval shape (see [0046]; claim 9) comprising opposed ferrule first and second longitudinal side walls that extend to and meet with opposed ferrule third and fourth curved end walls, and wherein the insulator hermetically sealed to the ferrule in the ferrule opening comprises opposed insulator first and second longitudinal side walls that extend to and meet with opposed insulator third and fourth curved end walls so that in a plan view, the shape of the insulator matches the shape of the ferrule opening (306).
Regarding Claim 11, Stevenson discloses all the limitations of claim 1, Stevenson further discloses the first conductive material conductively (156) connecting the outwardly extending first and second terminal pin (111) first ends to the capacitor internal metallization (144) connected to the at least one active electrode plate (148) and the second conductive material (152) connecting the capacitor external metallization (142) at the terminated dielectric outer surface portion to the first braze sealing the insulator (160) to the ferrule (112) are individually selected from the group consisting of a solder, a solder BGA, a solder paste, an epoxy, and a polyimide (thermal-setting conductive adhesive or a solder or the like, see [0028]).
Regarding Claim 15, Stevenson discloses all the limitations of claim 1, Stevenson further discloses an insulative washer can be disposed between the insulator (160) and the filter capacitor (132) (see 0157]).
Regarding Claim 16, Stevenson discloses all the limitations of claim 1, Stevenson further discloses the ferrule (112) is configured to be attachable to a housing (116) of an active implantable medical device (100) by a laser weld (see [0015])
Regarding Claim 17, Stevenson discloses all the limitations of claim 1, Stevenson further discloses the ferrule (112) is a continuous part of an active implantable medical device housing (116) [0015].
Regarding Claim 23, A hermetically sealed filtered feedthrough for an active implantable medical device AIMD, the filtered feedthrough comprising: a) an electrically conductive ferrule (112, Fig 21A) comprising a ferrule opening (306) extending to a ferrule device side spaced from a ferrule body fluid side [0038]; b) an electrically non-conductive insulator (160) comprising an insulator outer surface extending to an insulator device side (314) spaced from an insulator body fluid side (312) [0038], wherein the insulator (160) disposed in the ferrule opening (306) is hermetically sealed to the ferrule (112) by a first gold braze (150, Fig 22) so that when the ferrule (112) is attached to an opening in a housing (116) of an AIMD (100), the ferrule (112) and insulator body fluid sides (312), and the ferrule (112) and insulator device sides (314) reside outside and inside the AIMD (100), respectively, and wherein at least two insulator via holes (316) extend to the insulator device and body fluid sides (314 and 312); c) an insulator metallization (142, 144) disposed in the two insulator via holes (316); d) first and second terminal pins (active conductive pathways 111,114,117,185, and 186, synonymous to pin, see [0005]) residing in a respective one of the at least two insulator via holes (316) where a second gold braze (162) hermetically seals the terminal pin to the insulator metallization (the active conductive pathways are hermetically sealed to the insulator by a gold braze, see [0025, 0051]), wherein the first and second terminal pins (active conductive pathways 111,114,117,185, and 186) extend to a terminal pin first end spaced from a terminal pin second end, and wherein at least the first and second terminal pin first ends extend outwardly beyond the insulator device side (see Fig 21F, pins 111); e) a filter capacitor (132) disposed at or adjacent to the insulator device side, the filter capacitor (132) comprising: i) a capacitor dielectric (147) comprising a dielectric outer surface (322) extending to a dielectric first major face (326) spaced from a dielectric second major face (324) [see, 0038]; ii) at least one active electrode plate (148) and at least one ground electrode plate (146) supported in the capacitor dielectric (147) in an interleaved, partially overlapping capacitive relationship [see, 0038]; iii) first and second dielectric passageways (at least one passageway 134) extending through the capacitor dielectric (147); iv) a capacitor internal metallization (144) disposed in the first and second dielectric passageways (134), wherein the at least one active electrode plate (148) is connected to the capacitor internal metallization (144) in the first and second dielectric passageways (134), and wherein the outwardly extending first and second terminal pin (111) first ends reside in the respective first and second dielectric passageways (134) where the terminal pins (111) are conductively connected to the capacitor internal metallization (144) connected to the at least one active electrode plate (148) by a first conductive material (156), and wherein the at least one ground electrode plate (146) is in a non- conductive relation with the capacitor internal metallization (144) in the first and second dielectric passageways (134; see, [0020]); and v) a capacitor external metallization (142) disposed on at least a portion of the dielectric outer surface to provide a terminated dielectric outer surface portion (see Fig 33) comprising first and second segments of the terminated dielectric outer surface portion, wherein the at least one ground electrode plate (146) extends to the first segment of the terminated dielectric outer surface portion, but the at least one ground electrode plate (146) does not extend to the second segment of the terminated dielectric outer surface portion, and wherein the at least one active electrode plate (148) is in a non-conductive relation with the capacitor external metallization (142, four active electrodes 148 that are each individually associated with one of the four passageways, the ground electrode layer 146 extends in non-conductive relationship with the active passageways to the feedthrough capacitors outside diameter; see [0020]; and f) a second conductive material (152) connecting the capacitor external metallization (142) at the terminated dielectric outer surface portion to a gold bond pad (248, 250; see Fig 24) supported on the ferrule device side (see [0041]) or to the first braze sealing the insulator (160) to the ferrule (112) to provide a system ground for the filtered feedthrough (see [0038-0041].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Stevenson et al. [US 20190290920 A1] in view of Stevenson et al. [US 20190001123 A1].
Regarding Claim 13, Stevenson discloses all the limitations of claim 1, Stevenson does not explicitly disclose the at least one active electrode plate comprises a closely-spaced pair of active electrode plates and the at least one ground electrode plate comprises a closely- spaced pair of ground electrode plates.
However, Stevenson et al. [US 20190001123 A1] discloses at least one active electrode plate (212, see Fig 35-36) comprises a closely-spaced pair of active electrode plates and the at least one ground electrode plate (214) comprises a closely- spaced pair of ground electrode plates.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Stevenson as suggested by Stevenson to provide the at least one active electrode plate comprises a closely-spaced pair of active electrode plates and the at least one ground electrode plate comprises a closely- spaced pair of ground electrode plates. Doing so would drive down electrode plate resistance as recognized by Stevenson (see [0208]).
Allowable Subject Matter
Claims 18-22 allowed.
Regarding Claim 18, A hermetically sealed filtered feedthrough for an active implantable medical device (AIMD), the filtered feedthrough comprising: a) an electrically conductive ferrule (112, Fig 21A) comprising a ferrule opening (306) extending to a ferrule device side spaced from a ferrule body fluid side [0038]; b) an electrically non-conductive insulator (160) comprising an insulator outer surface extending to an insulator device side (314) spaced from an insulator body fluid side (312) [0038], wherein the insulator (160) disposed in the ferrule opening (306) is hermetically sealed to the ferrule (112) by a first gold braze (150, Fig 22) so that when the ferrule (112) is attached to an opening in a housing (116) of an AIMD (100), the ferrule (112) and insulator body fluid sides (312), and the ferrule (112) and insulator device sides (314) reside outside and inside the AIMD (100), respectively, and wherein at least two insulator via holes (316) extend to the insulator device and body fluid sides (314 and 312); c) an insulator metallization (142, 144) disposed in the two insulator via holes (316); d) first and second terminal pins (active conductive pathways 111,114,117,185, and 186, synonymous to pin, see [0005]) residing in a respective one of the at least two insulator via holes (316) where a second gold braze (162) hermetically seals the terminal pin to the insulator metallization (the active conductive pathways are hermetically sealed to the insulator by a gold braze, see [0025, 0051]), wherein the first and second terminal pins (active conductive pathways 111,114,117,185, and 186) extend to a terminal pin first end spaced from a terminal pin second end, and wherein at least the first and second terminal pin first ends extend outwardly beyond the insulator device side (see Fig 21F, pins 111); e) a filter capacitor (132) disposed at or adjacent to the insulator device side, the filter capacitor (132) comprising: i) a capacitor dielectric (147) comprising a dielectric outer surface (322) extending to a dielectric first major face (326) spaced from a dielectric second major face (324) [see, 0038], wherein, in a plan view (see Fig 21F) looking at the dielectric first major face (326), the capacitor dielectric (147) has a rectangular shape comprising opposed dielectric first and second long sides extending to and meeting with opposed dielectric third and fourth short ends; ii) at least one active electrode plate (148) and at least one ground electrode plate (146) supported in the capacitor dielectric (147) in an interleaved, partially overlapping capacitive relationship [see, 0038]; iii) first and second dielectric passageways (at least one passageway 134) extending through the capacitor dielectric (147); iv) a capacitor internal metallization (144) disposed in the first and second dielectric passageways (134), wherein the at least one active electrode plate (148) is connected to the capacitor internal metallization (144) in the first and second dielectric passageways (134), and wherein the outwardly extending first and second terminal pin (111) first ends reside in the respective first and second dielectric passageways (134) where the terminal pin (111) is conductively connected to the capacitor internal metallization (144) connected to the at least one active electrode plate (148) by a first conductive material (156), and wherein the at least one ground electrode plate (146) is in a non- conductive relation with the capacitor internal metallization (144) in the dielectric passageway (134; see, [0020]) and v) a capacitor external metallization (142) disposed on a terminated dielectric outer surface portion (see Fig 33), but not on an unterminated dielectric outer surface portion of the dielectric outer surface (see Fig 33), wherein the at least one ground electrode plate (146) extends to the dielectric first long side comprising the terminated dielectric outer surface portion, the at least one ground electrode plate (146) is conductively connected to the capacitor external metallization (142) at the terminated dielectric outer surface portion, and wherein the at least one active electrode plate (148) is in a non- conductive relation with the capacitor external metallization (142) (four active electrodes 148 that are each individually associated with one of the four passageways, the ground electrode layer 146 extends in non-conductive relationship with the active passageways to the feedthrough capacitors outside diameter; see [0020]; and f) a second conductive material (152) connecting the capacitor external metallization (142) at the terminated dielectric outer surface portion to a gold bond pad (248, 250; see Fig 24) supported on the ferrule device side (see [0041]) or to the first braze sealing the insulator (160) to the ferrule (112) to provide a system ground for the filtered feedthrough (see [0038-0041]. Stevenson and the prior art of record do not explicitly disclose the ground electrode plate (146) does not extend to the second long side comprising the unterminated dielectric outer surface portion of the capacitor dielectric, along with all other limitations of claim 18.
Claims 19-22 are allowable as they are dependent on claim 18.
Claims 7-10, 12, and 24-25 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 7, Stevenson discloses all the limitations of claim 1, Stevenson further discloses in a plan view looking at the dielectric first major face (326), the capacitor dielectric (147) has a rectangular shape comprising opposed dielectric first and second long sides extending to and meeting with opposed dielectric third and fourth short ends, and wherein the at least one ground electrode plate (146) extends to the dielectric first long side comprising the terminated dielectric outer surface portion, the ground metallization 142 is brought out to both of the long sides of the feedthrough capacitor 132 [0023]. Stevenson and the prior art of record do not explicitly disclose the ground electrode plate (146) does not extend to any of the second long side and the third and fourth short ends comprising the unterminated dielectric outer surface portion of the capacitor dielectric (147), along with all other limitations of claim 7 and 1.
Regarding Claim 8, Stevenson discloses all the limitations of claim 1, Stevenson further discloses in a plan view looking at the dielectric first major face (326), the capacitor dielectric (147) has a rectangular shape comprising opposed dielectric first and second long sides extending to and meeting with opposed dielectric third and fourth short ends, and wherein the at least one ground electrode plate (146) extends to the first long side. Stevenson does not explicitly disclose the ground plate extends to at least one of the third and fourth short ends comprising the terminated dielectric outer surface portion, but the ground electrode plate does not extend to the second long side comprising the unterminated dielectric outer surface portion of the capacitor dielectric, along with all other limitations of claim 1 and 8.
Regarding Claim 9, Stevenson discloses all the limitations of claim 1, Stevenson further discloses the capacitor dielectric (147) could be a square shape comprising opposed dielectric first and second sides extending to and meeting with opposed dielectric third and fourth sides, the dielectric first and second sides being substantially equal in length to the dielectric third and fourth sides, and wherein the at least one ground electrode plate (146) extends to the dielectric first side comprising the terminated dielectric outer surface portion [0023]. Stevenson further discloses Stevenson does not explicitly disclose the ground electrode plate does not extend to any of the dielectric second, third and fourth sides comprising the unterminated dielectric outer surface portion of the capacitor dielectric, along with all other limitations of claim 9 and 1.
Regarding Claim 10, Stevenson discloses all the limitations of claim 1, Stevenson further discloses the capacitor dielectric (147) could be a square shape comprising opposed dielectric first and second sides extending to and meeting with opposed dielectric third and fourth sides, the dielectric first and second sides being substantially equal in length to the dielectric third and fourth sides, and wherein the at least one ground electrode plate (146) extends to the dielectric first side. Stevenson does not explicitly disclose the ground plate extends to at least one of the third and fourth sides comprising the terminated dielectric outer surface portion, but the ground electrode plate does not extend to the dielectric second side comprising the unterminated dielectric outer surface portion of the capacitor dielectric, along with all other limitations of claim 10 and 1.
Regarding Claim 12, Stevenson discloses all the limitations of claim 1, Stevenson further discloses the second conductive material (152) connecting the capacitor external metallization (142) to the gold bond pad (248, 250) supported on the ferrule device side or to the first braze sealing the insulator (160) to the ferrule (112) . Stevenson does not explicitly disclose a plurality of second conductive material connections at spaced intervals along the capacitor external metallization disposed on the terminated dielectric outer surface portion of the dielectric outer surface, along with all other limitations of claim 12 and 1.
Regarding Claim 24, Stevenson and the prior art of record do not explicitly disclose the at least one ground electrode plate does not extend to the second long side of the capacitor dielectric as the second segment of the terminated dielectric outer surface portion, along with all other limitations of claim 24 and 23.
Claim 25 objected to as it is dependent on claim 24.
Conclusion
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/T.R./Examiner, Art Unit 2834
/TULSIDAS C PATEL/Supervisory Patent Examiner, Art Unit 2834
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