DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note
It is noted that any citations to specific, pages, columns, lines, or figures in the prior art references and any interpretation of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP § 2123.
Claim Status
Claims 1-9 are currently pending. Claims 1, 4, and 7 are amended as per Applicant’s amendment filed on 27 February 2026.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-9 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
The amended claims are addressed in the rejections below further in view of Huang (US 20190278940 A1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Isozaki (US 20220261166 A1) in view of Huang (US 20190278940 A1).
Referring to claims 1, 4, and 7, taking claim 1 as exemplary, Isozaki teaches
A method for data management in a non-volatile storage device ([Isozaki 0042] The storage module 34 includes a large-capacity nonvolatile storage medium such as a flash memory or a hard disk. The storage module 34 receives a read command or a write command from the host device 14, and writes or reads data.) comprising: configuring a logical unit in the non-volatile storage device to automatically erase data stored in the logical unit during a boot up process; ([Isozaki abstract, 0064-0066, Fig. 5A] Prior to reset, the host device 14 transfers, to the storage device 12, a data erasure mechanism indicator request to inquire the data erasure mechanism supported by the storage device 12. For example, this request is transferred when the host device 14 is booted.) reserving a logical space of the logical unit for one or more applications installed on a host system ([Isozaki abstract, 0032, 0105-0106, 0109, Fig. 13] FIG. 1 shows examples of connection between a storage device 12 and a host device 14 according to a first embodiment. the storage device 12 includes a plurality of namespaces, and each namespace includes a plurality of ranges, when the host device 14 merely gives a data erase command in namespace units, the storage device 12 is capable of easily erasing the data of all the ranges included in the specified namespace(s). As the host device 14 does not need to manage the relationship between namespaces and ranges, the structure of the application program of the host device 14 is simplified. Thus, the cost can be reduced. FIG. 13 schematically shows the storage area of the storage device 12. Namespaces are defined in NVM Express, Revision 1.3, May 1, 2017. A namespace is a quantity of nonvolatile memory that may be formatted into logical blocks. A namespace is each of the partial areas into which the entire storage area of the storage device 12 is divided, and is specifically, a collection of logical blocks. At least one namespace identified by a namespace ID can be defined for a single storage device. A namespace of size “n” includes logical blocks with logical block addresses 0 to “n−1.” A namespace global range is provided in each namespace. Each namespace global range includes a plurality of ranges. As described above, different PINs can be set for the ranges, respectively. A global range ranges over a plurality of namespaces.).
Isozaki does not explicitly disclose and automatically erasing the data stored in the logical unit during the boot up process.
Huang teaches and automatically erasing the data stored in the logical unit during the boot up process ([Huang abstract, 0027, 0031, 0034, 0045] A computing device is described herein that automatically enters a data protection mode in response to the detected presence or absence of certain user input and/or user input behaviors during a device boot-up state, a user login state, or a device shut-down state. during device boot-up, user login, or device shut-down to avoid triggering the data protection mode, such mode will be activated thereby causing sensitive data to be automatically hidden or delete. Examples of such data protection responses include one or more of: a hard delete, where data marked as sensitive is automatically deleted from the device without any option for recovery).
Isozaki and Huang are analogous art because they are from the same field of endeavor in storage devices. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Isozaki and Huang before him or her to modify the storage device of Isozaki to include the data protection mode of Huang, thereafter the storage device is connected to data protection mode. The suggestion and/or motivation for doing so would be obtaining the advantage of allowing the storage device have more control of what data is retained or remains accessible during the boot up process as suggested by Huang. It is known to combine prior art elements according to known methods to yield predictable results. Therefore, it would have been obvious to combine Isozaki with Huang to obtain the invention as specified in the instant application claims.
With regards to the non-exemplary limitations of claim 4, Isozaki teaches. A method for data management in a non-volatile storage device comprising: detecting whether a logical unit in the non-volatile storage device is configured to automatically erase data stored in the logical unit during a boot up process; and un-mapping the data stored in the logical unit based on detecting that the logical unit is configured to automatically erase data stored in the logical unit in the non-volatile storage device ([Isozaki 0040, 0064-0066, 0069, claim 7, Figs. 5A-5B, 7A-C] Prior to reset, the host device 14 transfers, to the storage device 12, a data erasure mechanism indicator request to inquire the data erasure mechanism supported by the storage device 12. For example, this request is transferred when the host device 14 is booted. The at least one data erasure mechanism comprises an overwrite erasure mechanism, a block erasure mechanism, or an unmap. For example, the data erasure mechanisms include overwrite data erasure, block erasure, unmap, reset write pointers and crypto erasure (encryption key updating). In overwrite data erasure, the area in which the data to be erased is stored is overwritten with “0” or data generated by random numbers. Block erasure disables the original written data of the entire block including the user data to be erased from being read. In unmap, a mapping table indicating in which block of the storage medium user data is stored is reset regarding the user data. In reset write pointers, a pointer indicating in which block of the storage medium user data is stored is reset. In crypto erasure, when input user data is encrypted with a key provided in the storage device 12, and the encrypted data is stored in the storage module 34, the key used for the data encryption is eradicated. In this way, the encrypted data cannot be decrypted, and thus, the input data is invalidated. Data erasure mechanism is allocated to the respective bits of Byte 4 as shown in FIG. 7C. When each bit is “1”, its data erasure mechanism is supported. When each bit is “0”, its data erasure mechanism is not supported. For example, when bit 0 of Feature Descriptor data is “1”, overwrite data erasure is supported. When bit 1 is “1”, block erasure is supported. When bit 2 is “1”, unmap is supported. When bit 3 is “1”, reset write pointers are supported. When bit 4 is “1”, encryption key updating (crypto erasure) is supported.).
With regards to the non-exemplary limitations of claim 7, Isozaki teaches and a control circuitry coupled with the non-volatile storage device, the control circuitry configured to instruct the non-volatile storage device to: ([Isozaki 0034, 0038-0039, 0105] FIG. 2 shows an example of the configuration of the storage device 12. The storage device 12 includes an interface (I/F) processor 22 which is connected to the host device 14 via a host I/F (not shown). An authentication processor 102, authorization processor 104, data erasure mechanism indicator module 106, and data erasure mechanism indicator request reception module 108 are connected to the I/F processor 22. the storage module 34 managed by the area information manager 114. The data erasure mechanism indicator request reception module 108 and an erase information manager 124 are connected to the data erasure mechanism indicating module 106.).
Referring to claims 2 and 8, taking claim 2 as exemplary, Isozaki in view of Huang teaches
The method of claim 1, further comprises storing data corresponding to the one or more applications in the logical space of the logical unit ([Isozaki abstract, 0032, 0105-0106, 0109, Fig. 13] FIG. 1 shows examples of connection between a storage device 12 and a host device 14 according to a first embodiment. the storage device 12 includes a plurality of namespaces, and each namespace includes a plurality of ranges, when the host device 14 merely gives a data erase command in namespace units, the storage device 12 is capable of easily erasing the data of all the ranges included in the specified namespace(s). As the host device 14 does not need to manage the relationship between namespaces and ranges, the structure of the application program of the host device 14 is simplified. Thus, the cost can be reduced. FIG. 13 schematically shows the storage area of the storage device 12. Namespaces are defined in NVM Express, Revision 1.3, May 1, 2017. A namespace is a quantity of nonvolatile memory that may be formatted into logical blocks. A namespace is each of the partial areas into which the entire storage area of the storage device 12 is divided, and is specifically, a collection of logical blocks. At least one namespace identified by a namespace ID can be defined for a single storage device. A namespace of size “n” includes logical blocks with logical block addresses 0 to “n−1.” A namespace global range is provided in each namespace. Each namespace global range includes a plurality of ranges. As described above, different PINs can be set for the ranges, respectively. A global range ranges over a plurality of namespaces.).
Referring to claims 3 and 9, taking claim 3 as exemplary, Isozaki in view of Huang teaches
The method of claim 1, wherein the configuring the logical unit in the non-volatile storage device comprises: adding an auto-erase flag to the logical unit in the non-volatile storage device, the auto-erase flag indicating that the data stored in the logical unit are to be discarded during the boot up process after a power reset ([Isozaki 0039, 0064-0066, 0069, Figs. 5A-B, 7A-C] The data erasure mechanism indicator request reception module 108 and an erase information manager 124 are connected to the data erasure mechanism indicating module 106. The data erasure mechanism indicator request reception module 108 receives an inquiry about data erasure mechanisms from the host device 14, and transfers it to the data erasure mechanism indicating module 106. The data erasure mechanism indicating module 106 shows the data erasure mechanisms supported by the storage device 12 to the host device 14. Prior to reset, the host device 14 transfers, to the storage device 12, a data erasure mechanism indicator request to inquire the data erasure mechanism supported by the storage device 12. For example, this request is transferred when the host device 14 is booted. The data erasure mechanism indicator request received in the data erasure mechanism indicator request reception module 108 is transferred to the data erasure mechanism indicating module 106. In step 50A, the data erasure mechanism indicating module 106 obtains, from the erase information manager 124, information indicating one or more erasure mechanisms supported by the storage device 12. The data erasure mechanism indicating module 106 sends back data erasure mechanism response information indicating the obtained data erasure mechanism(s) to the host device 14. Data erasure mechanism is allocated to the respective bits of Byte 4 as shown in FIG. 7C. When each bit is “1”, its data erasure mechanism is supported. When each bit is “0”, its data erasure mechanism is not supported. For example, when bit 0 of Feature Descriptor data is “1”, overwrite data erasure is supported. When bit 1 is “1”, block erasure is supported. When bit 2 is “1”, unmap is supported. When bit 3 is “1”, reset write pointers are supported. When bit 4 is “1”, encryption key updating (crypto erasure) is supported.).
Referring to claim 5, Isozaki in view of Huang teaches
The method of claim 4, wherein the detecting that the logical unit of the non-volatile storage device is configured to automatically erase the data stored in the logical unit comprises: identifying whether an auto-erase flag is added to the logical unit in the non-volatile storage device by a host system, the auto-erase flag indicating that the data stored in the logical unit are to be discarded during the boot up process after a power reset ([Isozaki 0039, 0064-0066, 0069, Figs. 5A-B, 7A-C] The data erasure mechanism indicator request reception module 108 and an erase information manager 124 are connected to the data erasure mechanism indicating module 106. The data erasure mechanism indicator request reception module 108 receives an inquiry about data erasure mechanisms from the host device 14, and transfers it to the data erasure mechanism indicating module 106. The data erasure mechanism indicating module 106 shows the data erasure mechanisms supported by the storage device 12 to the host device 14. Prior to reset, the host device 14 transfers, to the storage device 12, a data erasure mechanism indicator request to inquire the data erasure mechanism supported by the storage device 12. For example, this request is transferred when the host device 14 is booted. The data erasure mechanism indicator request received in the data erasure mechanism indicator request reception module 108 is transferred to the data erasure mechanism indicating module 106. In step 50A, the data erasure mechanism indicating module 106 obtains, from the erase information manager 124, information indicating one or more erasure mechanisms supported by the storage device 12. The data erasure mechanism indicating module 106 sends back data erasure mechanism response information indicating the obtained data erasure mechanism(s) to the host device 14. Data erasure mechanism is allocated to the respective bits of Byte 4 as shown in FIG. 7C. When each bit is “1”, its data erasure mechanism is supported. When each bit is “0”, its data erasure mechanism is not supported. For example, when bit 0 of Feature Descriptor data is “1”, overwrite data erasure is supported. When bit 1 is “1”, block erasure is supported. When bit 2 is “1”, unmap is supported. When bit 3 is “1”, reset write pointers are supported. When bit 4 is “1”, encryption key updating (crypto erasure) is supported.).
Referring to claim 6, Isozaki in view of Huang teaches
The method of claim 4, wherein based on a detection that the logical unit in the non-volatile storage device is not configured to automatically erase the data stored in the logical unit, the boot up process is completed without un-mapping the data ([Isozaki 0039-0040, 0064-0066, 0069, 0071, Figs. 5A-B, 7A-C] the data erasure mechanisms include overwrite data erasure, block erasure, unmap, reset write pointers and crypto erasure (encryption key updating). In step 50A, the data erasure mechanism indicating module 106 obtains, from the erase information manager 124, information indicating one or more erasure mechanisms supported by the storage device 12. The data erasure mechanism indicating module 106 sends back data erasure mechanism response information indicating the obtained data erasure mechanism(s) to the host device 14. The data erasure mechanism specification information received in the storage device 12 is transferred to the authentication processor 102. The authentication processor 102 performs authentication process of the user who issues Set command specifying the data erasure mechanism in step 50B. When the data erasure mechanism specified by the host device 14 is supported by the storage device 12 (YES in step 50C-1), the erase information manager 124 sets the data erasure mechanism specified by the host device 14 in the erase processor 118 in step 50E. Data erasure mechanism is allocated to the respective bits of Byte 4 as shown in FIG. 7C. When each bit is “1”, its data erasure mechanism is supported. When each bit is “0”, its data erasure mechanism is not supported. For example, when bit 0 of Feature Descriptor data is “1”, overwrite data erasure is supported. When bit 1 is “1”, block erasure is supported. When bit 2 is “1”, unmap is supported. When bit 3 is “1”, reset write pointers are supported. When bit 4 is “1”, encryption key updating (crypto erasure) is supported.).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Regarding memory reset and erase.
US 20050289289 A1
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FRANCISCO A GRULLON whose telephone number is (571)272-8318. The examiner can normally be reached Monday - Friday, 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at (571)272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FRANCISCO A GRULLON/Primary Examiner, Art Unit 2132
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