Prosecution Insights
Last updated: April 19, 2026
Application No. 18/921,783

PANEL DRIVING METHOD AND PANEL DRIVING SYSTEM

Final Rejection §103
Filed
Oct 21, 2024
Examiner
SHAH, SUJIT
Art Unit
2624
Tech Center
2600 — Communications
Assignee
Macroblock Inc.
OA Round
2 (Final)
66%
Grant Probability
Favorable
3-4
OA Rounds
2y 8m
To Grant
77%
With Interview

Examiner Intelligence

Grants 66% — above average
66%
Career Allow Rate
269 granted / 408 resolved
+3.9% vs TC avg
Moderate +11% lift
Without
With
+11.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
37 currently pending
Career history
445
Total Applications
across all art units

Statute-Specific Performance

§101
2.3%
-37.7% vs TC avg
§103
65.4%
+25.4% vs TC avg
§102
12.7%
-27.3% vs TC avg
§112
16.1%
-23.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 408 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-4, 6-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over You et al (US Pub 2022/0208057) in view of Kim et al (US Pub 2020/0324628). With respect to claim 1, You discloses a panel driving method, (par 0005; discloses the present disclosure may provide an infinitely expandable display apparatus and a driving method thereof) applied to a spliced display device comprising a plurality of panel modules (fig. 1; discloses a cabinet comprising plurality of display unit; par 0032; discloses the cabinet may include a plurality of display units connected to one another through an interface circuit), and the method comprising: by an image generation circuit, receiving an original image and scaling the original image to generate an initial image having an initial resolution (par 0036; discloses the panel driving circuit may include an application specific integrated circuit (ASIC); par 0054; discloses image data is output from the set board; par 0075; discloses the master display unit may check a resolution of an input image received from the set board,); by an image dispatch circuit, receiving the initial image and an application setting value and generating an advanced image having a terminal resolution (par 0037; discloses an ASIC of the master display unit may include an image scaler embedded therein, and thus, may perform an operation of calculating a physical resolution of each of the display units and an image scaling operation on the display units. Therefore, when a resolution mismatch between the set board and the display units occurs, the display units may reproduce a normal image even without changing an output resolution of the set board); by the image dispatch circuit, dividing the advanced image into a plurality of terminal images (par 0076; discloses each of the slave display units may divide the scaled image data into unit image data on the basis of corresponding coordinate information and may output the divided image data as a corresponding coordinate image (S35 and S36)); receiving the plurality of terminal images, respectively, and generating a plurality of panel driving signals corresponding to the plurality of terminal images; and outputting the plurality of panel driving signals to the plurality of panel modules, respectively, (par 0036; discloses the panel driving circuit may include an application specific integrated circuit (ASIC), a data driver, and a gate driver. Par 0055; discloses The ASIC may supply the data driver DIC with unit image data and timing control signals synchronized with the unit image data.) wherein generating the advanced image having the terminal resolution includes: determining whether a value of the initial resolution is equal to the application setting value, setting the initial image as the advanced image when determining the value of the initial resolution is equal to the application setting value (fig. 16; discloses when the resolution of the input image matches the resolution of the cabinet (i.e. left portion in fig. 16); image is displayed based on the input image resolution), scaling the initial image to generate the advanced image when determining the value of the initial resolution is not equal to the application setting value, and a value of the terminal resolution of the advanced image is equal to the application setting value (par 0075; discloses the master display unit may check a resolution of an input image received from the set board, and then, when the resolution of the input image does not match the total resolution of the cabinet, the master display unit may scale the resolution of the input image on the basis of the total resolution of the cabinet and may transfer the scaled image data to the slave display units (S31 to S34)); You doesn’t expressly disclose a plurality of timing controller, receiving the plurality of terminal images, respectively, and generating a plurality of panel driving signals corresponding to the plurality of terminal images; and by the plurality of timing controllers, outputting the plurality of panel driving signals to the plurality of panel modules, respectively; In the same field of endeavor, Kim discloses a tiled display system and control method (see abstract); Kim discloses a plurality of timing controller, receiving the plurality of terminal images, respectively, and generating a plurality of panel driving signals corresponding to the plurality of terminal images; and by the plurality of timing controllers, outputting the plurality of panel driving signals to the plurality of panel modules, respectively (par 0157; discloses the processor 130 may control to reproduce an image corresponding to a position of each cabinet in a received image by cropping through a timing controller (T-CON) included in each cabinet); Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by You to incorporate the teachings of Kim to include timing controller in each display panel that can receive corresponding scaled image data and display the image data on each panel. The modification would divide the processing load from a single processor to other chips of the display device. With respect to claim 2, You as modified by Kim don’t expressly disclose wherein receiving the plurality of terminal images by the plurality of timing controllers comprises: by the image dispatch circuit, outputting the plurality of terminal images based on a plurality of address of the plurality of timing controllers, respectively; Kim further discloses wherein receiving the plurality of terminal images by the plurality of timing controllers comprises: by the image dispatch circuit, outputting the plurality of terminal images based on a plurality of address of the plurality of timing controllers, respectively;(Kim; par 0012; discloses the processor may be configured to: identify a position in which the decomposed re-scaled image is to be displayed by the plurality of groups based on the resolution of the modular display apparatus and the resolution of the re-scaled image; and control to transmit, to the identified at least one group, information on the identified position in which the decomposed re-scaled image is to be displayed; par 0157; discloses The processor 130 may control to reproduce an image corresponding to a position of each cabinet in a received image by cropping through a timing controller (T-CON) included in each cabinet.). Therefore, it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by You as modified by Kim to incorporate the teachings of Kim to transmit image data based on the position of the display module such that images are correctly routed to each display panel and image is correctly display as a whole. With respect to claim 3, You as modified by Kim don’t expressly disclose wherein before generating the plurality of panel driving signals corresponding to the plurality of terminal images, the method further comprises: by the plurality of timing controllers, storing the plurality of terminal images received from the image dispatch circuit; Kim further discloses wherein before generating the plurality of panel driving signals corresponding to the plurality of terminal images, the method further comprises: by the plurality of timing controllers, storing the plurality of terminal images received from the image dispatch circuit (par 0152; discloses the storage 120 may store an image (e.g., still image or moving image) or image portions displayable on the modular display apparatus 100, audio data, multimedia content, etc. The storage 120 may also store a background image (or like image) displayable by one or more of (or one or more portions of) the first to Nth cabinets 110-1, 110-2, . . . , 110-n. Moreover, the storage 120 may store position information, identification information, resolution, etc., of each of the first to Nth cabinets 110-1, 110-2, . . . , 110-n, as well ); Therefore, it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by You as modified by Kim to incorporate the teachings of Kim to locally store the image data transmitted to the tiled display such that images are quickly accessed and display by each display accurately based on their position. With respect to claim 4, You discloses a panel driving system, (par 0005; discloses the present disclosure may provide an infinitely expandable display apparatus and a driving method thereof) applied to a spliced display device comprising a plurality of panel modules, (fig. 1; discloses a cabinet comprising plurality of display unit; par 0032; discloses the cabinet may include a plurality of display units connected to one another through an interface circuit), comprising: an image generation circuit receiving an original image and scaling the original image to generate an initial image having an initial resolution; (par 0036; discloses the panel driving circuit may include an application specific integrated circuit (ASIC); par 0054; discloses image data is output from the set board; par 0075; discloses the master display unit may check a resolution of an input image received from the set board,); an image dispatch circuit electrically connected to the image generation circuit, the image dispatch circuit receiving the initial image and an application setting value, generating an advanced image having a terminal resolution, (par 0037; discloses an ASIC of the master display unit may include an image scaler embedded therein, and thus, may perform an operation of calculating a physical resolution of each of the display units and an image scaling operation on the display units. Therefore, when a resolution mismatch between the set board and the display units occurs, the display units may reproduce a normal image even without changing an output resolution of the set board); and dividing the advanced image into a plurality of terminal images; (par 0076; discloses each of the slave display units may divide the scaled image data into unit image data on the basis of corresponding coordinate information and may output the divided image data as a corresponding coordinate image (S35 and S36)); and receiving the plurality of terminal images, respectively, generating a plurality of panel driving signals corresponding to the plurality of terminal images, and outputting plurality of the panel driving signals to the plurality of panel modules, respectively; (par 0036; discloses the panel driving circuit may include an application specific integrated circuit (ASIC), a data driver, and a gate driver. Par 0055; discloses The ASIC may supply the data driver DIC with unit image data and timing control signals synchronized with the unit image data.) wherein the image dispatch circuit determines whether a value of the initial resolution is equal to the application setting value, sets the initial image as the advanced image when determining the value of the initial resolution is equal to the application setting value, (fig. 16; discloses when the resolution of the input image matches the resolution of the cabinet (i.e. left portion in fig. 16); image is displayed based on the input image resolution), and scales the initial image to generate the advanced image when determining the value of the initial resolution is not equal to the application setting value, and a value of the terminal resolution of the advanced image is equal to the application setting value (par 0075; discloses the master display unit may check a resolution of an input image received from the set board, and then, when the resolution of the input image does not match the total resolution of the cabinet, the master display unit may scale the resolution of the input image on the basis of the total resolution of the cabinet and may transfer the scaled image data to the slave display units (S31 to S34)); You doesn’t expressly disclose a plurality of timing controllers electrically connected to the image dispatch circuit, receiving the plurality of terminal images, respectively, generating a plurality of panel driving signals corresponding to the plurality of terminal images, and outputting plurality of the panel driving signals to the plurality of panel modules, respectively; In the same field of endeavor, Kim discloses a tiled display system and control method (see abstract); Kim discloses a plurality of timing controllers electrically connected to the image dispatch circuit, receiving the plurality of terminal images, respectively, generating a plurality of panel driving signals corresponding to the plurality of terminal images, and outputting plurality of the panel driving signals to the plurality of panel modules, respectively; (par 0157; discloses the processor 130 may control to reproduce an image corresponding to a position of each cabinet in a received image by cropping through a timing controller (T-CON) included in each cabinet); Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by You to incorporate the teachings of Kim to include timing controller in each display panel that can receive corresponding scaled image data and display the image data on each panel. The modification would divide the processing load from a single processor to other chips of the display device. With respect to claim 6, You as modified by Kim don’t expressly disclose wherein the image dispatch circuit outputs the plurality of terminal images based on a plurality of addresses, corresponding to the plurality of timing controllers, respectively; Kim further discloses wherein the image dispatch circuit outputs the plurality of terminal images based on a plurality of addresses, corresponding to the plurality of timing controllers, respectively;(Kim; par 0012; discloses the processor may be configured to: identify a position in which the decomposed re-scaled image is to be displayed by the plurality of groups based on the resolution of the modular display apparatus and the resolution of the re-scaled image; and control to transmit, to the identified at least one group, information on the identified position in which the decomposed re-scaled image is to be displayed; par 0157; discloses The processor 130 may control to reproduce an image corresponding to a position of each cabinet in a received image by cropping through a timing controller (T-CON) included in each cabinet.). Therefore, it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by You as modified by Kim to incorporate the teachings of Kim to transmit image data based on the position of the display module such that images are correctly routed to each display panel and image is correctly display as a whole. With respect to claim 7, You as modified by Kim don’t expressly disclose wherein the plurality of timing controllers stores the plurality of terminal images received from the image dispatch circuit, respectively; Kim further discloses wherein the plurality of timing controllers stores the plurality of terminal images received from the image dispatch circuit, respectively (par 0152; discloses the storage 120 may store an image (e.g., still image or moving image) or image portions displayable on the modular display apparatus 100, audio data, multimedia content, etc. The storage 120 may also store a background image (or like image) displayable by one or more of (or one or more portions of) the first to Nth cabinets 110-1, 110-2, . . . , 110-n. Moreover, the storage 120 may store position information, identification information, resolution, etc., of each of the first to Nth cabinets 110-1, 110-2, . . . , 110-n, as well ); Therefore, it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by You as modified by Kim to incorporate the teachings of Kim to locally store the image data transmitted to the tiled display such that images are quickly accessed and display by each display accurately based on their position. Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over You et al (US Pub 2022/0208057) in view of Kim et al (US Pub 2020/0324628) and Kim et al (US Pub 2019/0102133) referred to as Kim133. With respect to claim 5, You as modified by Kim don’t expressly disclose wherein the image dispatch circuit is a field programmable gate array; In the same field of endeavor, Kim 133 discloses a tiled display system wherein the image dispatch circuit is a field programmable gate array (par 0069; discloses the gate driver 110, the data driver 120, and the signal controller 130, and/or one or more components thereof, may be implemented via one or more general purpose and/or special purpose components, such as one or more discrete circuits, digital signal processing chips, integrated circuits, application specific integrated circuits, microprocessors, processors, programmable arrays, field programmable arrays, instruction set processors); Therefore, it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by You as modified by Kim to incorporate the teachings of Kim133 to implement the application specific processor comprising field programmable array in order to achieve the same predictable result of scaling image and displaying across plurality of display panels. Response to Arguments Applicant's arguments filed with respect to claim 1, 4 have been fully considered but they are not persuasive and do not put the application in condition for allowance. With respect to claim 1 and 4, applicant’s representative argued that the cited references fails to teach “receiving the initial image and an application setting value and generating an advanced image having a terminal resolution; determining whether a value of the initial resolution is equal to the application setting value, setting the initial image as the advanced image when determining the value of the initial resolution is equal to the application setting value”; However examiner respectfully disagrees, the language of the claimed inventio is broad and the broad reasonable interpretation of the claimed invention reads on the disclosure of the cited references. You discloses receiving the initial image and an application setting value and generating an advanced image having a terminal resolution; Fig. 1 discloses SET board connected to display cabinet comprising plurality of display unit (see fig. 1); par 0035 discloses “Display units may be connected to one another through an interface circuit based on a cascading scheme and may sequentially transfer image data generated by a set board”. i.e. image data having initial image is received by the display cabinet via the SET board. Further You discloses in par 0037 “the display units may include one master display unit and a plurality of slave display units. An ASIC of the master display unit may include an image scaler embedded therein, and thus, may perform an operation of calculating a physical resolution of each of the display units and an image scaling operation on the display units”. The steps of calculating the physical resolution of the each of the display unit to determine the overall resolution of the display cabinet reads on the claim limitation “receiving application setting value” as the master display unit receives arrangement information from plurality of slave display units to determine the overall physical resolution of the display cabinet (see par 0038). You further discloses scaling the image data to generate advanced image having a terminal resolution (par 0072; discloses The display unit [3,3] may be connected to the display unit [1,1] through a feedback loop and may feed back unit arrangement coordinate information (for example, [3,3]), which is a final update result, to the display unit [1,1]. An ASIC of the display unit [1,1] may calculate a physical resolution of each of the display units on the basis of the unit arrangement coordinate information (for example, [3,3]). For example, the unit arrangement coordinate information [3,3] may denote that a screen size of connected display units (i.e., the number of matrixes of the cabinet) is “three units (width)*three units (height)”, and thus, the ASIC of the display unit [1,1] may calculate a physical resolution corresponding to the screen size on the basis of unit resolution information about a single unit previously stored in a memory. The ASIC of the display unit [1,1] may scale image data received from the set board on the basis of the physical resolution of each of the display units and may transfer the scaled image data to the slave display units.); You further discloses determining whether a value of the initial resolution is equal to the application setting value, setting the initial image as the advanced image when determining the value of the initial resolution is equal to the application setting value”; fig. 17 discloses an embodiment of the present invention where input image data and the resolution of the display units matches each other then the image is displayed as is without the need for scaling the image. i.e. resolution of advanced image is same as received initial image resolution (see fig. 17; 4X4 cabinet configuration); however, when the resolution of the display cabinet doesn’t match with the initial image resolution, then the image is scaled to advanced resolution such that image is accurately displayed in the display system with 8X8 cabinet configuration (see fig. 17; 8X8 cabinet configuration); Therefore the broad reasonable interpretation of the claim limitation reads on the disclosure of the cited reference. Hence the rejection is maintained. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUJIT SHAH whose telephone number is (571)272-5303. The examiner can normally be reached Monday-Friday, 9:00 am-6:00 pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Eason can be reached at (571)270-7230. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SUJIT SHAH/Examiner, Art Unit 2624
Read full office action

Prosecution Timeline

Oct 21, 2024
Application Filed
Jul 09, 2025
Non-Final Rejection — §103
Oct 01, 2025
Response Filed
Dec 23, 2025
Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
66%
Grant Probability
77%
With Interview (+11.4%)
2y 8m
Median Time to Grant
Moderate
PTA Risk
Based on 408 resolved cases by this examiner. Grant probability derived from career allow rate.

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