DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/15/2026 has been entered.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 112
The rejection of claim 1-20 under 35 U.S.C.112 (a) and 35 U.S.C.112 (b) rejections are withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chou et al (US Pub 2016/0358591) in view of Araya (US Pub 2009/0033645) and Lee et al (US Pub 2022/0269432).
With respect to claim 1, Chou discloses a timing controller, (fig. 1; timing controller 11) comprising: a plurality of registers located in the gating region (fig. 5; register unit 113; par 0030; discloses the timing controller 11 may further include a register unit 113 as shown in FIG. 5. The register unit 113 is electrically coupled to the memory unit 112 and the data driver 12. The register unit 113 is configured to temporarily stores with the optical data DS outputted from the memory unit 112 and then output the optical data DS to the data driver 12.); an image processing circuit configured to receive an image signal and perform image processing on the image signal based on a plurality of setting values (fig. 2; processing unit 111; par 0023; discloses the processing unit 111 is configured to receive external display data LVDS to be displayed and a control signal CS and control the memory unit 112 to store specific data according to the control signal CS. The processing unit 111 is further configured to generate and output the timing signal TS. The external display data LVDS includes a plurality of image); a restore memory located outside the power gating region (fig. 2; memory unit 112; par 0023; discloses the memory unit 112 is configured to store with the setting data setting while the display apparatus 1 is being power-on and store with one of the plurality of optical lookup table in the external memory unit 15 according to the control signal CS received by the processing unit 111);
Chou disclose receiving the plurality of setting values and store the plurality of setting values in the plurality of registers and the restore memory (par 0023; discloses the memory unit 112 is configured to store with the setting data setting while the display apparatus 1 is being power-on and store with one of the plurality of optical lookup table in the external memory unit 15 according to the control signal CS received by the processing unit 111; par 0030; discloses The register unit 113 is configured to temporarily stores with the optical data DS outputted from the memory unit 112 and then output the optical data DS to the data driver 12);
Chou doesn’t expressly disclose a bus control circuit connected to the plurality of registers and the restore memory;
In the same field of endeavor, Araya discloses a display device and operating method thereof (see abstract); Araya discloses a bus control circuit connected to the plurality of registers and the restore memory (fig. 4; discloses non-volatile memory control unit 19 connected to setting register 12 and the non-volatile memory 7);
Therefore, it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by Chou to incorporate the teachings of Araya to include a memory control circuit that is connected to the registers and the memory such that setting values are read/written effectively to the plurality of registers and the memory;
Chou as modified by Araya doesn’t expressly disclose simultaneously output the plurality of setting values to both the plurality of registers and the restore memory;
In the same field of endeavor, Lee discloses apparatus and method for improving operating speed of the apparatus (see abstract); Lee discloses simultaneously output the plurality of data to both first memory and second memory (par 0044; discloses Based on the shared/parallel connections, the apparatus controller 102 of FIG. 1 and/or the system controller 104 of FIG. 1 can simultaneously send write data to the LD-HP memory 402 and the HD-LP memories 404 and 406 over the data connections 116. Also, the apparatus controller 102 and/or the system controller 104 can simultaneously send write address to the LD-HP memory 402 and the HD-LP memories 404 and 406.);
Therefore, it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by Chou as modified by Araya to incorporate the teachings of Lee to connect plurality of registers and the memory in parallel such that same data being transmitted to the plurality of registers and the memory are stored simultaneously in order to improve the write speed at which data is stored in different memory, hence reducing the time taken to perform the write operation to multiple memory units.
With respect to claim 2, Chou as modified by Araya and Lee discloses wherein the bus control circuit is further configured to receive a read command and an address indicating one of the plurality of registers, and output a setting value read based on a memory address corresponding to the address of the restore memory to the outside (Araya; par 0040; discloses When the display mode change monitoring circuit 16 detects the change in the display mode, the display mode change monitoring circuit 16 outputs a read request signal REQ1, which indicates a request for reading the non-volatile memory 7, to the request arbiter circuit 18. The request arbiter circuit 18 supplies a read request signal REQ to the non-volatile memory control circuit 19. the non-volatile memory control circuit 19 sequentially stores the data read from the non-volatile memory 7 in the setting register 12. FIG. 5 illustrates an example of the data stored in the non-volatile memory 7. In the case of the mode change from the normal mode to the partial mode, the non-volatile memory control circuit 19 reads the partial mode setting value of the partial mode setting value holding region 7-3; fig.5; discloses 7-1 through 7-7 corresponds to the address of setting data in the memory).
With respect to claim 3, Chou as modified by Araya and Lee discloses further comprising a bus-memory interface circuit configured to receive the address from the bus control circuit, store a mapping table in which the address and the memory address are mapped, and transmit the setting value read from the restore memory based on the memory address to the bus control circuit (Araya; par 0035; discloses the non-volatile memory 7 in the present embodiment includes the check bit region 7-1 at the head thereof, at which a check bit is held. In reading data stored in the non-volatile memory 7, the check bit is first read at all times. In a case where the check bit matches with an expected value previously stored in the liquid crystal display device 1, the setting values of each mode are continued to be read).
Claim(s) 12-13, 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chou et al (US Pub 2016/0358591) in view of Lee et al (US Pub 2022/0269432).
With respect to claim 12, Chou discloses a display device, (fig. 1; discloses display device 1) comprising: a pixel array comprising a plurality of pixels, a plurality of gate lines and a plurality of source lines respectively connected to the plurality of pixels (fig. 1; discloses display panel 1 comprising plurality of pixels 1 and plurality of gate lines and source lines connected the pixels); a driving circuit configured to transmit signals for driving the plurality of pixels to the plurality of source lines based on image data (fig. 1; data driver 12; par 0022; discloses The data driver 12 and the gate driver 13 are further electrically coupled to the plurality of pixel 141. Each pixel 141 is configured to be turned on/off through a control of the gate driver 13, receive the optical data DS outputted from the data driver 12, and display the optical data DS at specific time); and a timing controller configured to receive a plurality of setting values, store the plurality of setting values in a restore memory, (fig. 1; timing controller 11; par 0023; discloses As shown in FIG. 2, the timing controller 11 in the present embodiment includes a processing unit 111 and a memory unit 112. The memory unit 112 is configured to store with the setting data setting while the display apparatus 1 is being power-on and store with one of the plurality of optical lookup table in the external memory unit 15 according to the control signal CS received by the processing unit 111) receive an image signal, process the image signal based on the plurality of setting values to obtain a processed image signal, generate the image data based on the processed image signal, and provide the image data to the driving circuit (par 0022; discloses the timing controller 11 is electrically coupled to the external memory unit 15, the data driver 12 and the gate driver 13. The timing controller 11 is configured to provide a timing signal TS (FIG. 2) for an operation of the display apparatus 1 and optical data DS (FIG. 2) for image displaying to the data driver 12 and the gate driver 13; par 0023; discloses the memory unit 112 is configured to store with the setting data setting while the display apparatus 1 is being power-on and store with one of the plurality of optical lookup table in the external memory unit 15 according to the control signal CS received by the processing unit 111. In addition, the memory unit 112 is further configured to output the optical data DS corresponding to a currently-displaying image in the stored optical lookup table to the data driver 12);
Chou discloses the timing controller may include a register and storing the setting value in a plurality of registers (see fig. 5; register unit 113; par 0030; discloses The register unit 113 is configured to temporarily stores with the optical data DS outputted from the memory unit 112 and then output the optical data DS to the data driver 12);
Chou as modified by Araya doesn’t expressly disclose simultaneously output the plurality of setting values to both the plurality of registers and the restore memory;
In the same field of endeavor, Lee discloses apparatus and method for improving operating speed of the apparatus (see abstract); Lee discloses simultaneously output the plurality of data to both first memory and second memory (par 0044; discloses Based on the shared/parallel connections, the apparatus controller 102 of FIG. 1 and/or the system controller 104 of FIG. 1 can simultaneously send write data to the LD-HP memory 402 and the HD-LP memories 404 and 406 over the data connections 116. Also, the apparatus controller 102 and/or the system controller 104 can simultaneously send write address to the LD-HP memory 402 and the HD-LP memories 404 and 406.);
Therefore, it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by Chou to incorporate the teachings of Lee to connect plurality of registers and the memory in parallel such that same data being transmitted to the plurality of registers and the memory are stored simultaneously in order to improve the write speed at which data is stored in different memory, hence reducing the time taken to perform the write operation to multiple memory units.
With respect to claim 13, Chou as modified by Lee discloses wherein the plurality of registers are power-gated during a power gating period (Chou; par 0023; discloses the memory unit 112 is configured to store with the setting data setting while the display apparatus 1 is being power-on and store with one of the plurality of optical lookup table in the external memory unit 15 according to the control signal CS received by the processing unit 111; par 0030; discloses the timing controller 11 may further include a register unit 113 as shown in FIG. 5. The register unit 113 is electrically coupled to the memory unit 112 and the data driver 12. The register unit 113 is configured to temporarily stores with the optical data DS outputted from the memory unit 112 and then output the optical data DS to the data driver 12).
With respect to claim 16, Chou as modified by Lee discloses wherein the timing controller is further configured to receive a command for reading the plurality of setting values and output the plurality of setting values stored in the restore memory (Chou; par 0023; discloses the processing unit 111 is configured to receive external display data LVDS to be displayed and a control signal CS and control the memory unit 112 to store specific data according to the control signal CS).
Claim(s) 14-15, 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chou et al (US Pub 2016/0358591) in view of Lee et al (US Pub 2022/0269432) and Araya (US Pub 2009/0033645).
With respect to claim 14, Chou as modified by Lee don’t expressly disclose wherein the timing controller is further configured to restore a plurality of stored setting values stored in the restore memory to the plurality of registers at an end of the power gating period;
In the same field of endeavor, Araya discloses a display device and operating method thereof (see abstract); Araya discloses wherein the timing controller is further configured to restore a plurality of stored setting values stored in the restore memory to the plurality of registers at an end of the power gating period; (Araya; par 0044; discloses the non-volatile memory control circuit 19 detects the timing, at which the blanking interval starts, in response to the blanking start signal outputted from the timing controller 13. Then, the non-volatile memory control circuit 19 reads a corresponding gamma setting value from the non-volatile memory 7 based on the read request signal REQ. Thereafter, the non-volatile memory control circuit 19 stores the read gamma setting value in the setting register 12. For example, in a case where the first gamma correction value is changed (switched) to the second gamma correction value, the non-volatile memory control circuit 19 reads the second gamma setting value storing region 7-7);
Therefore, it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by Chou as modified by Lee to incorporate the teachings of Araya to store the setting data form the memory to the shift register during blank interval starts such that display device is capable of witching modes without any adverse influence on image display even if an instruction of updating a setting data in a setting register is outputted during image display.
With respect to claim 15, Chou as modified by Lee and Araya discloses wherein the timing controller is further configured to process the image signal based on the plurality of setting values restored to the plurality of registers at the end of the power gating period (Chou; par 0024; discloses FIG. 3B is a schematic timing sequence for illustrating an operation of the timing controller 11 in accordance with an embodiment of the present disclosure. In FIG. 3B, CS denotes the control signal CS; Display Signal denotes the currently-displaying image; and Storage Data denotes the content stored in the memory unit 112. First, at time T1, the display apparatus 1 is converted from a power-off state to a power-on state. Thus, the setting data setting is automatically downloaded from the external memory unit 15 to the memory unit 112. In addition, because the display apparatus 1 is initially power-on and has not received the external display data LVDS to be displayed yet, the memory unit 112 just receiving the setting data setting automatically outputs the optical data DS corresponding to a black image to the electrically-coupled data driver 12. Then, at time T2, the display apparatus 1 displays a black image to avoid abnormal displaying situation. Meanwhile when the display apparatus 1 displays the black image at time T2, the processing unit 111 controls the memory unit 112 to store with the corresponding optical lookup table in the external memory unit 15 according to the content of the control signal CS).
With respect to claim 17, Chou as modified by Lee don’t expressly disclose wherein the timing controller is further configured to receive the command and an address indicating one of the plurality of registers, determine a memory address corresponding to the address, and output setting values, among the plurality of setting values, stored in a region of the restore memory corresponding to the memory address;
In the same field of endeavor, Araya discloses a display device and operating method thereof (see abstract); Araya discloses wherein the timing controller is further configured to receive the command and an address indicating one of the plurality of registers, determine a memory address corresponding to the address, and output setting values, among the plurality of setting values, stored in a region of the restore memory corresponding to the memory address; (Araya; par 0034; discloses FIG. 5 is a block diagram showing a configuration of the non-volatile memory 7. The non-volatile memory 7 includes a plurality of regions. That is, the plurality of regions includes a check-bit storing region 7-1, a normal-display-mode-setting-value storing region 7-2, a partial-mode-setting-value storing region 7-3, an 8-color-display-mode-setting-value storing region 7-4, a partial & 8-color-display-mode-setting-value storing region 7-5, a first-gamma-setting-value storing region 7-6, and a second-gamma-setting-value storing region 7-7. The check-bit storing region 7-1 stores a check bit; par 0037; discloses the setting values are read from the non-volatile memory 7 and stored as initial setting values in the setting register 12 after the reset release. Thus, the display mode is decided due to the initial setting values in the setting register 12. Incidentally, the values read just after the reset release for the display mode is generally the normal display mode setting value stored in the normal-display-mode-setting-value storing region 7-2);
Therefore, it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by Chou as modified by Lee to incorporate the teachings of Araya to receive the command and address from the processing unit that setting data are accurately stored in the shift registers and the restore memory based on the specified address.
Claim(s) 4-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chou et al (US Pub 2016/0358591) in view of Araya (US Pub 2009/0033645), Lee et al (US Pub 2022/0269432) and Tripathi et al (US Pub 2021/0333132).
With respect to claim 4, Chou as modified by Araya and Lee don’t expressly disclose further comprising: a power gating circuit configured to selectively provide power from a power source to the power gating region; and a power management circuit configured to output a power gating signal to control the power gating circuit at an enable level during a power gating period to control the power gating circuit to not provide the power to the power gating region during the power gating period;
In the same field of endeavor, Tripathi discloses control circuit comprising a power gating circuit configured to selectively provide power from a power source to the power gating region (fig. 1; power manager PMGR32; par 0043; discloses The PMGR 32 may be configured to control the supply voltage magnitudes requested from the PMU 156. The PMGR 32 may be under direct software control (e.g., software may directly request the power up and/or power down of components) and/or may be configured to monitor the SOC 10 and determine when various components are to be powered up or powered down); and a power management circuit configured to output a power gating signal to control the power gating circuit at an enable level during a power gating period to control the power gating circuit to not provide the power to the power gating region during the power gating period (fig. 1; power management unit 156; par 0044; discloses The PMU 156 may generally include the circuitry to generate supply voltages and to provide those supply voltages to other components of the system such as the SOC 10, the memory 12 (V.sub.MEM in FIG. 1), various off-chip peripheral components (not shown in FIG. 1) such as display devices, image sensors, user interface devices, etc. The PMU 156 may thus include programmable voltage regulators, logic to interface to the SOC 10 and more particularly the PMGR 32 to receive voltage requests, etc );
Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by Chou as modified by Araya and Lee to incorporate the teachings of Tripathi to include power management unit and power manager circuit configured to supply required voltages to various components and control activation/deactivation of each components in order to control each components to perform assigned tasks correctly.
With respect to claim 5, Chou as modified by Araya, Lee and Tripathi discloses further comprising a reload control circuit configured to read the plurality of setting values stored in the restore memory and store the plurality of setting values in the plurality of registers at an end of the power gating period (Chou; par 0024; discloses at time T1, the display apparatus 1 is converted from a power-off state to a power-on state. Thus, the setting data setting is automatically downloaded from the external memory unit 15 to the memory unit 112. In addition, because the display apparatus 1 is initially power-on and has not received the external display data LVDS to be displayed yet, the memory unit 112 just receiving the setting data setting automatically outputs the optical data DS corresponding to a black image to the electrically-coupled data driver 12. Then, at time T2, the display apparatus 1 displays a black image to avoid abnormal displaying situation. Meanwhile when the display apparatus 1 displays the black image at time T2, the processing unit 111 controls the memory unit 112 to store with the corresponding optical lookup table in the external memory unit 15 according to the content of the control signal CS; par 0030; discloses the timing controller 11 may further include a register unit 113 as shown in FIG. 5. The register unit 113 is electrically coupled to the memory unit 112 and the data driver 12. The register unit 113 is configured to temporarily stores with the optical data DS outputted from the memory unit 112 and then output the optical data DS to the data driver 12).
With respect to claim 6, Chou as modified by Araya, Lee and Tripathi discloses wherein the power management circuit is further configured to output a load signal at the enable level at the end of the power gating period, (Tripathi; par 0043; discloses The PMGR 32 may be configured to control the supply voltage magnitudes requested from the PMU 156. There may be multiple supply voltages generated by the PMU 156 for the SOC 10. For example, illustrated in FIG. 1 are a V.sub.CPU and a V.sub.SOC. The V.sub.CPU may be the supply voltage for the CPU complex 14. The V.sub.SOC may generally be the supply voltage for the rest of the SOC 10 outside of the CPU complex 14. For example, there may be separate supply voltages for the memory controller power domain and the always-on power domain, in addition to the V.sub.SOC for the other components) and wherein the bus control circuit is further configured to receive the plurality of setting values read by the reload control circuit, and store the plurality of setting values in the plurality of registers while the load signal is at the enable level (Araya; par 0041; discloses The non-volatile memory control circuit 19 detects the timing, at which a blanking interval starts, in response to a blanking start signal outputted from the timing controller 13. As illustrated in FIG. 6, the non-volatile memory control circuit 19 accesses the non-volatile memory 7 at the timing t15 (at the head of the front porch), based on the situation of the request; par 0042; discloses the non-volatile memory control circuit 19 sequentially stores the data read from the non-volatile memory 7 in the setting register 12).
Claim(s) 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chou et al (US Pub 2016/0358591) in view of Araya (US Pub 2009/0033645), Lee et al (US Pub 2022/0269432) and PARK et al (US Pub 2013/0207961).
With respect to claim 8, Chou as modified by Araya and Lee discloses timing controller comprises image processing unit (Chou; fig. 2; image processing unit 111);
Chou as modified by Araya and Lee don’t expressly disclose wherein the image processing circuit comprises a plurality of processing circuits configured to process the image signal using the plurality of setting values;
In the same field of endeavor, PARK discloses wherein the image processing circuit comprises a plurality of processing circuits configured to process the image signal using the plurality of setting values (fig. 6; data processor comprises plurality of data processing units 810-840; par 0090; discloses each of the first to fourth data processing circuits 810, 820, 830 and 840 may include a frame rate controller, for example. In such an embodiment, each of the first to fourth data processing circuits 810, 820, 830 and 840 may receive a corresponding input image signals, e.g., one of the first to fourth input image signals IDAT1, IDAT2, IDAT3 and IDAT4, and may generate and output an interpolation frame image signal, in which a motion is interpolated based on the first to fourth input image signals IDAT1, IDAT2, IDAT3 and IDAT4 of a current frame and the first to fourth input image signals IDAT1, IDAT2, IDAT3 and IDAT4 of a previous frame);
Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by Chou as modified by Araya and Lee to incorporate the teachings of PARK to include plurality of processing unit that is configured to process image data for different regions of the display screen in order to increase the processing response of the display device such that images are rendered and processed in a short period of time.
With respect to claim 9, Chou as modified by Araya, Lee and Park wherein at least one of the plurality of processing circuits is located in the power gating region (Chou; fig. 2; discloses the image processing unit 111 is incorporated within the timing controller 11).
Claim(s) 10-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chou et al (US Pub 2016/0358591) in view of Araya (US Pub 2009/0033645), Lee et al (US Pub 2022/0269432) and ORIO et al (US Pub 2020/0193893).
With respect to claim 10, Chou as modified by Araya and Lee don’t expressly disclose further comprising a plurality of input multiplexer circuits comprising a first input multiplexer circuit and a second input multiplexer circuit, wherein the plurality of registers comprises a first register and a second register, wherein the first register is connected between an input and an output of the first input multiplexer circuit, wherein the second register is connected between an input and an output of the second input multiplexer circuit, and wherein the plurality of input multiplexer circuits are configured to output one of the plurality of setting values based on a plurality of selection signals;
In the same field of endeavor, ORIO discloses display device and control method (see abstract); ORIO discloses a plurality of input multiplexer circuits comprising a first input multiplexer circuit and a second input multiplexer circuit, (fig. 3; selector 35-1, 35-2) wherein the plurality of registers comprises a first register and a second register, wherein the first register is connected between an input and an output of the first input multiplexer circuit, wherein the second register is connected between an input and an output of the second input multiplexer circuit, and wherein the plurality of input multiplexer circuits are configured to output one of the plurality of setting values based on a plurality of selection signals (par 0026; discloses The parameter sets A, B, C, and DEF may be stored in the register 14 as a part of the control parameters and supplied from the register 14 to the color gamut adjustment circuitry 15. Par 0028; discloses The selector circuitry 31 may be configured to select a plurality of selected parameter sets 41 from among the parameter sets A, B, C, and DEF supplied to the color gamut adjustment circuitry 15. The selector circuitry 31 may comprise two selectors 35.sub.1 and 35.sub.2 as illustrated in FIG. 3. The selector 35.sub.1 may be configured to select a selected parameter set 41.sub.1 from among the parameter sets A, B, C, and DEF based on a select signal CE_SEL1 received from the control circuitry 34, and the selector 35.sub.2 may be configured to select a selected parameter set 41.sub.2 from among the parameter sets A, B, C, and DEF based on a select signal CE_SEL2 received from the control circuitry 3);
Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by Chou as modified by Araya and Lee to incorporate the teachings of ORIO to use the selector circuit to transmit setting data stored in the registers to the processing circuits in order to accurately and effectively use the accurate setting data for displaying the content on the display.
With respect to claim 11, Chou as modified by Araya, Lee and ORIO discloses further comprising a selection signal generator configured to receive a plurality of addresses corresponding to the plurality of registers and generate the plurality of selection signals based on the plurality of addresses (ORIO; fig. 3; control circuitry 34; par 0034; discloses the control circuitry 34 is configured to control the operation of the color gamut adjustment circuitry 15. The control circuitry 34 may be configured to generate select signals CE_SEL1 and CE_SEL2 based on the color gamut setting data 4. In embodiments where the color gamut setting data 4 specifies the color gamut “A” for the region 6 of the display panel 1 and the color gamut “B” for the background region 7, the control circuitry 34 generates the select signals CE_SEL1 and CE_SEL2 so that the parameter set A is selected based on the select signal CE_SEL1 and the parameter set B is selected based on the select signal CE_SEL2; par 0035; discloses The control circuitry 34 may be further configured to generate the coordinates (X, Y) to indicate the position of the target pixel based on a vertical sync signal VSYNC, a horizontal sync signal HSYNC, and a dot clock DCLK and supply the coordinates (X, Y) to the selector 37.).
Claim(s) 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Araya (US Pub 2009/0033645) in view of PARK et al (US Pub 2016/0125794) and Lee et al (US Pub 2022/0269432).
With respect to claim 18, Araya discloses a display system, comprising: a host computing device (fig. 3; CPU 6); and a display device configured to store the plurality of setting values in a plurality of registers indicated by the plurality of addresses, (fig. 3; display device 1; par 0031; discloses the setting register 12 stores therein setting value of the display control circuit 3, which are required for displaying images on the display panel 2; fig. 5; discloses setting data with address in the memory) and in a restore memory based on a plurality of memory addresses corresponding to the plurality of addresses, (par 0042; discloses the non-volatile memory control circuit 19 sequentially stores the data read from the non-volatile memory 7 in the setting register 12. FIG. 5 illustrates an example of the data stored in the non-volatile memory 7; par 0029; discloses the non-volatile memory 7 is provided outside of the liquid crystal display device 1, and stores therein setting values (setting data), such as reference values of drive voltages, corresponding to a plurality of display modes in the liquid crystal display device 1;);
Araya doesn’t expressly disclose a host computing device configured to output a plurality of addresses and a plurality of setting values corresponding to the plurality of addresses;
In the same field of endeavor, PARK discloses display device and control method thereof (see abstract); PARK discloses a host device configured to output a plurality of addresses and a plurality of setting values corresponding to the plurality of addresses (par 0075; discloses the host HOST may select one of the TEDs TED0 and TED1 for a read operation or write operation in response to addresses transmitted through the auxiliary bus BUS_AU; par 0063; discloses the host 110 may transmit the video data to the TEDs TED0 and TED1 through a main link ML that includes a plurality of lanes ML0, ML1, ML2 and ML3, transmit or receive the additional data to or from the TEDs TED0 and TED1 through an auxiliary bus BUS_AUX, and receive the HPD signal from the TEDs TED0 and TED1 through an HPD bus BUS_HPD);
Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by Araya to incorporate the teachings of PARK to transmit the setting value and corresponding address to the display device via a host device in order to allow display device to easily access the setting value control the operation of the display device based on the received setting value;
Araya as modified by PARK don’t expressly disclose simultaneously output the plurality of setting values to both the plurality of registers and the restore memory;
In the same field of endeavor, Lee discloses apparatus and method for improving operating speed of the apparatus (see abstract); Lee discloses simultaneously output the plurality of data to both first memory and second memory (par 0044; discloses Based on the shared/parallel connections, the apparatus controller 102 of FIG. 1 and/or the system controller 104 of FIG. 1 can simultaneously send write data to the LD-HP memory 402 and the HD-LP memories 404 and 406 over the data connections 116. Also, the apparatus controller 102 and/or the system controller 104 can simultaneously send write address to the LD-HP memory 402 and the HD-LP memories 404 and 406.);
Therefore, it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by Araya as modified by PARK to incorporate the teachings of Lee to connect plurality of registers and the memory in parallel such that same data being transmitted to the plurality of registers and the memory are stored simultaneously in order to improve the write speed at which data is stored in different memory, hence reducing the time taken to perform the write operation to multiple memory units.
With respect to claim 19, Araya as modified by PARK and Lee discloses wherein the display device is further configured to restore the plurality of setting values stored in the restore memory to the plurality of registers at an end of a power gating period (Araya; par 0041; discloses the non-volatile memory control circuit 19 detects the timing, at which a blanking interval starts, in response to a blanking start signal outputted from the timing controller 13. As illustrated in FIG. 6, the non-volatile memory control circuit 19 accesses the non-volatile memory 7 at the timing t15 (at the head of the front porch), based on the situation of the request. Par 0042; discloses the non-volatile memory control circuit 19 sequentially stores the data read from the non-volatile memory 7 in the setting register 12).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Araya (US Pub 2009/0033645) in view of PARK et al (US Pub 2016/0125794), Lee et al (US Pub 2022/0269432) and KATO et al (US Pub 2020/0302878).
With respect to claim 20, Araya as modified by PARK and Lee don’t expressly disclose wherein the host computing device is further configured to output at least one of the plurality of addresses and a read command, and wherein the display device is further configured to output at least one setting value among the plurality of setting values from the restore memory to the host computing device based on the at least one of the plurality of addresses;
In the same field of endeavor, KATO discloses display device and driving method (see abstract); KATO discloses wherein the host device is further configured to output at least one of the plurality of addresses and a read command, and wherein the display device is further configured to output at least one setting value among the plurality of setting values from the restore memory to the host device based on the at least one of the plurality of addresses (par 0113; discloses the input/output circuit IO outputs setting data set in the register REG and image data stored in the display memory DRAM to the host apparatus HOST in response to read command or the like issued by the host apparatus HOST);
Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by Araya as modified by PARK and Lee to incorporate the teachings of KATO to transmit the setting data from the display device to the host device such that setting data are maintained across the different components and updated as necessary based on displayed contents.
Allowable Subject Matter
Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With respect to claim 7, Chou alone or in view of other prior art of record fails to disclose wherein the reload controller comprises: a counter circuit configured to count a clock signal based on the load signal being at the enable level; an address generator configured to generate an address indicating one of the plurality of registers and a memory address corresponding to the address based on a value output by the counter circuit; a memory interface circuit configured to output the memory address to the restore memory and receive data stored in the memory address; and a delay circuit configured to delay the address so that the address is output together with the data.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 12 and 18 have been considered but are moot because the arguments do not apply to new references being used in the current rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUJIT SHAH whose telephone number is (571)272-5303. The examiner can normally be reached Monday-Friday, 9:00 am-6:00 pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Eason can be reached at (571)270-7230. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SUJIT SHAH/Examiner, Art Unit 2624
Prosecution Insights