DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1, 2, 3, 4, 5, 6 and 7 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1, 3, 4, 5, 8, 9 and 10 of Patent No. 12,148,354 B2. Although the conflicting claims are not identical, they are not patentably distinct from each other because: the instant claims are substantially similar to the claims in the conflicting patent, as shown in the following tables.
Claim 1 is rejected for obviousness-type double patenting under claim 1 of Patent No. 12,148,354 B2
Instant application claim 1
Claim 1 of Patent No. 12,148,354
A virtual reality (VR) headset comprising:
A virtual reality (VR) headset comprising:
a headset processor including a transmitter arranged to receive a stream of digital video samples, to continuously convert sets of digital video samples each into a set of analog output levels, and to transmit said sets of analog output levels as an analog waveform over an electromagnetic pathway; and
a headset processor including a transmitter arranged to receive a stream of video samples, to continuously encode sets of N of said video samples each into a set of L output levels, and to transmit said sets of L output levels as an analog waveform over an electromagnetic pathway, wherein L>=N>=2; and
a VR visor including at least one display having at least one source driver, said source driver including
a VR visor including at least one display having at least one source driver, said source driver including
a receiver arranged to receive said sets of analog output levels of said analog waveform from said transmitter,
a receiver arranged to receive said sets of L output levels of said analog waveform from said transmitter, a decoder arranged to decode each set of said L output levels into an output vector of N analog samples,
a buffer arranged to collect said sets of analog output levels as analog samples from said receiver, and to output said analog samples in parallel, each of said analog samples being output to a column of said display, wherein said analog samples corresponding to said stream of digital video samples are substantially displayed on said display
a buffer arranged to collect said output vectors of N analog samples each from said decoder, and to output said output vectors of N analog samples in parallel, each of said analog samples being output to a column of said display, wherein said analog samples corresponding to said stream of video samples are substantially displayed on said display.
Claim 2 is rejected for obviousness-type double patenting under claim 3 of Patent No. 12,148,354 B2
Instant application claim 2
Claim 3 of Patent No. 12,148,354
The virtual reality headset as recited in claim 1 wherein said source driver further includes a plurality of amplifiers arranged to amplify said analog samples output from said buffer before being output to said display
The virtual reality headset as recited in claim 1 wherein said source driver further includes a plurality of amplifiers arranged to amplify said analog samples of said output vectors output from said buffer before being output to said display.
Claim 3 is rejected for obviousness-type double patenting under claim 4 of Patent No. 12,148,354 B2
Instant application claim 3
Claim 4 of Patent No. 12,148,354
The virtual reality headset as recited in claim 1 wherein said source driver further includes a plurality of amplifiers arranged to amplify said analog samples before being input into said buffer.
The virtual reality headset as recited in claim 1 wherein said source driver further includes a plurality of amplifiers arranged to amplify said analog samples of said output vectors output from said decoder before being input into said buffer.
Claim 4 is rejected for obviousness-type double patenting under claim 5 of Patent No. 12,148,354 B2
Instant application claim 4
Claim 5 of Patent No. 12,148,354
The virtual reality headset as recited in claim 1 wherein said source driver does not include any digital-to-analog converters (DACs) for purposes of converting digital pixel data to analog pixel data.
The virtual reality headset as recited in claim 1 wherein said source driver does not include a digital-to-analog converter (DAC) for purposes of converting digital pixel data to analog pixel data.
Claim 5 is rejected for obviousness-type double patenting under claim 8 of Patent No. 12,148,354 B2
Instant application claim 5
Claim 8 of Patent No. 12,148,354
The virtual reality headset as recited in claim 1 wherein said transmitter also transmits said sets of analog output levels as a second analog waveform over a second electromagnetic pathway, and wherein said VR visor further including a second display having a second source driver that receives said sets of analog output levels from said second analog waveform
The virtual reality headset as recited in claim 1 wherein said transmitter also transmits said sets of L output levels as a second analog waveform over a second electromagnetic pathway, and wherein said visor further including a second display having a second source driver that receives said sets of L output levels from said second analog waveform.
Claim 6 is rejected for obviousness-type double patenting under claim 9 of Patent No. 12,148,354 B2
Instant application claim 6
Claim 9 of Patent No. 12,148,354
The virtual reality headset as recited in claim 1 wherein said headset processor further includes a wireless transmitter arranged to transmit said analog waveform over a RF electromagnetic pathway, and wherein said VR visor further includes a wireless receiver arranged to receive said analog waveform.
The virtual reality headset as recited in claim 1 wherein said headset processor further includes a wireless transmitter arranged to transmit said analog waveform over a RF electromagnetic pathway, and wherein said VR visor further includes a wireless receiver arranged to receive said analog waveform.
Claim 7 is rejected for obviousness-type double patenting under claim 10 of Patent No. 12,148,354 B2
Instant application claim 7
Claim 10 of Patent No. 12,148,354
The virtual reality headset as recited in claim 1 wherein one of said digital video samples is a sample that has a value that represents a chemical odor or a haptic sensation, said VR visor further including a device to reproduce said chemical odor or said haptic sensation for a user based upon a value of one of said analog output levels corresponding to said sample that represents said chemical odor or said haptic sensation.
The virtual reality headset as recited in claim 1 wherein one of said video samples has a value that represents a chemical odor or a haptic sensation, said VR visor further including a device to reproduce said chemical odor or said haptic sensation for a user based upon the value of one of said N analog samples corresponding to said one of said video samples.
Claims 8 and 35 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claim 1 of Patent No. 12,531,007 B2. Although the conflicting claims are not identical, they are not patentably distinct from each other because: the instant claims are substantially similar to the claims in the conflicting patent, as shown in the following table.
Claim 8 is rejected for obviousness-type double patenting under claim 1 of Patent No. 12,531,007 B2
Instant application claim 8
Claim 1 of Patent No. 12,531,007
A transmitter of a virtual reality (VR) headset comprising:
A display unit comprising:
a transmitter including
a distributor arranged to receive a plurality of streams of digital video samples from a processing unit of said VR headset and to distribute said digital video samples into a plurality of input vectors according to a predetermined permutation; and
a distributor and a plurality of digital-to-analog converters, said distributor arranged to receive a stream of digital video samples and to distribute said digital video samples into a plurality of input vectors according to a predetermined permutation, and
a plurality of digital-to-analog converters (DACs), each DAC arranged to receive said digital video samples from one of said input vectors, to convert said digital video samples of said one input vector into a series of analog video samples and
one of said digital-to-analog converters (DAC) per input vector, each DAC arranged to receive serially from its corresponding input vector the digital video samples from said corresponding input vector and to convert said digital video samples into a series of analog video samples;
to output said series of analog video samples onto an electromagnetic pathway to a display of said VR headset
a plurality of electromagnetic pathways, each arranged to transport one of said series of analog video samples to a display panel of said display unit; and
a source driver array including a source driver corresponding to each of said DACs, each source driver including
a collector arranged to receive said series of analog video samples from said each DAC and to store said analog video samples of said corresponding input vector, and
a plurality of column drivers arranged to receive said stored analog video samples in parallel from said collector and to amplify each of said stored analog video samples onto a column of said display panel, wherein said each source driver does not decode said analog video samples.
As shown in the chart above, all the claimed features from claim 8 in the instant application are taught in claim 1 in US Patent 12,531,007 with the exception of the claim being a virtual reality (VR) headset. However, these features would have been obvious to incorporated into claim 1 in US Patent 12,531,007 in order to perform these features on a virtual reality (VR) headset.
Claim 35 is rejected for obviousness-type double patenting under claim 1 of Patent No. 12,531,007 B2
Instant application claim 35
Claim 1 of Patent No. 12,531,007
A virtual reality (VR) headset comprising:
A display unit comprising:
a transmitter including
a transmitter including
a distributor arranged to receive a stream of digital video samples and to distribute said digital video samples into a plurality of input vectors in a line buffer according to a predetermined permutation, and
a distributor and a plurality of digital-to-analog converters, said distributor arranged to receive a stream of digital video samples and to distribute said digital video samples into a plurality of input vectors according to a predetermined permutation, and
a digital-to-analog converter (DAC) per input vector, each DAC arranged to receive serially from its corresponding input vector the digital video samples from said corresponding input vector and to convert said digital video samples into a series of analog video samples;
one of said digital-to-analog converters (DAC) per input vector, each DAC arranged to receive serially from its corresponding input vector the digital video samples from said corresponding input vector and to convert said digital video samples into a series of analog video samples;
a plurality of electromagnetic pathways, each arranged to transport one of said series of analog video samples to a display of said VR headset; and
a plurality of electromagnetic pathways, each arranged to transport one of said series of analog video samples to a display panel of said display unit; and
a source driver array including a source driver corresponding to each of said DACs, each source driver including
a source driver array including a source driver corresponding to each of said DACs, each source driver including
a collector arranged to receive said series of analog video samples from said each DAC and to store said analog video samples of said corresponding input vector, and
a collector arranged to receive said series of analog video samples from said each DAC and to store said analog video samples of said corresponding input vector, and
a plurality of column drivers arranged to receive said stored analog video samples in parallel from said collector and to amplify each of said stored analog video samples onto a column of said display.
a plurality of column drivers arranged to receive said stored analog video samples in parallel from said collector and to amplify each of said stored analog video samples onto a column of said display panel, wherein said each source driver does not decode said analog video samples.
As shown in the chart above, all the claimed features from claim 35 in the instant application are taught in claim 1 in US Patent 12,531,007 with the exception of the claim being a virtual reality (VR) headset. However, these features would have been obvious to incorporated into claim 1 in US Patent 12,531,007 in order to perform these features on a virtual reality (VR) headset.
Claim Objections
Claims 9-21, 23-34 and 36-43 are objected to because of the following informalities:
Claims 9-21 depend upon independent claim 8 and recite “A transmitter as recited in claim 8, 10, 17 or 18 ...”. Since independent claim 8 already mention “A transmitter of a virtual reality (VR) headset comprising: ...”, claims 9-21 need to be amended to include the article “The” instead of “A” prior to the appearance of “A” in “A transmitter”.
Claims 23-34 depend upon independent claim 22 and recite “A source driver as recited in claim 22 or 23 ...”. Since independent claim 22 already mention “A source driver of a display comprising: ...”, claims 23-34 need to be amended to include the article “The” instead of “A” prior to the appearance of “A” in “A source drive”.
Claims 36-43 depend upon independent claim 35 and recite “A VR headset as recited in claim 35 or 36 ...”. Since independent claim 35 already mention “A virtual reality (VR) headset comprising: ...”, claims 36-43 need to be amended to include the article “The” instead of “A” prior to the appearance of “A” in “A VR headset”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 18-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Dependent claim 18 depends upon independent claim 8 and recites “... gate driver control signals that are output to gate drivers of said display panel”. However, “said display panel” is undefined in claims 8 and 18. It renders the claim indefinite. Therefore, the claim is rejected under U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph.
Dependent claim 19 is rejected because it depends upon dependent claim 18.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 are rejected under 35 U.S.C. 103 as being unpatentable over Glen (U.S. Patent Application Publication 2003/0231191 A1) in view of KUROKAWA et al (U.S. Patent Application Publication 2018/0211620 A1).
Regarding claim 1, Glen discloses a virtual reality (VR) headset (Paragraph [0014], FIG. 1; Data system 110 can include any device capable of rendering graphics data, such as a virtual reality headset) comprising:
a headset processor (Paragraph [0014], video/graphics controller 120; paragraph [0020], referring to FIG. 2, video/graphics controller 120 is illustrated in greater detail according to at least one embodiment of the present invention) including a transmitter (Paragraph [0020], video/graphics controller 120 includes transmitter 260) arranged to receive a stream of digital video samples (Paragraphs [0022]-[0025], the storage of data to be displayed in frame buffer 220 is controlled by memory controller 210, as is the retrieval of transmitted data 215 from memory 220. In at least one embodiment, memory controller 210 retrieves all or a portion of display data 215 from the frame buffer 220 and provides the display data 215 to the to display engine 230 for further processing ... Display engine 230, in at least one embodiment, renders display data 215 to generate rendered data 225, which is then provided to DEMUX 240 ... rendered data 225 must be supplied to DEMUX 240 at a rate greater than the effective refresh rate of display device 130 ... transmitter 260 receives color component data 245 in parallel from DEMUX 240 and then formats and/or encodes color component data 245 into transmitted data 125 for transmission to display device 130 ...), to continuously convert sets of digital video samples each into a set of analog output levels (Paragraph [0026], transmitter 260 could include one or more digital-to-analog converters (DAC) and connector 150 could include a VGA connector. In this case, transmitted data 125 can be converted from a digital to an analog format and transmitted over the VGA connector (connector 150) using the three color channels (data ports 140)), and to transmit said sets of analog output levels as an analog waveform over an electromagnetic pathway (Paragraph [0026], transmitted data 125 can be converted from a digital to an analog format and transmitted over the VGA connector (connector 150) using the three color channels (data ports 140), each conventionally associated with one of a red, green, and blue channel. Alternately, display device 130 could include a DVI-compliant interface, transmitter 260 could include a digital video interface (DVI) transmitter, and connector 150 could include a DVI connector. Similar to the analog case, transmitted data 125, specific to a single color component, is digitally transmitted in parallel over the DVI connector (connector 150) using the three digital color channels (data ports 140) of the DVI connector conventionally associated with the digital red, green, and blue channels); and
a VR visor (Paragraph [0014], display device 130; paragraph [0028], referring next to FIG. 3, display device 130 is illustrated in greater detail according to one embodiment of the present invention) including at least one display (Paragraph [0028], display 330) having
a receiver (Paragraph [0028], display device 130 includes receiver 310) arranged to receive said sets of analog output levels of said analog waveform from said transmitter (Paragraph [0029], receiver 310 receives, processes, and/or conditions transmitted data 125 sent over connector 150 from video/graphics controller 120 for internal use. In at least one embodiment, transmitted data 125 is transmitted in parallel over a plurality of data ports 140 located on connector 150),
However, Glen does not specifically disclose a VR visor including at least one display having at least one source driver, said source driver including
a receiver arranged to receive said sets of analog output levels of said analog waveform from said transmitter,
a buffer arranged to collect said sets of analog output levels as analog samples from said receiver, and to output said analog samples in parallel, each of said analog samples being output to a column of said display, wherein said analog samples corresponding to said stream of digital video samples are substantially displayed on said display.
In additional, KUROKAWA discloses a VR visor including at least one display (FIG. 1; paragraph [0088], an electronic device 10 includes a display device 11) having at least one source driver (Paragraph [0089], the display device 11 includes a display portion PA, a source driver circuit SD), said source driver (Paragraph [0121], FIG. 3 is a block diagram illustrating the AI decoder AID, the display portion PA, and a source driver circuit SD1 that is applicable to the source driver circuit SD) including
a receiver (Paragraph [0122], the source driver circuit SD1 includes an analog buffer circuit AB1) arranged to receive said sets of analog output levels of said analog waveform from said transmitter (Paragraph [0116], when an analog signal corresponding to image data is transmitted from the image processing portion PP to the AI encoder AIE of the autoencoder 13, the AI encoder AIE performs processing for converting the image data into feature extracted image data. Meanwhile, the AI decoder AID of the autoencoder 13 performs processing for restoring the feature extracted image data into the original image data and outputting the original image data as an analog signal from the output layer OL; paragraph [0131], ... The restored image data is transmitted to the input terminal of the analog buffer circuit AB1 from the output layer OL in the AI decoder AID as an analog signal),
a buffer (Paragraph [0122], the source driver circuit SD1 includes an analog buffer circuit AB2) arranged to collect said sets of analog output levels as analog samples from said receiver (Paragraphs [0126]-[0127], the output layer OL in the AI decoder AID is electrically connected to an input terminal of the analog buffer circuit AB1 ... an output terminal of the analog buffer circuit AB1 is electrically connected to a first terminal of the transistor Tr included in the sample-and-hold circuit SH. A second terminal of the transistor Tr is electrically connected to an input terminal of the analog buffer circuit AB2), and to output said analog samples in parallel (Paragraph [0123], FIG. 3 illustrates the output terminal SEL[j], where j is an integer greater than or equal to 1 and less than or equal to n ... As shown in FIG. 3, the plurality of transistors Tr are connected in parallel with the analog buffer circuit AB1; paragraph [0127], an output terminal of the analog buffer circuit AB1 is electrically connected to a first terminal of the transistor Tr included in the sample-and-hold circuit SH. A second terminal of the transistor Tr is electrically connected to an input terminal of the analog buffer circuit AB2. A gate of the transistor Tr is electrically connected to the output terminal SEL[j].), each of said analog samples being output to a column of said display (Paragraph [0125], the connection structure between the source driver circuit SD1 and each of the AI decoder AID and the display portion PA illustrated in FIG. 3, and the circuit configuration of the source driver circuit SD1 will be described. Note that the description of the circuit configuration of the source driver circuit SD1 will be made with a focus on the jth column), wherein said analog samples corresponding to said stream of digital video samples are substantially displayed on said display (Paragraph [0144], the image data transmitted to the second terminal of the transistor Tr is transmitted to the input terminal of the analog buffer circuit AB2. As a result, the image data is amplified by the analog buffer circuit AB2 at an amplification degree of 1 and is output from the output terminal of the analog buffer circuit AB2. The image data output from the output terminal of the analog buffer circuit AB2 is transmitted to the display portion PA. When the image data is written to the corresponding pixel in the display portion PA, an image is displayed on the display device 11).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the virtual reality headset taught by Glen incorporate the teachings of KUROKAWA, and applying the device configuration taught by KUROKAWA to add the source driver into the virtual reality visor for processing and outputting the received analog samples to a column of the display. Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Glen according to the relied-upon teachings of KUROKAWA to obtain the invention as specified in claim.
Regarding claim 2, the combination of Glen in view of KUROKAWA discloses everything claimed as applied above (see claim 1).
However, Glen does not specifically disclose wherein said source driver further includes
a plurality of amplifiers arranged to amplify said analog samples output from said buffer before being output to said display.
In additional, KUROKAWA discloses wherein said source driver further includes
a plurality of amplifiers arranged to amplify said analog samples output from said buffer before being output to said display (FIG. 3; paragraph [0144], the image data transmitted to the second terminal of the transistor Tr is transmitted to the input terminal of the analog buffer circuit AB2. As a result, the image data is amplified by the analog buffer circuit AB2 at an amplification degree of 1 and is output from the output terminal of the analog buffer circuit AB2. The image data output from the output terminal of the analog buffer circuit AB2 is transmitted to the display portion PA. When the image data is written to the corresponding pixel in the display portion PA, an image is displayed on the display device 11).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the virtual reality headset taught by Glen incorporate the teachings of KUROKAWA, and applying the device configuration taught by KUROKAWA to add the source driver into the virtual reality visor for processing and outputting the received analog samples to a column of the display. Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Glen according to the relied-upon teachings of KUROKAWA to obtain the invention as specified in claim.
Regarding claim 3, the combination of Glen in view of KUROKAWA discloses everything claimed as applied above (see claim 1).
However, Glen does not specifically disclose wherein said source driver further includes
a plurality of amplifiers arranged to amplify said analog samples before being input into said buffer.
In additional, KUROKAWA discloses wherein said source driver further includes
a plurality of amplifiers arranged to amplify said analog samples before being input into said buffer (FIG. 3; paragraph [0144], the image data transmitted to the second terminal of the transistor Tr is transmitted to the input terminal of the analog buffer circuit AB2. As a result, the image data is amplified by the analog buffer circuit AB2 at an amplification degree of 1 and is output from the output terminal of the analog buffer circuit AB2. The image data output from the output terminal of the analog buffer circuit AB2 is transmitted to the display portion PA. When the image data is written to the corresponding pixel in the display portion PA, an image is displayed on the display device 11).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the virtual reality headset taught by Glen incorporate the teachings of KUROKAWA, and applying the device configuration taught by KUROKAWA to add the source driver into the virtual reality visor for processing and outputting the received analog samples to a column of the display. Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Glen according to the relied-upon teachings of KUROKAWA to obtain the invention as specified in claim.
Regarding claim 4, the combination of Glen in view of KUROKAWA discloses everything claimed as applied above (see claim 1).
However, Glen does not specifically disclose wherein said source driver does not include any digital-to-analog converters (DACs) for purposes of converting digital pixel data to analog pixel data.
In additional, KUROKAWA discloses wherein said source driver does not include any digital-to-analog converters (DACs) for purposes of converting digital pixel data to analog pixel data (As shown in FIG. 3; the source driver circuit SD1 does not include any digital-to-analog converters).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the virtual reality headset taught by Glen incorporate the teachings of KUROKAWA, and applying the device configuration taught by KUROKAWA to add the source driver into the virtual reality visor for processing and outputting the received analog samples to a column of the display. Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Glen according to the relied-upon teachings of KUROKAWA to obtain the invention as specified in claim.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Glen (U.S. Patent Application Publication 2003/0231191 A1) in view of KUROKAWA et al (U.S. Patent Application Publication 2018/0211620 A1) in view of Okamoto et al (U.S. Patent No. 12,449,898 B2).
Regarding claim 5, the combination of Glen in view of KUROKAWA discloses everything claimed as applied above (see claim 1).
However, Glen does not specifically disclose wherein said transmitter also transmits said sets of analog output levels as a second analog waveform over a second electromagnetic pathway, and wherein said VR visor further including a second display having a second source driver that receives said sets of analog output levels from said second analog waveform.
In additional, Okamoto discloses (Col 5, lines 39-46, FIG. 1A illustrates a perspective view of a glasses-type (goggle-type) electronic device 100 as an example of a wearable electronic device. FIG. 1A illustrates the electronic device 100 that includes, in a housing 105, a pair of display apparatuses 10 (a display apparatus 10_L and a display apparatus 10_R), a motion detection portion 101, gaze detection portions 102, an arithmetic portion 103, and a communication portion 104) wherein said transmitter also transmits said sets of analog output levels as a second analog waveform over a second electromagnetic pathway (Col 5, lines 47-62, FIG. 1B is a block diagram of the electronic device 100 in FIG. 1A. As in FIG. 1A, the electronic device 100 includes the display apparatus 10_L, the display apparatus 10_R, the motion detection portion 101, the gaze detection portions 102, the arithmetic portion 103, and the communication portion 104, and a variety of signals are transmitted and received between these components through a bus wiring BW. Each of the display apparatus 10_L and the display apparatus 10_R includes a plurality of pixels 230, a driver circuit 30, and a functional circuit 40; Col 7, lines 4-49, The communication portion 104 has a function of communicating with an external device by wire or wirelessly to obtain a variety of data, including image data. The communication portion 104 is provided with a high frequency circuit (RF circuit), for example, to transmit and receive an RF signal ...), and wherein said VR visor further including a second display (Col 5, lines 39-46, FIG. 1A illustrates the electronic device 100 that includes, in a housing 105, a pair of display apparatuses 10 (a display apparatus 10_L and a display apparatus 10_R. The display apparatus 10_R is interpreted as the second display) having a second source driver (Col 7, lines 34-41, the display apparatus 10_R includes the driver circuit 30; Col 12, lines 14-27, the driver circuit 30 includes a gate driver circuit, a source driver circuit ...) that receives said sets of analog output levels from said second analog waveform (Col 15, lines 3-33, specific structure examples of the driver circuit 30 and the functional circuit 40 will be described with reference to FIG. 4 ... The input/output circuit 80 is compatible with a transmission method such as LVDS (Low Voltage Differential Signaling), and the input/output circuit 80 has a function of dividing control signals, image data, and the like input via the terminal portion 14 between the driver circuit 30 and the functional circuit 40. Furthermore, the input/output circuit 80 has a function of outputting information of the display apparatus 10A to the outside via the terminal portion 14).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the virtual reality headset taught by Glen in view of KUROKAWA incorporate the teachings of Okamoto, and applying the display configuration taught by Okamoto to include the second display having the second source driver and the transmitter transmit the second analog waveform to the second source driver for controlling the second display. Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Glen in view of KUROKAWA according to the relied-upon teachings of Okamoto to obtain the invention as specified in claim.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Glen (U.S. Patent Application Publication 2003/0231191 A1) in view of KUROKAWA et al (U.S. Patent Application Publication 2018/0211620 A1) in view of BAE et al (U.S. Patent Application Publication 2018/0268780 A1).
Regarding claim 6, the combination of Glen in view of KUROKAWA discloses everything claimed as applied above (see claim 1).
However, Glen does not specifically disclose wherein said headset processor further includes a wireless transmitter arranged to transmit said analog waveform over a RF electromagnetic pathway, and wherein said VR visor further includes a wireless receiver arranged to receive said analog waveform.
In additional, BAE discloses wherein said headset processor (FIGS. 1 and 2; an electronic device 100 includes a processor 140 (e.g., an AP), a DDI 200, and a display panel 160) further includes a wireless transmitter (FIGS. 7; paragraph [0170], the communication interface 770 may connect to a network 762 through wireless communication ...; paragraph [0179], referring to FIG. 8, the electronic device 801 may include, for example, all or part of an electronic device 701 shown in FIG. 7. The electronic device 801 may include one or more processors 810 (e.g., APs), a communication module 820 ...; paragraph [0181], the communication module 802 may have the same or similar configuration to a communication interface 770 of FIG. 7. The communication module 820 may include a wireless fidelity (Wi-Fi) module 822) arranged to transmit said analog waveform (Paragraph [0050], the DDI 200 may process display data to be transmitted to the display panel 160 in a pixel unit according to the display configurations. For example, the DDI 200 may turn on some elements of the gamma generator under the control of the processor 140 in order to generate a gamma tap voltage of a specified sub-pixel and may use the generated gamma tap voltage a gamma tap voltages of other sub-pixels ...) over a RF electromagnetic pathway (Paragraph [0181], the communication module 820 may include a radio frequency (RF) module 827), and wherein said VR visor further includes a wireless receiver arranged to receive said analog waveform (Paragraph [0185], the RF module 827 may transmit and receive, for example, a communication signal (e.g., an RF signal). Though not shown, the RF module 827 may include, for example, a transceiver, a power amplifier module (PAM), a frequency filter, or a low noise amplifier (LNA); paragraph [0074], the gamma generator 208 may generate an analog gamma value corresponding to at least one of a first color (e.g., red), a second color (e.g., green), or a third color (e.g., blue), and may supply the analog gamma value to the source driver 206 ...; paragraph [0070], the source driver 206 may transmit, to the display panel 160 ...).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the virtual reality headset taught by Glen in view of KUROKAWA incorporate the teachings of BAE, and applying the operating method for an electronic device using a gamma voltage corresponding to a display configuration taught by BAE to add a wireless fidelity (Wi-Fi) module and a radio frequency (RF) module into the virtual reality visor, and use the wireless module to transmit and receive the analog waveform over the radio frequency (RF) electromagnetic pathway. Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Glen in view of KUROKAWA according to the relied-upon teachings of BAE to obtain the invention as specified in claim.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Glen (U.S. Patent Application Publication 2003/0231191 A1) in view of KUROKAWA et al (U.S. Patent Application Publication 2018/0211620 A1) in view of Dom et al (U.S. Patent Application Publication 2022/0062766 A1).
Regarding claim 7, the combination of Glen in view of KUROKAWA discloses everything claimed as applied above (see claim 1).
However, Glen does not specifically disclose wherein one of said digital video samples is a sample that has a value that represents a chemical odor or a haptic sensation, said VR visor further including a device to reproduce said chemical odor or said haptic sensation for a user based upon a value of one of said analog output levels corresponding to said sample that represents said chemical odor or said haptic sensation.
In additional, Dom discloses (Paragraph [0014], FIGS. 3A and 3B illustrate a user using a head-mounted display (HMD) and a plurality of haptic sensors located at various locations along the HMD ...) wherein one of said digital video samples is a sample that has a value that represents a chemical odor or a haptic sensation (Paragraph [0023], ... methods, systems, and devices for activating a plurality of haptic sensors of a physical audio headset of a user playing a video game. In one embodiment, when the haptic sensors of the physical headset of a user are activated, select ones of the haptic sensors vibrate in response to sound components from the video game ...), said VR visor further including a device (Paragraph [0036], FIG. 4 illustrates an embodiment illustrating a method for activating a plurality of haptic sensors of a headset 104 of a user 102 based on 3-dimensional (3D) audio data from a scene of a video game) to reproduce said chemical odor or said haptic sensation for a user (Paragraph [0041], an operation 410 that is configured to amplify the converted analog signals before it is disturbed to the haptic sensors HS1-HSN of the headset 104. After the digital signal is converted to an analog signal, operation 410 can amplify the signal before it is distributed to the haptic sensors ...; paragraph [0042], operation 412 and operation 414 where the operations are configured to distribute the amplified magnitudes and to apply the magnitudes to the respective haptic sensors HS1-HSN on the headset 104, respectively. In one embodiment, operation 412 can be configured to process the amplified magnitudes and distribute it to the appropriate haptic sensors. Upon receiving the amplified magnitudes, operation 414 can be configured to apply the magnitudes to the corresponding haptic sensor. Accordingly, when the amplified magnitudes are applied to the haptic sensors during the gameplay of the user, haptic vibrations may occur along the haptic sensors of the headset resulting in an augmented user perception of the video game) based upon a value of one of said analog output levels corresponding to said sample that represents said chemical odor or said haptic sensation (Paragraph [0038], an operation 406 that is configured to determine the position and orientation of the user character 102′ and to perform vector tracing from the audio objects in the scene to each virtual haptic sensor of a virtual headset of the user character 102′ ...; paragraph [0040], operation 408 can perform translation mapping which includes determining the respective magnitudes to apply to each haptic sensor (e.g., HS1-HSN) of the headset of 104 the user 102 ... operation 408 is configured to convert the digital data to an analog, e.g., digital to analog audio conversion. In some embodiments, it may be necessary to convert the digital signal to an analog signal so that the signal can be interpreted by the headset 104).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the virtual reality headset taught by Glen in view of KUROKAWA incorporate the teachings of Dom, and applying the method and system for activating a plurality of haptic sensors of a physical headset of a user playing a video game taught by Dom to add the haptic sensors on the virtual reality visor for tracking the position and orientation of the virtual reality headset, then reproduce the analog output levels corresponding to video sample that represents the haptic sensation. Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Glen in view of KUROKAWA according to the relied-upon teachings of Dom to obtain the invention as specified in claim.
Claims 8-10, 17 and 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over Glen (U.S. Patent Application Publication 2003/0231191 A1) in view of Kang (U.S. Patent Application Publication 2006/0109228 A1).
Regarding claim 8, Glen discloses a transmitter of a virtual reality (VR) headset (Paragraph [0014], FIG. 1; Data system 110 can include any device capable of rendering graphics data, such as a virtual reality headset; paragraph [0014], video/graphics controller 120; paragraph [0020], referring to FIG. 2, video/graphics controller 120 is illustrated in greater detail according to at least one embodiment of the present invention ... video/graphics controller 120 includes transmitter 260) comprising:
a distributor arranged to receive a plurality of streams of digital video samples from a processing unit of said VR headset (Paragraphs [0022]-[0025], the storage of data to be displayed in frame buffer 220 is controlled by memory controller 210, as is the retrieval of transmitted data 215 from memory 220. In at least one embodiment, memory controller 210 retrieves all or a portion of display data 215 from the frame buffer 220 and provides the display data 215 to the to display engine 230 for further processing ... Display engine 230, in at least one embodiment, renders display data 215 to generate rendered data 225, which is then provided to DEMUX 240 ... rendered data 225 must be supplied to DEMUX 240 at a rate greater than the effective refresh rate of display device 130 ... transmitter 260 receives color component data 245 in parallel from DEMUX 240 ...); and
a plurality of digital-to-analog converters (DACs) (Paragraph [0026], transmitter 260 could include one or more digital-to-analog converters (DAC)), each DAC arranged to receive said digital video samples from one of said input vectors (Paragraph [0023], EMUX 240 selects one color component of a plurality of color components for pixels values of rendered data 225 and outputs data associated with a plurality of pixels with a selected single color component (color component data 245) to a plurality of channels 281-283. Each channel (channels 281-283) is capable of transmitting at least one pixel color component to transmitter 260), to convert said digital video samples of said one input vector into a series of analog video samples (Paragraph [0026], transmitter 260 could include one or more digital-to-analog converters (DAC) and connector 150 could include a VGA connector. In this case, transmitted data 125 can be converted from a digital to an analog format and transmitted over the VGA connector (connector 150) using the three color channels (data ports 140)) and to output said series of analog video samples onto an electromagnetic pathway to a display of said VR headset (Paragraph [0026], transmitted data 125 can be converted from a digital to an analog format and transmitted over the VGA connector (connector 150) using the three color channels (data ports 140), each conventionally associated with one of a red, green, and blue channel. Alternately, display device 130 could include a DVI-compliant interface, transmitter 260 could include a digital video interface (DVI) transmitter, and connector 150 could include a DVI connector. Similar to the analog case, transmitted data 125, specific to a single color component, is digitally transmitted in parallel over the DVI connector (connector 150) using the three digital color channels (data ports 140) of the DVI connector conventionally associated with the digital red, green, and blue channels).
However, Glen does not specifically disclose to distribute said digital video samples into a plurality of input vectors according to a predetermined permutation.
In additional, Kang discloses to distribute said digital video samples into a plurality of input vectors (FIG. 3; paragraph [0020], the source driving IC 100 includes a data storage unit 110, a decoder 120, a first sample-hold unit 130, an amplification unit 140, a second sample-hold unit 150, and an analog voltage generator 160. The data storage unit 110 includes a plurality of data registers RG1 through RG3L (L is an integer). The data registers RG1 through RG3L store a digital data signal S_DAT corresponding to one horizontal line of an LCD panel (not shown) in response to an input control signal DIO. The digital data signal S_DAT includes R, G and B color signals r1 through rL, g1 through gL and b1 through bL ...) according to a predetermined permutation (Paragraph [0020], specifically, the data register RG1 stores the R color signal r1, the data register RG2 stores the G color signal g1, and the data register RG3 stores the B color signal b1. The data registers RG4 through RG3L sequentially store the color signals r2, g2, b2, . . . , rL, gL and bL, respectively. Furthermore, the data registers RG1 through RG3L output the R, G and B color signals r1 through rL, g1 through gL and b1 through bL stored therein in response to control signals P1 through P3L, respectively .... Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to understand that the order of data register (RF1, RG2 ... ) associated each horizontal line of an LCD panel would be according to a predetermined order).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the virtual reality headset taught by Glen incorporate the teachings of Kang, and applying the driving method of a source driving integrated circuit for driving an LCD panel taught by Kang to provide a predetermined order for registering and distributing the digital video samples. Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Glen according to the relied-upon teachings of Kang to obtain the invention as specified in claim.
Regarding claim 9, the combination of Glen in view of Kang discloses everything claimed as applied above (see claim 8), and Glen further disclose wherein said processing unit is a graphics processing unit (GPU), an image processing unit (IPU) (FIG. 2; paragraph [0020], video/graphics controller 120 includes display engine 230; paragraph [0022], memory controller 210 retrieves all or a portion of display data 215 from the frame buffer 220 and provides the display data 215 to the to display engine 230 for further processing ... Display engine 230, in at least one embodiment, renders display data 215 to generate rendered data 225, which is then provided to DEMUX 240), or a system-on-chip (SoC).
Regarding claim 10, the combination of Glen in view of Kang discloses everything claimed as applied above (see claim 8), and Glen further disclose wherein said VR headset comprises a headset processor (Paragraph [0014], video/graphics controller 120; paragraph [0020], referring to FIG. 2, video/graphics controller 120 is illustrated in greater detail according to at least one embodiment of the present invention) and a VR visor (Paragraph [0014], display device 130; paragraph [0028], referring next to FIG. 3, display device 130 is illustrated in greater detail according to one embodiment of the present invention), wherein said processing unit and said transmitter are within said headset processor (Paragraph [0020], video/graphics controller 120 includes display engine 230 and transmitter 260), and wherein said display is within said VR visor (FIG. 3; paragraph [0028], display device 130 includes display 330display 330).
Regarding claim 17, the combination of Glen in view of Kang discloses everything claimed as applied above (see claim 8).
However, Glen does not specifically disclose wherein said predetermined permutation permits that each sampling amplifier of a source driver within said display that receives one of said series of analog video samples may output said analog video samples to contiguous storage locations.
In additional, Kang discloses wherein said predetermined permutation permits that each sampling amplifier of a source driver within said display (FIG. 3; paragraph [0020], the source driving IC 100 includes a data storage unit 110, a decoder 120, a first sample-hold unit 130, an amplification unit 140, a second sample-hold unit 150, and an analog voltage generator 160. The data storage unit 110 includes a plurality of data registers RG1 through RG3L (L is an integer). The data registers RG1 through RG3L store a digital data signal S_DAT corresponding to one horizontal line of an LCD panel (not shown) in response to an input control signal DIO. The digital data signal S_DAT includes R, G and B color signals r1 through rL, g1 through gL and b1 through bL ...; paragraph [0007], the present invention provides a source driving IC for an LCD ...) that receives one of said series of analog video samples may output said analog video samples to contiguous storage locations (Paragraph [0020], specifically, the data register RG1 stores the R color signal r1, the data register RG2 stores the G color signal g1, and the data register RG3 stores the B color signal b1. The data registers RG4 through RG3L sequentially store the color signals r2, g2, b2, . . . , rL, gL and bL, respectively. Furthermore, the data registers RG1 through RG3L output the R, G and B color signals r1 through rL, g1 through gL and b1 through bL stored therein in response to control signals P1 through P3L, respectively ....).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the virtual reality headset taught by Glen incorporate the teachings of Kang, and applying the driving method of a source driving integrated circuit for driving an LCD panel taught by Kang to provide a predetermined order for registering and distributing the digital video samples. Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Glen according to the relied-upon teachings of Kang to obtain the invention as specified in claim.
Regarding claim 20, the combination of Glen in view of Kang discloses everything claimed as applied above (see claim 17).
However, Glen does not specifically disclose wherein said predetermined permutation permits that one of said sampling amplifiers samples exclusively control signals.
In additional, Kang discloses wherein said predetermined permutation permits that one of said sampling amplifiers samples exclusively control signals (FIG. 3; paragraph [0020], the source driving IC 100 includes a data storage unit 110, a decoder 120, a first sample-hold unit 130, an amplification unit 140, a second sample-hold unit 150, and an analog voltage generator 160. The data storage unit 110 includes a plurality of data registers RG1 through RG3L (L is an integer). The data registers RG1 through RG3L store a digital data signal S_DAT corresponding to one horizontal line of an LCD panel (not shown) in response to an input control signal DIO ... Specifically, the data register RG1 stores the R color signal r1, the data register RG2 stores the G color signal g1, and the data register RG3 stores the B color signal b1. The data registers RG4 through RG3L sequentially store the color signals r2, g2, b2, . . . , rL, gL and bL, respectively. Furthermore, the data registers RG1 through RG3L output the R, G and B color signals r1 through rL, g1 through gL and b1 through bL stored therein in response to control signals P1 through P3L, respectively ... ; paragraph [0021], the decoder 120 selects one of first analog voltages FAV1 through FAVN (N is an integer) in response to the values of the bits of an R color signal (one of the signals r1 through rL) received from one of the data registers RG1, RG4, RG7, . . . , RG(3L-2) and outputs the selected analog voltage as the analog data signal (one of FAS1 through FASL ...; paragraph [0025], the amplification unit 140 includes amplifiers A1 through A3L. The amplifiers A1 through A3L increase the quantity of current of the latched analog data signals).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the virtual reality headset taught by Glen incorporate the teachings of Kang, and applying the driving method of a source driving integrated circuit for driving an LCD panel taught by Kang to provide a predetermined order for registering and distributing the digital video samples. Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Glen according to the relied-upon teachings of Kang to obtain the invention as specified in claim.
Regarding claim 21, the combination of Glen in view of Kang discloses everything claimed as applied above (see claim 8).
However, Glen does not specifically disclose further comprising:
an image processor arranged to input said digital video samples and to perform at least Gamma correction on said digital video samples, and to output corrected digital video samples.
In additional, Kang discloses further comprising:
an image processor (FIG. 3; paragraph [0020], the source driving IC 100 includes an analog voltage generator 160) arranged to input said digital video samples and to perform at least Gamma correction on said digital video samples (Paragraphs [0026]-[0027], the second sample-hold unit 150 latches first gamma voltages FGV1 through FGVK (K is an integer), second gamma voltages SGV1 through SGVK (K is an integer) or third gamma voltages TGV1 through TGVK (K is an integer) in response to switching control signals S1 through SK (K is an integer) ... When the latched first gamma voltages FGV1' through FGVK' are received, the analog voltage generator 160 generates the first analog voltages FAV1 through FAVN based on the latched first gamma voltages FGV1' through FGVK'. ...), and to output corrected digital video samples (Paragraph [0028], only gamma voltages GV1 through GVK (not shown) having a single transmissivity-to-voltage curve can be continuously input to the second sample-hold unit 150. In this case, the second sample-hold unit 150 latches the gamma voltages GV1 through GVK and outputs the latched gamma voltages GV1' through GVK'. The analog voltage generator 160 generates analog voltages ALV1 through ALVN based on the latched gamma voltages GV1' through GVK' ... Accordingly, the analog video signals R1 through RL, G1 through GL and B1 through BL corresponding to the R, G and B color signals r1 through rL, g1 through gL and b1 through bL can be displayed with the same contrast).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the virtual reality headset taught by Glen incorporate the teachings of Kang, and applying the driving method of a source driving integrated circuit for driving an LCD panel taught by Kang to provide a predetermined order for registering and distributing the digital video samples. Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Glen according to the relied-upon teachings of Kang to obtain the invention as specified in claim.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Glen (U.S. Patent Application Publication 2003/0231191 A1) in view of Kang (U.S. Patent Application Publication 2006/0109228 A1) in view of Okamoto et al (U.S. Patent No. 12,449,898 B2).
Regarding claim 11, the combination of Glen in view of Kang discloses everything claimed as applied above (see claim 8).
However, Glen does not specifically disclose wherein said VR headset further includes a second display and wherein said transmitter also outputs said series of analog video samples onto electromagnetic pathways to said second display of said VR headset.
In additional, Okamoto discloses (Col 5, lines 39-46, FIG. 1A illustrates a perspective view of a glasses-type (goggle-type) electronic device 100 as an example of a wearable electronic device. FIG. 1A illustrates the electronic device 100 that includes, in a housing 105, a pair of display apparatuses 10 (a display apparatus 10_L and a display apparatus 10_R), a motion detection portion 101, gaze detection portions 102, an arithmetic portion 103, and a communication portion 104) wherein said VR headset further includes a second display (Col 5, lines 39-46, FIG. 1A illustrates the electronic device 100 that includes, in a housing 105, a pair of display apparatuses 10 (a display apparatus 10_L and a display apparatus 10_R. The display apparatus 10_R is interpreted as the second display) and wherein said transmitter also outputs said series of analog video samples onto electromagnetic pathways (Col 5, lines 47-62, FIG. 1B is a block diagram of the electronic device 100 in FIG. 1A. As in FIG. 1A, the electronic device 100 includes the display apparatus 10_L, the display apparatus 10_R, the motion detection portion 101, the gaze detection portions 102, the arithmetic portion 103, and the communication portion 104, and a variety of signals are transmitted and received between these components through a bus wiring BW. Each of the display apparatus 10_L and the display apparatus 10_R includes a plurality of pixels 230, a driver circuit 30, and a functional circuit 40; Col 7, lines 4-49, The communication portion 104 has a function of communicating with an external device by wire or wirelessly to obtain a variety of data, including image data. The communication portion 104 is provided with a high frequency circuit (RF circuit), for example, to transmit and receive an RF signal ...; Col 7, lines 34-41, the display apparatus 10_R includes the driver circuit 30; Col 12, lines 14-27, the driver circuit 30 includes a gate driver circuit, a source driver circuit ..) to said second display of said VR headset (Col 15, lines 3-33, specific structure examples of the driver circuit 30 and the functional circuit 40 will be described with reference to FIG. 4 ... The input/output circuit 80 is compatible with a transmission method such as LVDS (Low Voltage Differential Signaling), and the input/output circuit 80 has a function of dividing control signals, image data, and the like input via the terminal portion 14 between the driver circuit 30 and the functional circuit 40. Furthermore, the input/output circuit 80 has a function of outputting information of the display apparatus 10A to the outside via the terminal portion 14).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the virtual reality headset taught by Glen in view of Kang incorporate the teachings of Okamoto, and applying the display configuration taught by Okamoto to include the second display having the second source driver and the transmitter transmit the second analog waveform to the second source driver for controlling the second display. Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Glen in view of Kang according to the relied-upon teachings of Okamoto to obtain the invention as specified in claim.
Claims 12, 16 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Glen (U.S. Patent Application Publication 2003/0231191 A1) in view of Kang (U.S. Patent Application Publication 2006/0109228 A1) in view of BAE et al (U.S. Patent Application Publication 2018/0268780 A1).
Regarding claim 12, the combination of Glen in view of Kang discloses everything claimed as applied above (see claim 10).
However, Glen does not specifically disclose wherein said headset processor further includes a wireless transmitter arranged to transmit said series of analog video samples wirelessly, and wherein said VR visor further includes a wireless receiver arranged to receive said series of analog video samples.
In additional, BAE discloses wherein said headset processor (FIGS. 1 and 2; an electronic device 100 includes a processor 140 (e.g., an AP), a DDI 200, and a display panel 160) further includes a wireless transmitter (FIGS. 7; paragraph [0170], the communication interface 770 may connect to a network 762 through wireless communication ...; paragraph [0179], referring to FIG. 8, the electronic device 801 may include, for example, all or part of an electronic device 701 shown in FIG. 7. The electronic device 801 may include one or more processors 810 (e.g., APs), a communication module 820 ...; paragraph [0181], the communication module 820 may have the same or similar configuration to a communication interface 770 of FIG. 7. The communication module 820 may include a wireless fidelity (Wi-Fi) module 822) arranged to transmit said series of analog video samples wirelessly (Paragraph [0050], the DDI 200 may process display data to be transmitted to the display panel 160 in a pixel unit according to the display configurations. For example, the DDI 200 may turn on some elements of the gamma generator under the control of the processor 140 in order to generate a gamma tap voltage of a specified sub-pixel and may use the generated gamma tap voltage a gamma tap voltages of other sub-pixels ...), and wherein said VR visor further includes a wireless receiver arranged to receive said series of analog video samples (Paragraph [0185], the RF module 827 may transmit and receive, for example, a communication signal (e.g., an RF signal). Though not shown, the RF module 827 may include, for example, a transceiver, a power amplifier module (PAM), a frequency filter, or a low noise amplifier (LNA); paragraph [0074], the gamma generator 208 may generate an analog gamma value corresponding to at least one of a first color (e.g., red), a second color (e.g., green), or a third color (e.g., blue), and may supply the analog gamma value to the source driver 206 ...; paragraph [0070], the source driver 206 may transmit, to the display panel 160 ...).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the virtual reality headset taught by Glen in view of Kang incorporate the teachings of BAE, and applying the operating method for an electronic device using a gamma voltage corresponding to a display configuration taught by BAE to add a wireless fidelity (Wi-Fi) module into the virtual reality visor, and use the wireless module to transmit and receive the analog waveform. Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Glen in view of Kang according to the relied-upon teachings of BAE to obtain the invention as specified in claim.
Regarding claim 16, the combination of Glen in view of Kang discloses everything claimed as applied above (see claim 8).
However, Glen does not specifically disclose wherein said digital video samples are distributed into said input vectors at a first frequency and wherein said digital video samples are serially output from each of said input vectors at a second frequency different from said first frequency.
In additional, BAE discloses (Abstract, an electronic device and a method of operating the electronic device using a gamma voltage of a display panel are provided ...) wherein said digital video samples (FIG. 7; paragraph [0169], the display 760 may display, for example, a variety of content () are distributed into said input vectors at a first frequency (Paragraph [0177], in the time-division manner for the source amplifier of the electronic device 701, a first period of time-division driving of a specified source amplifier at a first driving frequency (e.g., 60 Hz)) and wherein said digital video samples are serially output from each of said input vectors at a second frequency different from said first frequency (Paragraph [0177], the electronic device 701 may output the still image while operating at a driving frequency (e.g., 30 Hz) having a specified size or more. Accordingly, the electronic device 701 may output the still image by using the connection switch in a turn-on state or in the time-division driving manner (during time-division driving, some source amplifiers is in the turn-off state) for a specified source amplifier ... ).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the virtual reality headset taught by Glen in view of Kang incorporate the teachings of BAE, and applying the electronic device taught by BAE to drive the different frequency for distributing and outputting input vectors based on the characteristic of the digital video samples. Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Glen in view of Kang according to the relied-upon teachings of BAE to obtain the invention as specified in claim.
Regarding claim 18, the combination of Glen in view of Kang discloses everything claimed as applied above (see claim 8).
However, Glen does not specifically disclose wherein said transmitter is integrated with a timing controller of said VR headset, said integrated transmitter and timing controller further comprising:
gate driver control signals that are output to gate drivers of said display panel.
In additional, BAE discloses (Abstract, an electronic device and a method of operating the electronic device using a gamma voltage of a display panel are provided ...) wherein said transmitter is integrated with a timing controller of said VR headset (FIGS. 1 and 2; paragraph [0050], the DDI 200 may process display data to be transmitted to the display panel 160 in a pixel unit according to the display configurations ...; paragraphs [0056]-[0058], the DDI 200 includes an interface circuit 201, a logic circuit 202 ... The interface circuit 201 may interface signals or data exchanged between the processor 140 and the DDI 200 ... The logic circuit 202 may include a graphic memory write controller, a timing controller ...; paragraph [0129], an electronic device may include a display panel and a display driver integrated circuit, wherein the display driver integrated circuit includes a source driver including source amplifiers configured to amplify output signals to be output through one or more sub-pixels included in each pixel of the display pane ...), said integrated transmitter and timing controller further comprising:
gate driver control signals that are output to gate drivers of said display panel (Paragraph [0060], the timing controller may control the gate driver 207 to sequentially supply gate signals to the gate lines of the display panel 160, or may control the gate driver 207 to output gate signals to the gate lines of the display panel 160).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the virtual reality headset taught by Glen in view of Kang incorporate the teachings of BAE, and applying the electronic device taught by BAE to provide the timing controller for controlling the gate driver to supply gate signals to the gate lines of the display panel. Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Glen in view of Kang according to the relied-upon teachings of BAE to obtain the invention as specified in claim.
Regarding claim 19, the combination of Glen in view of Kang in view of BAE discloses everything claimed as applied above (see claim 18).
However, Glen does not specifically disclose wherein said integrated transmitter and timing controller are also integrated with a system on-chip of said VR headset.
In additional, BAE discloses wherein said integrated transmitter and timing controller are also integrated with a system on-chip of said VR headset (FIG. 1; paragraph [0041], the processor 140 may control the overall operation of the electronic device 100. The processor 140 may be implemented with an IC, a system on chip (SoC) ...).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the virtual reality headset taught by Glen in view of Kang incorporate the teachings of BAE, and applying the electronic device taught by BAE to provide the system on chip for controlling operations of the gamma generator of the display panel. Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Glen in view of Kang according to the relied-upon teachings of BAE to obtain the invention as specified in claim.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Glen (U.S. Patent Application Publication 2003/0231191 A1) in view of Kang (U.S. Patent Application Publication 2006/0109228 A1) in view of Dom et al (U.S. Patent Application Publication 2022/0062766 A1).
Regarding claim 13, the combination of Glen in view of Kang discloses everything claimed as applied above (see claim 8).
However, Glen does not specifically disclose wherein one of said digital video samples is a sample that has a value that represents a chemical odor or a haptic sensation, said VR headset further including a device to reproduce said chemical odor or said haptic sensation for a user based upon a value of one of said analog video samples corresponding to said sample that represents said chemical odor or said haptic sensation.
In additional, Dom discloses (Paragraph [0014], FIGS. 3A and 3B illustrate a user using a head-mounted display (HMD) and a plurality of haptic sensors located at various locations along the HMD ...) wherein one of said digital video samples is a sample that has a value that represents a chemical odor or a haptic sensation (Paragraph [0023], ... methods, systems, and devices for activating a plurality of haptic sensors of a physical audio headset of a user playing a video game. In one embodiment, when the haptic sensors of the physical headset of a user are activated, select ones of the haptic sensors vibrate in response to sound components from the video game ...), said VR headset further including a device (Paragraph [0036], FIG. 4 illustrates an embodiment illustrating a method for activating a plurality of haptic sensors of a headset 104 of a user 102 based on 3-dimensional (3D) audio data from a scene of a video game) to reproduce said chemical odor or said haptic sensation for a user (Paragraph [0041], an operation 410 that is configured to amplify the converted analog signals before it is disturbed to the haptic sensors HS1-HSN of the headset 104. After the digital signal is converted to an analog signal, operation 410 can amplify the signal before it is distributed to the haptic sensors ...; paragraph [0042], operation 412 and operation 414 where the operations are configured to distribute the amplified magnitudes and to apply the magnitudes to the respective haptic sensors HS1-HSN on the headset 104, respectively. In one embodiment, operation 412 can be configured to process the amplified magnitudes and distribute it to the appropriate haptic sensors. Upon receiving the amplified magnitudes, operation 414 can be configured to apply the magnitudes to the corresponding haptic sensor. Accordingly, when the amplified magnitudes are applied to the haptic sensors during the gameplay of the user, haptic vibrations may occur along the haptic sensors of the headset resulting in an augmented user perception of the video game) based upon a value of one of said analog video samples corresponding to said sample that represents said chemical odor or said haptic sensation (Paragraph [0038], an operation 406 that is configured to determine the position and orientation of the user character 102′ and to perform vector tracing from the audio objects in the scene to each virtual haptic sensor of a virtual headset of the user character 102′ ...; paragraph [0040], operation 408 can perform translation mapping which includes determining the respective magnitudes to apply to each haptic sensor (e.g., HS1-HSN) of the headset of 104 the user 102 ... operation 408 is configured to convert the digital data to an analog, e.g., digital to analog audio conversion. In some embodiments, it may be necessary to convert the digital signal to an analog signal so that the signal can be interpreted by the headset 104).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the virtual reality headset taught by Glen in view of Kang incorporate the teachings of Dom, and applying the method and system for activating a plurality of haptic sensors of a physical headset of a user playing a video game taught by Dom to add the haptic sensors on the virtual reality visor for tracking the position and orientation of the virtual reality headset, then reproduce the analog output levels corresponding to video sample that represents the haptic sensation. Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Glen in view of Kang according to the relied-upon teachings of Dom to obtain the invention as specified in claim.
Claims 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Glen (U.S. Patent Application Publication 2003/0231191 A1) in view of Kang (U.S. Patent Application Publication 2006/0109228 A1) in view of CHAE (U.S. Patent Application Publication 2023/0139147 A1).
Regarding claim 14, the combination of Glen in view of Kang discloses everything claimed as applied above (see claim 8).
However, Glen does not specifically disclose wherein said distributor further includes
a first line buffer that stores said plurality of input vectors; and
a second line buffer that stores a plurality of second input vectors, wherein said distributor being further arranged to alternately distribute a line of said digital video samples between said input vectors of said first line buffer and said second input vectors of said second line buffer, and wherein said DACs alternately read from said first line buffer while said distributor writes into said second line buffer and read from said second line buffer while said distributor writes into said first line buffer.
In additional, CHAE discloses (Abstract, a display device including: a display panel; a scan driver; and a data driver, wherein the data driver includes: a controller configured to generate a gamma voltage control signal with respect to gamma voltage information corresponding to a target luminance level of an image displayed by the display pane ...) wherein said distributor further includes
a first line buffer (FIGS. 1 and 3; paragraph [0110], the output buffer 360 may include source buffers 361 each of which is connected to the corresponding data line DL among the data lines DL. Thus, the first line buffer of source buffers 361) that stores said plurality of input vectors (Paragraph [0052], the data driver 140 may generate data signals (or data voltages) based on the data control signal DCS and the second data DATA2 and may supply the data signals to the data line DL1); and
a second line buffer (Paragraph [0110], the output buffer 360 may include source buffers 361 each of which is connected to the corresponding data line DL among the data lines DL. Thus, the second line buffer of source buffers 361) that stores a plurality of second input vectors (Paragraph [0052], the data driver 140 may generate data signals (or data voltages) based on the data control signal DCS and the second data DATA2 and may supply the data signals to the data lines DL2), wherein said distributor being further arranged to alternately distribute a line of said digital video samples between said input vectors of said first line buffer and said second input vectors of said second line buffer (Paragraph [0110], the output buffer 360 may receive and output the data signal VGS to a corresponding data line DL among data lines DL (in other words, the data lines DL1 to DLm of the display unit 110 described with reference to FIG. 1)), and wherein said DACs alternately read from said first line buffer while said distributor writes into said second line buffer and read from said second line buffer while said distributor writes into said first line buffer (Paragraph [0052], the data driver 140 may generate data signals (or data voltages) based on the data control signal DCS and the second data DATA2 and may supply the data signals to the data lines DL1 to DLm. In this case, the data signal supplied to the data lines DL1 to DLm may be synchronized with an output timing of the first scan signal supplied to the first scan lines SL11 to SL1n. Here, the data control signal DCS may be a signal that controls an operation of the data driver 140 and may include a load signal (or a data enable signal) for instructing the output of a valid data signal).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the virtual reality headset taught by Glen in view of Kang incorporate the teachings of CHAE, and applying the display device taught by CHAE to provide line buffers into the display device controller for storing the input vectors corresponding to each data line of the display unit, then read out data from each data line for driving the pixel to the display unit. Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Glen in view of Kang according to the relied-upon teachings of CHAE to obtain the invention as specified in claim.
Regarding claim 15, the combination of Glen in view of Kang discloses everything claimed as applied above (see claim 8).
However, Glen does not specifically disclose wherein said digital video samples distributed into said input vectors make up a line of an image.
In additional, CHAE discloses (Abstract, a display device including: a display panel; a scan driver; and a data driver, wherein the data driver includes: a controller configured to generate a gamma voltage control signal with respect to gamma voltage information corresponding to a target luminance level of an image displayed by the display pane ...) wherein said digital video samples distributed into said input vectors (FIGS. 1 and 3; paragraph [0110], the output buffer 360 may include source buffers 361 each of which is connected to the corresponding data line DL among the data lines DL. Thus, the first line buffer of source buffers 361; paragraph [0052], the data driver 140 may receive the data control signal DCS and the second data DATA2 from the timing controller 150. The data driver 140 may generate data signals (or data voltages) based on the data control signal DCS and the second data DATA2 and may supply the data signals to the data lines DL1 to DLm) make up a line of an image (Paragraph [0054], the data driver 140 may change an entire voltage range of the gamma voltages to adjust a level of an output data signal according to a target luminance level of an image displayed by the display unit 110).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the virtual reality headset taught by Glen in view of Kang incorporate the teachings of CHAE, and applying the display device taught by CHAE to provide line buffers into the display device controller for storing the input vectors corresponding to each data line of the display unit, then read out data from each data line for driving the pixel to the display unit. Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Glen in view of Kang according to the relied-upon teachings of CHAE to obtain the invention as specified in claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 22, 25, 28-29 and 31-32 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by KUROKAWA et al (U.S. Patent Application Publication 2018/0211620 A1).
Regarding claim 22, KUROKAWA discloses a source driver of a display (FIG. 1; paragraph [0088], an electronic device 10 includes a display device 11; paragraph [0089], the display device 11 includes a display portion PA, a source driver circuit SD; paragraph [0148], FIG. 4 is a block diagram illustrating the AI decoder AID, the display portion PA, and a source driver circuit SD2 that is applicable to the source driver circuit SD. Note that FIG. 4 illustrates part of the circuit configuration of the source driver circuit SD2)comprising:
an input terminal (Paragraph [0149], the source driver circuit SD2 includes an analog buffer circuit AB1) arranged to receive an analog electromagnetic signal over an electromagnetic pathway that includes a continuous series of analog video samples (Paragraph [0160], the image data from the image processing portion PP is input to the autoencoder 13, the AI encoder AIE performs processing for converting the image data into feature extracted image data (the signal PSig in FIG. 4) and the AI decoder AID performs processing for restoring the feature extracted image data into the original image data. The restored image data is transmitted to the input terminal of the analog buffer circuit AB1 from the output layer OL in the AI decoder AID as an analog signal);
a plurality of sampling amplifiers (Paragraph [0176], the image data is amplified by the analog buffer circuit AB2 ...) each arranged to sample exclusively a portion of said analog video samples and to write said portion of analog video samples (Paragraph [0150], a terminal through which the clock signal CLK is input, and the output terminals SEL[1] to SEL[n], where n is an integer greater than or equal to 1. In the case where the pixels (display elements) included in the display portion PA are arranged in a matrix, n corresponds to the number of pixels in one row; paragraphs [0153]-[0154], the output layer OL in the AI decoder AID is electrically connected to an input terminal of the analog buffer circuit AB1 ... An input terminal of the demultiplexer DMX2 is electrically connected to the output terminal SEL[j]) into positions in a storage array designated for said each sampling amplifier (Paragraph [0177], the sample-and-hold circuit SH[2] in the j-th column to the display portion PA through the analog buffer circuit AB2 is stored in the pixel PIX[2] in the j-th column); and
a plurality of column drivers (Paragraph [0156], the sample-and-hold circuit SH[1] is transmitted to a pixel PIX[1] in the display portion PA ...) each arranged to read one of said analog video samples from one of said positions in said storage array (Paragraph [0156], an electric signal output through an output terminal of the analog buffer circuit AB2 that is electrically connected to the sample-and-hold circuit SH[2] is transmitted to a pixel PIX[2] in the display portion PA), to amplify said one of said analog video samples and to drive said one of said amplified analog video samples onto a column of said display (Paragraph [0156], the pixels PIX[1] and PIX[2] in the display portion PA are in the same column; paragraph [0176], the image data transmitted to the second terminal of the transistor Tr in each of the sample-and-hold circuits SH[1] and SH[2] is transmitted to the input terminal of the analog buffer circuit AB2. As a result, the image data is amplified by the analog buffer circuit AB2 at an amplification degree of 1 and is output from the output terminal of the analog buffer circuit AB2. The image data output from the output terminal of the analog buffer circuit AB2 is transmitted to the display portion PA. When the image data is written to the corresponding pixel in the display portion PA, an image is displayed on the display device 11).
Regarding claim 25, KUROKAWA discloses everything claimed as applied above (see claim 22), and KUROKAWA further disclose wherein said electromagnetic pathway is a wired pathway (FIG. 1; paragraph [0107], at least one of the AI decoder AID, the timing controller TC, the source driver circuit SD, and the gate driver circuit GD included in the display device 11 can be mounted on the substrate over which the display portion PA is formed, as an integrated circuit (IC) by a chip on glass (COG) method; paragraphs [0116]-[0117], an analog signal corresponding to image data is transmitted from the image processing portion PP to the AI encoder AIE of the autoencoder 13, the AI encoder AIE performs processing for converting the image data into feature extracted image data. Meanwhile, the AI decoder AID of the autoencoder 13 performs processing for restoring the feature extracted image data into the original image data and outputting the original image data as an analog signal from the output layer OL ... The restored image data that is output from the output layer OL of the AI decoder AID in the autoencoder 13 is transmitted to the source driver circuit SD).
Regarding claim 28, KUROKAWA discloses everything claimed as applied above (see claim 22), and KUROKAWA disclose further comprising a second storage array having positions designated for each sampling amplifier (FIG. 4; paragraph [0176], the image data is amplified by the analog buffer circuit AB2 ... ), wherein said sampling amplifiers being further arranged to alternately write said respective portions of said analog video samples into said storage array or into said second storage array (Paragraph [0177], the sample-and-hold circuit SH[2] in the j-th column to the display portion PA through the analog buffer circuit AB2 is stored in the pixel PIX[2] in the j-th column), and wherein said column drivers alternately read from said storage array while said sampling amplifiers write into said second storage array (Paragraph [0156], an electric signal output through an output terminal of the analog buffer circuit AB2 that is electrically connected to the sample-and-hold circuit SH[2] is transmitted to a pixel PIX[2] in the display portion PA) and read from said second storage array while said sampling amplifiers write into said storage array (Paragraph [0156], the pixels PIX[1] and PIX[2] in the display portion PA are in the same column; paragraph [0176], the image data transmitted to the second terminal of the transistor Tr in each of the sample-and-hold circuits SH[1] and SH[2] is transmitted to the input terminal of the analog buffer circuit AB2. As a result, the image data is amplified by the analog buffer circuit AB2 at an amplification degree of 1 and is output from the output terminal of the analog buffer circuit AB2. The image data output from the output terminal of the analog buffer circuit AB2 is transmitted to the display portion PA. When the image data is written to the corresponding pixel in the display portion PA, an image is displayed on the display device 11).
Regarding claim 29, KUROKAWA discloses everything claimed as applied above (see claim 22), and KUROKAWA disclose further comprising:
control logic circuitry arranged to enable each of said sampling amplifiers to sample said portion of said analog video samples (FIG. 4; paragraph [0176], the image data is amplified by the analog buffer circuit AB2 ... ), to enable said sampling amplifiers to write into said storage array or into said second storage array (Paragraph [0156], an electric signal output through an output terminal of the analog buffer circuit AB2 that is electrically connected to the sample-and-hold circuit SH[2] is transmitted to a pixel PIX[2] in the display portion PA; paragraph [0177], the sample-and-hold circuit SH[2] in the j-th column to the display portion PA through the analog buffer circuit AB2 is stored in the pixel PIX[2] in the j-th column), and to enable said column drivers to read from said storage array or from said second storage array (Paragraph [0156], the pixels PIX[1] and PIX[2] in the display portion PA are in the same column; paragraph [0176], the image data transmitted to the second terminal of the transistor Tr in each of the sample-and-hold circuits SH[1] and SH[2] is transmitted to the input terminal of the analog buffer circuit AB2. As a result, the image data is amplified by the analog buffer circuit AB2 at an amplification degree of 1 and is output from the output terminal of the analog buffer circuit AB2. The image data output from the output terminal of the analog buffer circuit AB2 is transmitted to the display portion PA. When the image data is written to the corresponding pixel in the display portion PA, an image is displayed on the display device 11).
Regarding claim 31, KUROKAWA discloses everything claimed as applied above (see claim 22), and KUROKAWA further disclose wherein said source driver does not include any digital-to-analog-converters (DACs) used to convert video samples (As shown in FIG. 3; the source driver circuit SD1 does not include any digital-to-analog converters).
Regarding claim 32, KUROKAWA discloses everything claimed as applied above (see claim 22), and KUROKAWA further disclose wherein said column drivers are further arranged to read in parallel from said storage array when said storage array is full or to read in parallel from said second storage array when said second storage array is full (FIG. 4; paragraph [0150], a terminal through which the clock signal CLK is input, and the output terminals SEL[1] to SEL[n], where n is an integer greater than or equal to 1. In the case where the pixels (display elements) included in the display portion PA are arranged in a matrix, n corresponds to the number of pixels in one row; paragraphs [0153]-[0154], the output layer OL in the AI decoder AID is electrically connected to an input terminal of the analog buffer circuit AB1 ... An input terminal of the demultiplexer DMX2 is electrically connected to the output terminal SEL[j]; paragraph [0176], the image data transmitted to the second terminal of the transistor Tr in each of the sample-and-hold circuits SH[1] and SH[2] is transmitted to the input terminal of the analog buffer circuit AB2. As a result, the image data is amplified by the analog buffer circuit AB2 at an amplification degree of 1 and is output from the output terminal of the analog buffer circuit AB2. The image data output from the output terminal of the analog buffer circuit AB2 is transmitted to the display portion PA. When the image data is written to the corresponding pixel in the display portion PA, an image is displayed on the display device 11).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 23-24 are rejected under 35 U.S.C. 103 as being unpatentable over KUROKAWA et al (U.S. Patent Application Publication 2018/0211620 A1) in view of Glen (U.S. Patent Application Publication 2003/0231191 A1).
Regarding claim 23, KUROKAWA discloses everything claimed as applied above (see claim 22).
However, KUROKAWA does not specifically disclose wherein said display is within a virtual reality (VR) visor of a VR headset.
In additional, Glen discloses wherein said display is within a virtual reality (VR) visor (FIG. 1; paragraph [0014], display device 130; paragraph [0028], referring next to FIG. 3, display device 130 is illustrated in greater detail according to one embodiment of the present invention. Display device 130 includes display 330) of a VR headset (Paragraph [0014], data system 110 can include any device capable of rendering graphics data, such as a virtual reality headset).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display system taught by KUROKAWA incorporate the teachings of Glen to include the virtual reality headset in order to improve the user’s experience. Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify KUROKAWA according to the relied-upon teachings of Glen to obtain the invention as specified in claim.
Regarding claim 24, the combination of KUROKAWA in view of Glen discloses everything claimed as applied above (see claim 23).
However, KUROKAWA does not specifically disclose wherein said analog electromagnetic signal is received from a transmitter of a headset processor of said VR headset, and wherein said continuous series of analog video samples originate as digital video samples in a graphics processing unit (GPU), an image processing unit (IPU), or a system-on-chip (SoC) of said headset processor.
In additional, Glen discloses wherein said analog electromagnetic signal is received (FIG. 1; paragraph [0028], display device 130 includes receiver 310) from a transmitter (Paragraph [0029], receiver 310 receives, processes, and/or conditions transmitted data 125 sent over connector 150 from video/graphics controller 120 for internal use. In at least one embodiment, transmitted data 125 is transmitted in parallel over a plurality of data ports 140 located on connector 150) of a headset processor of said VR headset (Paragraph [0014], video/graphics controller 120; paragraph [0020], referring to FIG. 2, video/graphics controller 120 is illustrated in greater detail according to at least one embodiment of the present invention ... video/graphics controller 120 includes transmitter 260), and wherein said continuous series of analog video samples originate as digital video samples in a graphics processing unit (GPU), an image processing unit (IPU) (Paragraph [0020], video/graphics controller 120 includes display engine 230; paragraph [0022], memory controller 210 retrieves all or a portion of display data 215 from the frame buffer 220 and provides the display data 215 to the to display engine 230 for further processing ... Display engine 230, in at least one embodiment, renders display data 215 to generate rendered data 225, which is then provided to DEMUX 240) , or a system-on-chip (SoC) of said headset processor.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display system taught by KUROKAWA incorporate the teachings of Glen to include a transmitter within the virtual reality headset in order to transmit the received video samples to the image processing unit for generating the video on the display. Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify KUROKAWA according to the relied-upon teachings of Glen to obtain the invention as specified in claim.
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over KUROKAWA et al (U.S. Patent Application Publication 2018/0211620 A1) in view of Glen (U.S. Patent Application Publication 2003/0231191 A1) in view of BAE et al (U.S. Patent Application Publication 2018/0268780 A1).
Regarding claim 26, the combination of KUROKAWA in view of Glen discloses everything claimed as applied above (see claim 23).
However, KUROKAWA does not specifically disclose wherein said electromagnetic pathway is a wireless pathway, wherein said VR headset further including a wireless transmitter arranged to transmit said continuous series of analog video samples to a wireless receiver of said VR visor, and wherein said wireless receiver being arranged to input said continuous series of analog video samples into said input terminal.
In additional, BAE discloses wherein said electromagnetic pathway (FIGS. 1 and 2; an electronic device 100 includes a processor 140 (e.g., an AP), a DDI 200, and a display panel 160) is a wireless pathway (FIGS. 7; paragraph [0170], the communication interface 770 may connect to a network 762 through wireless communication ...; paragraph [0179], referring to FIG. 8, the electronic device 801 may include, for example, all or part of an electronic device 701 shown in FIG. 7. The electronic device 801 may include one or more processors 810 (e.g., APs), a communication module 820 ...; paragraph [0181], the communication module 802 may have the same or similar configuration to a communication interface 770 of FIG. 7. The communication module 820 may include a wireless fidelity (Wi-Fi) module 822), wherein said VR headset further including a wireless transmitter (FIGS. 7; paragraph [0170], the communication interface 770 may connect to a network 762 through wireless communication ...; paragraph [0179], referring to FIG. 8, the electronic device 801 may include, for example, all or part of an electronic device 701 shown in FIG. 7. The electronic device 801 may include one or more processors 810 (e.g., APs), a communication module 820 ...; paragraph [0181], the communication module 820 may have the same or similar configuration to a communication interface 770 of FIG. 7. The communication module 820 may include a wireless fidelity (Wi-Fi) module 822) arranged to transmit said continuous series of analog video samples to a wireless receiver of said VR visor (Paragraph [0050], the DDI 200 may process display data to be transmitted to the display panel 160 in a pixel unit according to the display configurations. For example, the DDI 200 may turn on some elements of the gamma generator under the control of the processor 140 in order to generate a gamma tap voltage of a specified sub-pixel and may use the generated gamma tap voltage a gamma tap voltages of other sub-pixels ...), and wherein said wireless receiver being arranged to input said continuous series of analog video samples into said input terminal (Paragraph [0185], the RF module 827 may transmit and receive, for example, a communication signal (e.g., an RF signal). Though not shown, the RF module 827 may include, for example, a transceiver, a power amplifier module (PAM), a frequency filter, or a low noise amplifier (LNA); paragraph [0074], the gamma generator 208 may generate an analog gamma value corresponding to at least one of a first color (e.g., red), a second color (e.g., green), or a third color (e.g., blue), and may supply the analog gamma value to the source driver 206 ...; paragraph [0070], the source driver 206 may transmit, to the display panel 160 ...).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display system taught by KUROKAWA in view of Glen incorporate the teachings of BAE, and applying the operating method for an electronic device using a gamma voltage corresponding to a display configuration taught by BAE to add a wireless fidelity (Wi-Fi) module into the virtual reality visor, and use the wireless module to transmit and receive the analog waveform. Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify KUROKAWA in view of Glen according to the relied-upon teachings of BAE to obtain the invention as specified in claim.
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over KUROKAWA et al (U.S. Patent Application Publication 2018/0211620 A1) in view of Glen (U.S. Patent Application Publication 2003/0231191 A1) in view of Dom et al (U.S. Patent Application Publication 2022/0062766 A1).
Regarding claim 27, the combination of KUROKAWA in view of Glen discloses everything claimed as applied above (see claim 23).
However, KUROKAWA does not specifically disclose wherein one of said analog video samples has a value that represents a chemical odor or a haptic sensation, said VR headset further including a device to reproduce said chemical odor or said haptic sensation for a user based upon a value of one of said analog video samples.
In additional, Dom discloses (Paragraph [0014], FIGS. 3A and 3B illustrate a user using a head-mounted display (HMD) and a plurality of haptic sensors located at various locations along the HMD ...) wherein one of said analog video samples has a value that represents a chemical odor or a haptic sensation (Paragraph [0023], ... methods, systems, and devices for activating a plurality of haptic sensors of a physical audio headset of a user playing a video game. In one embodiment, when the haptic sensors of the physical headset of a user are activated, select ones of the haptic sensors vibrate in response to sound components from the video game ...), said VR headset further including a device (Paragraph [0036], FIG. 4 illustrates an embodiment illustrating a method for activating a plurality of haptic sensors of a headset 104 of a user 102 based on 3-dimensional (3D) audio data from a scene of a video game) to reproduce said chemical odor or said haptic sensation for a user (Paragraph [0041], an operation 410 that is configured to amplify the converted analog signals before it is disturbed to the haptic sensors HS1-HSN of the headset 104. After the digital signal is converted to an analog signal, operation 410 can amplify the signal before it is distributed to the haptic sensors ...; paragraph [0042], operation 412 and operation 414 where the operations are configured to distribute the amplified magnitudes and to apply the magnitudes to the respective haptic sensors HS1-HSN on the headset 104, respectively. In one embodiment, operation 412 can be configured to process the amplified magnitudes and distribute it to the appropriate haptic sensors. Upon receiving the amplified magnitudes, operation 414 can be configured to apply the magnitudes to the corresponding haptic sensor. Accordingly, when the amplified magnitudes are applied to the haptic sensors during the gameplay of the user, haptic vibrations may occur along the haptic sensors of the headset resulting in an augmented user perception of the video game) based upon a value of one of said analog video samples (Paragraph [0038], an operation 406 that is configured to determine the position and orientation of the user character 102′ and to perform vector tracing from the audio objects in the scene to each virtual haptic sensor of a virtual headset of the user character 102′ ...; paragraph [0040], operation 408 can perform translation mapping which includes determining the respective magnitudes to apply to each haptic sensor (e.g., HS1-HSN) of the headset of 104 the user 102 ... operation 408 is configured to convert the digital data to an analog, e.g., digital to analog audio conversion. In some embodiments, it may be necessary to convert the digital signal to an analog signal so that the signal can be interpreted by the headset 104).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display system taught by KUROKAWA in view of Glen incorporate the teachings of Dom, and applying the method and system for activating a plurality of haptic sensors of a physical headset of a user playing a video game taught by Dom to add the haptic sensors on the virtual reality visor for tracking the position and orientation of the virtual reality headset, then reproduce the analog output levels corresponding to video sample that represents the haptic sensation. Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify KUROKAWA in view of Glen according to the relied-upon teachings of Dom to obtain the invention as specified in claim.
Claims 30 and 33-34 are rejected under 35 U.S.C. 103 as being unpatentable over KUROKAWA et al (U.S. Patent Application Publication 2018/0211620 A1) in view of Kang (U.S. Patent Application Publication 2006/0109228 A1).
Regarding claim 30, KUROKAWA discloses everything claimed as applied above (see claim 22).
However, KUROKAWA does not specifically disclose wherein said electromagnetic signal includes control signals used for synchronization and are not driven into columns of said display, said source driver further comprising:
a sampling amplifier dedicated to sampling said control signals.
In additional, Kang discloses wherein said electromagnetic signal includes control signals used for synchronization and are not driven into columns of said display (FIG. 3; paragraph [0020], the source driving IC 100 includes a data storage unit 110, a decoder 120, a first sample-hold unit 130, an amplification unit 140, a second sample-hold unit 150, and an analog voltage generator 160. The data storage unit 110 includes a plurality of data registers RG1 through RG3L (L is an integer). The data registers RG1 through RG3L store a digital data signal S_DAT corresponding to one horizontal line of an LCD panel (not shown) in response to an input control signal DIO ... Specifically, the data register RG1 stores the R color signal r1, the data register RG2 stores the G color signal g1, and the data register RG3 stores the B color signal b1. The data registers RG4 through RG3L sequentially store the color signals r2, g2, b2, . . . , rL, gL and bL, respectively. Furthermore, the data registers RG1 through RG3L output the R, G and B color signals r1 through rL, g1 through gL and b1 through bL stored therein in response to control signals P1 through P3L, respectively ...), said source driver further comprising:
a sampling amplifier dedicated to sampling said control signals (Paragraph [0021], the decoder 120 selects one of first analog voltages FAV1 through FAVN (N is an integer) in response to the values of the bits of an R color signal (one of the signals r1 through rL) received from one of the data registers RG1, RG4, RG7, . . . , RG(3L-2) and outputs the selected analog voltage as the analog data signal (one of FAS1 through FASL ...; paragraph [0025], the amplification unit 140 includes amplifiers A1 through A3L. The amplifiers A1 through A3L increase the quantity of current of the latched analog data signals).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display system taught by KUROKAWA incorporate the teachings of Kang, and applying the driving method of a source driving integrated circuit for driving an LCD panel taught by Kang to exclusive the control signals provide and only distribute the digital video samples. Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify KUROKAWA according to the relied-upon teachings of Kang to obtain the invention as specified in claim.
Regarding claim 33, KUROKAWA discloses everything claimed as applied above (see claim 22).
However, KUROKAWA does not specifically disclose wherein said series of analog video samples arrive in a predetermined permutation that permits that each sampling amplifier to output its respective portion of analog video samples to contiguous storage locations in said storage array.
In additional, Kang discloses wherein said series of analog video samples arrive (FIG. 3; paragraph [0020], the source driving IC 100 includes a data storage unit 110, a decoder 120, a first sample-hold unit 130, an amplification unit 140, a second sample-hold unit 150, and an analog voltage generator 160. The data storage unit 110 includes a plurality of data registers RG1 through RG3L (L is an integer). The data registers RG1 through RG3L store a digital data signal S_DAT corresponding to one horizontal line of an LCD panel (not shown) in response to an input control signal DIO. The digital data signal S_DAT includes R, G and B color signals r1 through rL, g1 through gL and b1 through bL ...) in a predetermined permutation that permits (Paragraph [0020], specifically, the data register RG1 stores the R color signal r1, the data register RG2 stores the G color signal g1, and the data register RG3 stores the B color signal b1. The data registers RG4 through RG3L sequentially store the color signals r2, g2, b2, . . . , rL, gL and bL, respectively. Furthermore, the data registers RG1 through RG3L output the R, G and B color signals r1 through rL, g1 through gL and b1 through bL stored therein in response to control signals P1 through P3L, respectively .... Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to understand that the order of data register (RF1, RG2 ... ) associated each horizontal line of an LCD panel would be according to a predetermined order) that each sampling amplifier to output its respective portion of analog video samples to contiguous storage locations in said storage array Paragraph [0021], the decoder 120 selects one of first analog voltages FAV1 through FAVN (N is an integer) in response to the values of the bits of an R color signal (one of the signals r1 through rL) received from one of the data registers RG1, RG4, RG7, . . . , RG(3L-2) and outputs the selected analog voltage as the analog data signal (one of FAS1 through FASL ...; paragraph [0025], the amplification unit 140 includes amplifiers A1 through A3L. The amplifiers A1 through A3L increase the quantity of current of the latched analog data signals).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display system taught by KUROKAWA incorporate the teachings of Kang, and applying the driving method of a source driving integrated circuit for driving an LCD panel taught by Kang to exclusive the control signals provide and only distribute the digital video samples. Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify KUROKAWA according to the relied-upon teachings of Kang to obtain the invention as specified in claim.
Regarding claim 34, KUROKAWA discloses everything claimed as applied above (see claim 22).
However, KUROKAWA does not specifically disclose wherein said predetermined permutation indicates that one of said sampling amplifiers samples exclusively control signals.
In additional, Kang discloses wherein said predetermined permutation indicates that one of said sampling amplifiers samples exclusively control signals (FIG. 3; paragraph [0020], the source driving IC 100 includes a data storage unit 110, a decoder 120, a first sample-hold unit 130, an amplification unit 140, a second sample-hold unit 150, and an analog voltage generator 160. The data storage unit 110 includes a plurality of data registers RG1 through RG3L (L is an integer). The data registers RG1 through RG3L store a digital data signal S_DAT corresponding to one horizontal line of an LCD panel (not shown) in response to an input control signal DIO ... Specifically, the data register RG1 stores the R color signal r1, the data register RG2 stores the G color signal g1, and the data register RG3 stores the B color signal b1. The data registers RG4 through RG3L sequentially store the color signals r2, g2, b2, . . . , rL, gL and bL, respectively. Furthermore, the data registers RG1 through RG3L output the R, G and B color signals r1 through rL, g1 through gL and b1 through bL stored therein in response to control signals P1 through P3L, respectively ... ; paragraph [0021], the decoder 120 selects one of first analog voltages FAV1 through FAVN (N is an integer) in response to the values of the bits of an R color signal (one of the signals r1 through rL) received from one of the data registers RG1, RG4, RG7, . . . , RG(3L-2) and outputs the selected analog voltage as the analog data signal (one of FAS1 through FASL ...; paragraph [0025], the amplification unit 140 includes amplifiers A1 through A3L. The amplifiers A1 through A3L increase the quantity of current of the latched analog data signals).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display system taught by KUROKAWA incorporate the teachings of Kang, and applying the driving method of a source driving integrated circuit for driving an LCD panel taught by Kang to exclusive the control signals provide and only distribute the digital video samples. Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify KUROKAWA according to the relied-upon teachings of Kang to obtain the invention as specified in claim.
Examiner’s Comment
Claims 35-43 have not art rejection.
Independent claim 35 is rejected under double patenting. A final determination of patentability, after further search, will be mode upon resolution of above double patenting.
Dependent claims 36-43 depend upon independent claim 35 and they have the same reasons.
Conclusion
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/XILIN GUO/Primary Examiner, Art Unit 2616
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