DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claim(s) 1-10 is/are allowed.
Claim(s) 14-17 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 11-13 and 18-20 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Desai (US 2020/0228625).
Regarding claim 11, Desai teaches:
A method of controlling a memory device, the memory device including a data latch and a nonvolatile memory cell array, said method comprising: managing information about an operation period of a sense operation, the sense operation being an operation in which data stored in the nonvolatile memory cell array is read into the data latch; and in response to an inquiry instruction from a memory controller, outputting, to the memory controller, the information about the operation period of the sense operation. Fig. 3 and [0037] In one embodiment such as illustrated in the example 200, the cache 208 may be a portion of global memory of the data storage system 204 whereby cache 208 is used as a data cache for data that is read from and/or written to physical storage such as in connection with I/O operations received from the host 202 at the data storage system 204. [0054] Referring to FIG. 5, shown is an example 300 of an internal cost table of baseline times that may be used in an embodiment in accordance with techniques herein. The table 300 includes the following 3 columns: I/O type 310, I/O size 312 and internal baseline time 314. Element 302 denotes the rows of the table 300 including internal baseline times for different read hit I/O sizes. For example row 302a indicates that the internal baseline time for a read hit I/O size of 4K is 8 micro seconds and row 302b indicates that the internal baseline time for a read hit I/O size of 8K is 12 microseconds.
The limitation “in response to an inquiry instruction from a memory controller, outputting, to the memory controller, the information about the operation period of the sense operation.” is a contingent limitation in a method claim. The claimed invention may be practiced without the condition of “inquiry instruction from a memory controller”, therefore the broadest reasonable interpretation of the claim does not require the contingent limitation.
The Examiner notes that amending the claim to include limitation about “receiving an inquiry instruction from a memory controller” prior to the contingent limitation would likely overcome the cited prior art.
Regarding claim 12, Desai teaches:
further comprising: determining the information about the operation period of the sense operation based on a read condition received from the memory controller together with an inquiry about the information, and then outputting the information to the memory controller. [0054] Referring to FIG. 5, shown is an example 300 of an internal cost table of baseline times that may be used in an embodiment in accordance with techniques herein. The table 300 includes the following 3 columns: I/O type 310, I/O size 312 and internal baseline time 314. Element 302 denotes the rows of the table 300 including internal baseline times for different read hit I/O sizes. For example row 302a indicates that the internal baseline time for a read hit I/O size of 4K is 8 micro seconds and row 302b indicates that the internal baseline time for a read hit I/O size of 8K is 12 microseconds.
Regarding claim 13, Desai teaches:
further comprising: determining the information about the operation period of the sense operation based on a read command issued by the memory controller, and then outputting the information in response to an inquiry about the information from the memory controller. [0054] Referring to FIG. 5, shown is an example 300 of an internal cost table of baseline times that may be used in an embodiment in accordance with techniques herein. The table 300 includes the following 3 columns: I/O type 310, I/O size 312 and internal baseline time 314. Element 302 denotes the rows of the table 300 including internal baseline times for different read hit I/O sizes. For example row 302a indicates that the internal baseline time for a read hit I/O size of 4K is 8 micro seconds and row 302b indicates that the internal baseline time for a read hit I/O size of 8K is 12 microseconds.
Regarding claim 18, Desai teaches:
further comprising: receiving a sense instruction from the memory controller, the sense instruction being an instruction to execute the sense operation; and outputting, to the memory controller, a start time of the sense operation. [0053] Generally, an embodiment may determine the internal baseline cost or time for processing a particular type of I/O of a particular size by measuring the amount of time it takes the data storage system to service the I/O once received at the data storage system when there is minimal or no load on the system. The internal baseline time may denote the amount of time measured from when the I/O is received by the data storage system (e.g., by an FA or HA generally) and end with the point in time when the system is ready to send an acknowledgement (along with any requested read data) to the client (e.g., host) that the I/O operation has completed. The internal baseline time for a particular type of I/O (e.g., read hit, read miss or write) and I/O size may include accessing any data from physical storage and/or cache as needed to service the I/O operation (e.g., for reads) or storing any data (e.g., storing write data to cache).
Regarding claim 19, Desai teaches:
further comprising: receiving a sense instruction from the memory controller, the sense instruction being an instruction to execute the sense operation; and outputting, to the memory controller, a scheduled end time of the sense operation. [0068] In connection with step 3, processing is performed to estimate the amount of time the new I/O will have to wait in the queue before servicing or execution of the new I/O is performed.
Regarding claim 20, Desai teaches:
indicating, to the memory controller, a busy state of the memory device for a time period of the operation period of the sense operation. [0067] In step 3, the data storage system inspects the currently queued I/Os (with their assigned SLOs) currently waiting to be serviced and evaluates the estimated time delay this new I/O will experience due to other pending I/Os in the queue that will be serviced prior to servicing the new I/O (e.g., since the data storage system knows all the queued/other pending I/Os that will be serviced before this new I/O).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Iwai (US 2019/0303024): describes determining scheduling of command processing by using time needed for memory to perform read processing.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLES J CHOI whose telephone number is (571)270-0605. The examiner can normally be reached MON-FRI: 9AM-5PM EST.
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/CHARLES J CHOI/Primary Examiner, Art Unit 2133