DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority to Taiwan Application #113134431 filed 9/11/2024 is acknowledged.
Claims 1-14 filed 10/22/2024 remain pending.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9/25/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. NOTE: US Patent Application Publication Cite No. 1 to Pierson is listed as 20240269738, but should be 20170269738 as indicated in NPL Cite No. 1, Office Action of Taiwan counterpart Application.
Specification
The disclosure is objected to because of the following informalities:
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The term “vender” in paragraphs [0009], [0014], and [0032] would conventionally be spelled - - vendor - -. Appropriate correction is required.
Claim Objections
Claims 5 and 12 are objected to because of the following informalities: “vender” should be spelled - - vendor - -. Appropriate correction is required.
Claim Interpretation
Regarding claims 5 and 12, “post manner” and “non-post manner” are interpreted according to paragraphs 29 and 32 of the instant application: “non-post manner” means the transmitter waits for packet completion of the receiver prior to subsequent operations, and “post manner” means the transmitter does not have to wait for packet confirmation/completion before continuing other operations.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6-11, 13, and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kumagai et al. (US20180287939A1), hereafter Kumagai.
Regarding claim 1,
Kumagai discloses a communication system (Fig. 1, networks 101, 102) comprising a plurality of FPGA devices comprise a first FPGA device and a second FPGA device (Fig. 1, transfer devices 100 in network 101/102; Fig. 3-4 and paragraphs 40-42 describe devices 100 comprises FPGAs) electrically connected to another one of the FPGA devices through a corresponding at least one connection port (Fig. 1; Fig. 2, modules 202), wherein the first FPGA device is configured to determine a format of a packet that belongs to one of a plurality of transmission formats (Fig. 13, S1301-1302; Fig. 14, S1404; paragraphs 6, 10, 36-43, 48, 57, 103; determine the packet format among first/second/third header types), when the format belongs to a first or a second format among the formats, the first FPGA device adds a routing information to the packet and transmits the packet to the second FPGA device (Fig. 3-4; Fig. 13, S1303-1304; Fig. 14, S1405; paragraphs 48-62, 104, 105; packet header format is extracted; search control FPGA results include destination information according to extracted header format updated/added to packet for transfer to destination).
Regarding claim 8,
Kumagai discloses a communication method (Fig. 13, 14) adapted for a plurality of FPGA devices (Fig. 1, transfer devices 100 in network 101/102; Fig. 3-4 and paragraphs 40-42 describe devices 100 comprises FPGAs) comprising determining a format of a plurality of transmission formats of a packet by a first FPGA device among the FPGA devices (Fig. 13, S1301-1302; Fig. 14, S1404; paragraphs 6, 10, 36-43, 48, 57, 103; determine the packet format among first/second/third header types), each of the FPGA devices are electrically connected to another one of the FPGA devices through the corresponding at least one connection port (Fig. 1 devices connected via ports shown in Fig. 2, modules 202); and adding a routing information to the packet and transmitting the packet to a second FPGA device among the FPGA devices by the first FPGA device when the format belongs to a first or a second format among the formats (Fig. 3-4; Fig. 13, S1303-1304; Fig. 14, S1405; paragraphs 48-62, 104, 105; header format extracted; search control FPGA results include destination information updated/added to packet for transfer to destination).
Regarding claims 2 and 9,
Kumagai discloses the routing information comprises a bus sequence number that correspond to the second FPGA device (paragraph 5, 51-52; destination IP/MAC address), a device sequence number that corresponds to the at least one connection port of the second FPGA device (paragraphs 47-49, 59; sequence number indicating the order data is received to the input port of the module 202), and a function sequence number that corresponds to one of a plurality of modules in the second FPGA device (Fig. 3; paragraph 53-56; port number table identifies the module ID corresponding to the port number).
Regarding claims 3 and 10,
Kumagai discloses the FPGA devices comprise a third FPGA device electrically connected between the first FPGA device and the second FPGA device (Fig. 1, transfer devices 100 in network 101 nearest to and farthest from network 102 and having other transfer devices 100 in between) that receives the packet and transmits the packet to the second FPGA device based on the routing information (Fig. 3-4; Fig. 13, S1303-1304; Fig. 14, S1405; paragraphs 41-66, 104, 105; header processing across next hop transfer devices 100 until the packet reaches the destination).
Regarding claims 4 and 11,
Kumagai discloses a number of the at least one connection port of the second FPGA device is greater than one (Fig. 2; each transfer device comprises multiple communication modules 202), and the device sequence number corresponds to one of the connection ports (paragraphs 47-49, 59; sequence number indicating the order data is received to the input port of the module 202).
Regarding claims 6 and 13,
Kumagai discloses when the format belongs to a third transmission format among the transmission formats, the first FPGA device sets the packet to be transmitted to the second FPGA device in a memory writing manner (Fig. 5-8; paragraph 61-79; TCAM Search processing).
Regarding claims 7 and 14,
Kumagai discloses the first FPGA device is electrically connected to the second FPGA device (Fig. 1-2, devices 100 connected to other devices 100 via modules 202), the packet comprises an address (paragraph 5; destination address), and the second FPGA device provides the packet to one of a plurality of modules in the second FPGA device based on the address (paragraph 51-52, 66; search results include destination IP/MAC address to be updated to the header for packet transfer).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Kumagai in view of Keys (US20100332633A1).
Regarding claims 5 and 12,
Kumagai discloses when the format belongs to the first, the device transmits the packet in a non-post manner (Fig. 20; paragraph 181; search delay causes retention of search result in FIFO memory and awaits search result), but does not expressly disclose setting the packet as a vender/vendor message and transmit in a post manner when the format belongs to the second format.
Keys discloses analogous art related to peer-to-peer distribution for FPGA network nodes (Title; Fig. 3, 7, 11; paragraph 30) including setting the packet as a vender/vendor message and transmits the packet in a post manner when the format belongs to the second transmission format (paragraph 89; automatic push of a message type from the vendor server).
It would have been obvious to one of ordinary skill in the art at the time of effective filing to modify Kumagai by setting the packet as a vender/vendor message and transmits the packet in a post manner when the format belongs to the second transmission format, as shown by Keys, thereby indicating available network updates.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. For example:
Qiu (US20220174009A1) relates to segment routing-based data transmission among FPGA devices
Matthews (USP 10931588) relates to a FPGA network switch for forwarding data over ports according to data format and seq. number.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GREGORY B SEFCHECK whose telephone number is (571)272-3098. The examiner can normally be reached Monday-Friday 6AM-4PM.
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/GREGORY B SEFCHECK/Primary Examiner, Art Unit 2477
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