Prosecution Insights
Last updated: October 01, 2026
Application No. 18/922,594

SEMICONDUCTOR DEVICE AND MEMORY SYSTEM

Non-Final OA §101§DP
Filed
Oct 22, 2024
Priority
Dec 09, 2009 — JP 2009-279719 +11 more
Examiner
LEE, SIU M
Art Unit
Tech Center
Assignee
KIOXIA Corporation
OA Round
1 (Non-Final)
91%
Grant Probability
Favorable
1-2
OA Rounds
2m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allowance Rate
985 granted / 1081 resolved
+31.1% vs TC avg
Moderate +11% lift
Without
With
+11.0%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
22 currently pending
Career history
1098
Total Applications
across all art units

Statute-Specific Performance

§101
7.9%
-32.1% vs TC avg
§103
45.7%
+5.7% vs TC avg
§102
14.5%
-25.5% vs TC avg
§112
17.8%
-22.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1081 resolved cases

Office Action

§101 §DP
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application is being examined under the pre-AIA first to invent provisions. Double Patenting A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957). A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101. Claim 1 is rejected under 35 U.S.C. 101 as claiming the same invention as that of claim 1 of prior U.S. Patent No. 12,141,091 B2. This is a statutory double patenting rejection. Claim Instant Application Claim US Patent 12,141,091 B2 1 A device capable of communicating with a host apparatus, comprising: a symbol generation unit which includes a random number generation circuit, the symbol generation unit configured to select one of a first symbol and a second symbol in a random order with use of the random number generation circuit and output the selected one of the symbols; a coding unit which performs coding a signal of the outputted symbol to transform a bit number; and a transmission unit which transmits the symbol coded by the coding unit to the host apparatus, wherein the first symbol and the second symbol indicate an idle state, wherein the coded symbol is transmitted to the host apparatus by the transmission unit, wherein each of the first and second symbols includes a pair of symbols including a symbol as a plus running disparity and another symbol as a minus running disparity, wherein if a symbol which was most recently selected by the random number generation circuit had a plus running disparity, a symbol selected by the random number generation circuit becomes a minus running disparity, and wherein if a symbol which was most recently selected by the random number generation circuit had a minus running disparity, a symbol selected by the random number generation circuit becomes a plus running disparity. 1 A device capable of communicating with a host apparatus, comprising: a symbol generation unit which includes a random number generation circuit, the symbol generation unit configured to select one of a first symbol and a second symbol in a random order with use of the random number generation circuit and output the selected one of the symbols; a coding unit which performs coding a signal of the outputted symbol to transform a bit number; and a transmission unit which transmits the symbol coded by the coding unit to the host apparatus, wherein the first symbol and the second symbol indicate an idle state, wherein the coded symbol is transmitted to the host apparatus by the transmission unit, wherein each of the first and second symbols includes a pair of symbols including a symbol as a plus running disparity and another symbol as a minus running disparity, wherein if a symbol which was most recently selected by the random number generation circuit had a plus running disparity, a symbol selected by the random number generation circuit becomes a minus running disparity, and wherein if a symbol which was most recently selected by the random number generation circuit had a minus running disparity, a symbol selected by the random number generation circuit becomes a plus running disparity. Regarding claim 1: Claim 1 of US Patent 12,141,091 B2 disclose the exact subject matter of claim 1 as shown in the above comparison. Therefore, claim 1 is rejected under 35 U.S.C. 101 statutory double patenting rejection as claiming the same invention as that of claim 1 of prior U.S. Patent No. 12,141,091 B2. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 3/1 of U.S. Patent No. 8,781,024 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following comparison. Claim Instant Application Claim US Patent 8,781,024 B2 1 A device capable of communicating with a host apparatus, comprising: a symbol generation unit which includes a random number generation circuit, the symbol generation unit configured to select one of a first symbol and a second symbol in a random order with use of the random number generation circuit and output the selected one of the symbols; a coding unit which performs coding a signal of the outputted symbol to transform a bit number; and a transmission unit which transmits the symbol coded by the coding unit to the host apparatus, wherein the first symbol and the second symbol indicate an idle state, wherein the coded symbol is transmitted to the host apparatus by the transmission unit, wherein each of the first and second symbols includes a pair of symbols including a symbol as a plus running disparity and another symbol as a minus running disparity, wherein if a symbol which was most recently selected by the random number generation circuit had a plus running disparity, a symbol selected by the random number generation circuit becomes a minus running disparity, and wherein if a symbol which was most recently selected by the random number generation circuit had a minus running disparity, a symbol selected by the random number generation circuit becomes a plus running disparity. 3/1 A semiconductor device capable of communicating with a host apparatus, comprising: a symbol generation unit which selects and outputs one of a first symbol and a second symbol in a random order; a coding unit which performs 8b/10b coding for the output symbol; and a transmission unit which transmits the symbol coded by the coding unit to the host apparatus, wherein the first and second symbols indicate an idle state, wherein the 8b/10b coded symbol is repeatedly transmitted to the host apparatus by the transmission unit, wherein each of the first and second symbols includes a pair of symbols including a symbol as a plus running disparity and another symbol as a minus running disparity, and wherein a symbol output from the symbol generation unit has a running disparity different from that of a symbol which is most recently output from the symbol generation unit. The device according to claim 1, wherein the symbol generation unit includes a random number generation circuit and selects one of the first and second symbols according to a random number generated by the random number generation circuit. (1) Regarding claim 1: Claim 3/1 of US Patent 8,781,024 B2 disclose all subject matter of claim 1 with the recognition that a 8B/10B coded symbol involve transform a bit number of a symbol, except explicitly disclose “if a symbol which was most recently selected by the random number generation circuit had a plus running disparity, a symbol selected by the random number generation circuit becomes a minus running disparity, and wherein if a symbol which was most recently selected by the random number generation circuit had a minus running disparity, a symbol selected by the random number generation circuit becomes a plus running disparity”. However, claim 3/1 of US Patent 8,781,024 B2 disclose “a symbol output from the symbol generation unit has a running disparity different from that of a symbol which is most recently output from the symbol generation unit”. Claim 3/1 discloses “each of the first and second symbols includes a pair of symbols including a symbol as a plus running disparity and another symbol as a minus running disparity”; therefore, a symbol output from the symbol generation unit has a running disparity different from a symbol most recently output from the symbol generation unit has the same meaning of “if a symbol which was most recently selected by the random number generation circuit had a plus running disparity, a symbol selected by the random number generation circuit becomes a minus running disparity, and wherein if a symbol which was most recently selected by the random number generation circuit had a minus running disparity, a symbol selected by the random number generation circuit becomes a plus running disparity”, thus the claimed limitation is met for the benefit of avoiding DC offset. Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 9/1 of U.S. Patent No. 9,111,048 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following comparison. Claim Instant Application Claim US Patent 9,111,048 B2 1 A device capable of communicating with a host apparatus, comprising: a symbol generation unit which includes a random number generation circuit, the symbol generation unit configured to select one of a first symbol and a second symbol in a random order with use of the random number generation circuit and output the selected one of the symbols; a coding unit which performs coding a signal of the outputted symbol to transform a bit number; and a transmission unit which transmits the symbol coded by the coding unit to the host apparatus, wherein the first symbol and the second symbol indicate an idle state, wherein the coded symbol is transmitted to the host apparatus by the transmission unit, wherein each of the first and second symbols includes a pair of symbols including a symbol as a plus running disparity and another symbol as a minus running disparity, wherein if a symbol which was most recently selected by the random number generation circuit had a plus running disparity, a symbol selected by the random number generation circuit becomes a minus running disparity, and wherein if a symbol which was most recently selected by the random number generation circuit had a minus running disparity, a symbol selected by the random number generation circuit becomes a plus running disparity. 9/1 A host device capable of communicating with a peripheral apparatus, comprising: a symbol generation unit which selects and outputs one of a first symbol and a second symbol in a random order; a coding unit which performs 8b/10b coding for the output symbol; and a transmission unit which transmits the symbol coded by the coding unit to the peripheral apparatus, wherein the first and second symbols indicate an idle state, wherein the 8b/10b coded symbol is repeatedly transmitted to the peripheral apparatus by the transmission unit, wherein each of the first and second symbols includes a pair of symbols including a symbol as a plus running disparity and another symbol as a minus running disparity, and wherein a symbol output from the symbol generation unit has a running disparity different from that of a symbol which is most recently output from the symbol generation unit. (1) Regarding claim 1: Claim 9/1 of US Patent 9,111,048 B2 discloses all subject matter of claim 1 with the recognition that a 8B/10B coded symbol involve transform a bit number of a symbol, except explicitly disclose (a) if a symbol which was most recently selected by the random number generation circuit had a plus running disparity, a symbol selected by the random number generation circuit becomes a minus running disparity, and if a symbol which was most recently selected by the random number generation circuit had a minus running disparity, a symbol selected by the random number generation circuit becomes a plus running disparity, and (b) the transmission is from a device to a host apparatus. With respect to (a), Claim 9/1 of US Patent 9,111,048 B2 discloses “a symbol output from the symbol generation unit has a running disparity different from that of a symbol which is most recently output from the symbol generation unit”. Claim 9/1 of US Patent 9,111,048 B2 discloses “each of the first and second symbols includes a pair of symbols including a symbol as a plus running disparity and another symbol as a minus running disparity”; therefore, a symbol output from the symbol generation unit has a running disparity different from a symbol most recently output from the symbol generation unit has the same meaning of “if a symbol which was most recently selected by the random number generation circuit had a plus running disparity, a symbol selected by the random number generation circuit becomes a minus running disparity, and wherein if a symbol which was most recently selected by the random number generation circuit had a minus running disparity, a symbol selected by the random number generation circuit becomes a plus running disparity”, thus the claimed limitation is met for the benefit of avoiding DC offset. With respect to (b), claim 9/1 of US Patent 9,111,048 B2 discloses the same method of claim 1, but fails to disclose the method is for transmission to a host apparatus, However, such limitation is merely an intended use for the same method, and does not define a patentably distinct invention over the method of claim 9/1 of US Patent 9,111,048 B2 since both invention as a whole are directed to transmit a coded signal by the same method. Therefore, the transmission to a host apparatus would have been a matter of obvious design choice to one of ordinary skill in the art for the benefit of reducing DC offset. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Yoshida (US 2008/0046778 A1) discloses memory controller and semiconductor memory device. Sakai et al. (US 2002/0018492 A1) discloses transmission method and transmission system as well as communications device, but fails to disclose a symbol generation unit which includes a random number generation circuit, the symbol generation unit configured to select one of a first symbol and a second symbol in a random order with use of the random number generation circuit and output the selected one of the symbols; wherein the first symbol and the second symbol indicate an idle state, and wherein each of the first and second symbols includes a pair of symbols including a symbol as a plus running disparity and another symbol as a minus running disparity. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SIU M LEE whose telephone number is (571)270-1083. The examiner can normally be reached M-T 8:30-7:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chieh M Fan can be reached at 571-272-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SIU M LEE/Primary Examiner, Art Unit 2632 8/29/2026
Read full office action

Prosecution Timeline

Oct 22, 2024
Application Filed
Sep 02, 2026
Non-Final Rejection mailed — §101, §DP (current)

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Prosecution Projections

1-2
Expected OA Rounds
91%
Grant Probability
99%
With Interview (+11.0%)
2y 1m (~2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1081 resolved cases by this examiner. Grant probability derived from career allowance rate.

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