DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/22/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-13, 16, and 18-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chantre et al. (US 2014/0376857 A1 Hereinafter Chantre) in view of Budd et al. (US 2017/0047312 A1 Hereinafter Budd) and further in view of Yu et al. (US 2022/0392881 A1 Hereinafter Yu).
Regarding claim 1, Chantre teaches a method of manufacturing a photonic device, the method comprising, successively:
forming on a first substrate (3, Fig. 1, paragraph 0036) at least one metallization level (M1-M4 in insulating region 4, Fig. 1, paragraph 0036), the height of interconnect region RITX being typically about 3 microns (paragraph 0036);
bonding a handle substrate (6, Fig. 2, paragraph 0037) to the upper side of the insulating region;
removing the first substrate (3, Fig. 3, paragraph 0038); and
forming a first optical component (additional waveguide 71, Fig. 5, paragraph 0041, or laser gain medium 800, Fig. 7, paragraph 0047) on a first surface of the at least one metallization level opposite to a second surface of the at least one metallization level that faces the handle, silicon layer (1, Fig. 5, paragraph 0041) and insulating layer (70, Fig. 5, paragraph 0042) lying between that optical component and the metallization.
Chantre fails to teach a first bonding layer, a second bonding layer on a second high-resistivity substrate, and a sum greater than 3 μm.
Budd teaches a second high-resistivity substrate (132, Fig. 1, paragraph 0033) of high-resistivity silicon, a high-resistivity greater than 1 kΩ·cm interposer material being desirable to decrease energy lost in high-frequency signals (paragraph 0034), and a metallization level (BEOL structure 123, Fig. 1, paragraph 0038) having a thickness of about 10 um to about 15 um.
Yu teaches a first bonding layer and a second bonding layer (topmost dielectric layers 115 and a surface dielectric layer of the joined part, Fig. 8, paragraph 0043), those dielectric layers being silicon oxide (paragraph 0039), bonded oxide-to-oxide to each other (paragraph 0043).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to have replaced the handle and the about 3 micron interconnect of the device of Chantre with the high-resistivity silicon substrate and the about 10 to 15 micrometer metallization thickness of Budd, in order to reduce high-frequency loss in the retained support and to use a back-end metallization thickness already used on a photonic chip.
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to have added the two silicon-oxide bonding layers of Yu to the device of Chantre, in order to join the metallization face to the high-resistivity handle by two facing oxide films.
Regarding claim 2, Budd teaches the sum is greater than 4 μm (BEOL structure 123 about 10 um to about 15 um, Fig. 1, paragraph 0038).
Regarding claim 3, Yu teaches:
the first bonding layer is silicon oxide, and
the second bonding layer is silicon oxide (dielectric layers 115, Fig. 8, paragraph 0039 and paragraph 0043).
Regarding claim 4, Budd teaches the second high-resistivity substrate is a semiconductor substrate (high-resistivity silicon 132, Fig. 1, paragraph 0033).
Regarding claim 5, Budd teaches the second high-resistivity substrate has a resistivity greater than 500 Ohms-cm (greater than 1 kΩ·cm, paragraph 0034).
Regarding claim 6, Budd teaches the second high-resistivity substrate has a resistivity greater than 700 Ohms-cm (greater than 1 kΩ·cm, paragraph 0034).
Regarding claim 7, Chantre teaches the first optical component is a waveguide (additional waveguide 71, Fig. 5, paragraph 0041).
Regarding claim 8, Chantre teaches the at least one metallization level comprises at least one first electronic, optical, or optoelectronic component. The optical alternative is additional means 71 in first insulating region 4 with the metallization (Fig. 9, paragraph 0050). The claim is met by that optical component. It also permits an electronic or optoelectronic component in the alternative.
Regarding claim 9, Chantre teaches the at least one metallization level is electrically coupled to a via crossing a layer having the first optical component formed therein (contacts 903 connect metal tracks to contact pads on the back side, through second insulating region 9 in which the optical component is formed, Fig. 8, paragraph 0048).
Regarding claim 10, Chantre teaches, during the forming of the first optical component, forming a third layer on the first surface of the at least one metallization level (additional silicon layer etched as waveguide 71, or heterostructure 8, paragraph 0042 and paragraph 0044), silicon layer 1 lying between that layer and the metallization (paragraph 0041).
Regarding claim 11, Chantre teaches:
the third layer is indium phosphide (InP), a material comprising indium phosphide (InP), and indium gallium arsenide phosphide (InGaAsP) (p-type InP substrate 80, InGaAsP quantum-well stack 81, and n-type InP/InGaAs layer 82 of heterostructure 8, paragraph 0045); or
the third layer is a multiple quantum well stack, comprising layers of indium phosphide (InP) and indium gallium arsenide phosphide (InGaAsP) (stack 81, paragraph 0045).
Regarding claim 12, Chantre teaches the first optical component is a laser (gain medium 800, Fig. 7, paragraph 0047).
Regarding claim 13, Chantre teaches the at least one metallization level is formed on a front surface of the first substrate (front side F1 and metallization levels M1-M4 above carrier 3, Fig. 1, paragraph 0036).
Regarding claim 16, Chantre teaches a photonic device comprising:
a first optical component (waveguide 71 or laser gain medium 800, Fig. 8, paragraph 0048) disposed on a stack; and
the stack, successively comprising:
a first surface of at least one metallization level (device-side face of metallization levels M1-M4 in insulating region 4, Fig. 8, paragraph 0048), silicon layer 1 lying between the optical component and that surface (paragraph 0041); and
a handle substrate (6, Fig. 2, paragraph 0037) on the opposite side of the metallization, the height of interconnect region RITX being typically about 3 microns (paragraph 0036).
Claim 16 does not require the manufacturing order of claim 1. Chantre fails to teach a first bonding layer, a second bonding layer, a second high-resistivity substrate, and a sum greater than 3 μm.
Budd teaches a second high-resistivity substrate (132, Fig. 1, paragraph 0033) of high-resistivity silicon greater than 1 kΩ·cm (paragraph 0034), and a metallization level (BEOL structure 123, Fig. 1, paragraph 0038) having a thickness of about 10 um to about 15 um.
Yu teaches a first bonding layer and a second bonding layer (topmost dielectric layers 115 and a surface dielectric layer, Fig. 8, paragraph 0043) of silicon oxide (paragraph 0039), bonded oxide-to-oxide (paragraph 0043).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to have replaced the handle and the about 3 micron interconnect of the device of Chantre with the high-resistivity silicon substrate and the about 10 to 15 micrometer metallization thickness of Budd, in order to retain a low-loss support under the stack and to separate the optical component from that support by a back-end thickness already used on a photonic chip.
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to have added the two silicon-oxide bonding layers of Yu to the device of Chantre, in order to place two facing oxide films between the metallization and the high-resistivity handle.
Regarding claim 18, Budd teaches the second high-resistivity substrate has a resistivity greater than 500 Ohms-cm (greater than 1 kΩ·cm, paragraph 0034).
Regarding claim 19, Chantre teaches the first optical component is a waveguide (71, Fig. 8, paragraph 0041).
Regarding claim 20, Chantre teaches the first optical component (71, Fig. 8, paragraph 0048) on the surface of the metallization opposite the handle-facing surface, silicon layer 1 lying between the component and the metallization (paragraph 0041).
Regarding claim 21, Chantre teaches the first optical component in an insulating layer (second insulating region 9, Fig. 8, paragraph 0048) on that first surface.
Claim(s) 14, 15, 22, and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chantre et al. (US 2014/0376857 A1 Hereinafter Chantre) in view of Budd et al. (US 2017/0047312 A1 Hereinafter Budd) and further in view of Yu et al. (US 2022/0392881 A1 Hereinafter Yu) and further in view of Chen et al. (US 2022/0381999 A1 Hereinafter Chen).
Regarding claim 14, Chantre teaches an optical component on the face exposed by removing carrier 3 (additional waveguide 71, Fig. 5, paragraph 0041) and a handle substrate (6, Fig. 2, paragraph 0037) on the other side of the metallization.
Chantre fails to teach a second optical component on the rear surface of the second high-resistivity substrate.
Chen teaches a second optical component (waveguide 140 and photodetector 146, Fig. 2, paragraph 0036) on the second side of a substrate (120, Fig. 1, paragraph 0036).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to have added the second optical component of Chen to the rear surface of the high-resistivity substrate of the device of Chantre, in order to carry an optical signal on the outer face of the retained support.
Regarding claim 15, Chen teaches the second optical component is a waveguide (140, core 140a and cladding 140b, Fig. 2, paragraph 0045).
Regarding claim 22, Chantre teaches a handle substrate (6, Fig. 2, paragraph 0037) and a first optical component on the metallization side opposite that handle (71, Fig. 8, paragraph 0048).
Chantre fails to teach a second optical component on the rear surface of the second high-resistivity substrate.
Chen teaches a second optical component (waveguide 140 and photodetector 146, Fig. 2, paragraph 0036) on the second side of a substrate (120, Fig. 1, paragraph 0036).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to have added the second optical component of Chen to the rear surface of the high-resistivity substrate of the device of Chantre, in order to carry an optical signal on the outer face of the retained support.
Regarding claim 23, Chen teaches the second optical component is a waveguide (140, core 140a and cladding 140b, Fig. 2, paragraph 0045).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Chantre et al. (US 2014/0376857 A1 Hereinafter Chantre) in view of Budd et al. (US 2017/0047312 A1 Hereinafter Budd), Yu et al. (US 2022/0392881 A1 Hereinafter Yu), and Chan et al. (US 2006/0194414 A1 Hereinafter Chan). This rejection does not use Budd's about 10 to 15 micrometer back-end thickness.
Regarding claim 17, Chantre teaches a photonic device comprising:
a first optical component (additional waveguide 71, Fig. 5, paragraph 0041, or laser gain medium 800, Fig. 7, paragraph 0047) disposed on a stack; and
the stack, successively comprising:
a first surface of at least one metallization level (metallization levels M1-M4 in insulating region 4, Fig. 1 and Fig. 8, paragraph 0036 and paragraph 0048), silicon layer 1 and insulating layer 70 lying between the optical component and that surface (Fig. 5, paragraph 0041 and paragraph 0042); and
a handle substrate (6, Fig. 2, paragraph 0037) bonded to the opposite side of the metallization, the height of interconnect region RITX being typically about 3 microns (paragraph 0036).
Chantre fails to teach a second high-resistivity substrate, two bonding layers, and a sum on an order of 4 μm.
Budd teaches a second high-resistivity substrate (interposer substrate 132, Fig. 1, paragraph 0033) of high-resistivity silicon, a resistivity greater than 1 kΩ·cm being desirable to decrease energy lost in high-frequency signals (paragraph 0034).
Yu teaches a multilayer interconnect (120, Fig. 7, paragraph 0039) of conductive features 114 in dielectric layers 115, having a thickness between about 4 μm and about 7 μm, and oxide-to-oxide bonding between the topmost dielectric layer (115, Fig. 8, paragraph 0043) and a surface dielectric layer of the mating part (paragraph 0043). The stated interconnect thickness includes that topmost dielectric layer.
Chan teaches an oxide bonding film (15 on wafer 20, Fig. 1A, paragraph 0026 and paragraph 0029) having a thickness of from about 10 to about 500 nm as deposited, and permits the mating surface to be an oxide layer rather than the bare surface shown in the drawing (surface 12 of wafer 10, Fig. 1A, paragraph 0023). The oxide is formed and annealed at or below about 400°C (paragraph 0026 and paragraph 0030), which is the temperature range identified for stacks that already contain back-end metals and low-k dielectrics (paragraph 0006). The bond can survive later grinding or polishing without delamination (paragraph 0010). Polishing of that oxide is optional and can thin the deposited film (paragraph 0031). The about 10 to about 500 nm range is the thickness as deposited, not a thickness measured after polishing.
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to have replaced the handle of the device of Chantre with the high-resistivity silicon substrate of Budd, in order to retain mechanical support while reducing high-frequency electrical loss in the support.
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to have replaced the interconnect of the device of Chantre with the oxide-bonded interconnect of Yu, in order to provide electrical routing and a dielectric bonding surface in a comparatively thin stack, while keeping the optical component on the side opposite the handle.
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to have added the thin oxide bonding layer of Chan to the high-resistivity handle of the device of Chantre, in order to provide a distinct mating oxide surface and a strong low-temperature bond compatible with the existing back-end structure and later carrier removal, without adding unnecessary thickness to the interconnect.
In that combination, the metallization level is the portion of interconnect 120 beneath its topmost dielectric layer 115, and that topmost dielectric layer is the first bonding layer. Those two portions together occupy a thickness selected near the about 4 μm end of Yu's range, so the top dielectric is counted once and is not also added as a new film. The second bonding layer is a separate oxide film on the handle. A nominal 100 nm thickness is a selection within Chan's about 10 to about 500 nm deposited range. Chan does not disclose an express 100 nm embodiment. The sum of the metallization level and the two bonding layers is about 4 μm plus 0.1 μm, or about 4.1 μm. That 4.1 μm figure is a calculated combination. It is not a stack thickness printed in any reference, and it is not inherent. The present specification states that, unless specified otherwise, “on the order of” signifies plus or minus 10%, preferably plus or minus 5% (paragraph 0051). About 4.1 μm is inside both 3.6 to 4.4 μm and 3.8 to 4.2 μm. The specification is used for that meaning only. It is not prior art.
Relevant Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Bauters (US 9,285,540 B2) joins two oxide films, but that stack is not the claimed metallization and high-resistivity handle. Watts (US 2022/0244454 A1) uses a replacement support after handle removal. Lentine (US 10,788,689 B1) shows a lithium-niobate modulator. Menezo (US 2021/0234334 A1) shows a via through an optical layer. Chantre (US 2016/0233641 A1) is a different family from US 2014/0376857 A1. Kalnitsky (US 9,269,591 B2) shows a high-resistivity silicon handle. Budd is used for that property.
Conclusion
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/ERIC T EIDE/ Examiner, Art Unit 2875
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