DETAILED ACTION
Status of Application
Claims 1-20 are pending in the present application.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 14, and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
In regards to claims 2, 9, 12, 13, 15, and 20, applicant has not provided specific arguments as to how said claims patentably distinguish themselves from the references. Therefore, cited prior art is maintained.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 12, 14, and 20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ali et al (hereinafter Ali), US 20240403235 A1.
Referring to claim 1, Ali discloses an electronic circuit, comprising:
a first chiplet [fig. 1, element 121] having a first surface and a plurality of edges at a perimeter of the first surface [fig. 1, see 121 having a surface and four edges at its perimeter], and at least one shoreline interface at one or more of the plurality of edges [fig. 1, element 1211], the at least one shoreline interface extending edge to edge along a length of the first chiplet [fig. 1, see 1211 extending along the length of 121, from the top edge of 121 to the bottom edge of 121]; and
at least one second chiplet [fig. 1, element 110] having a second surface and a plurality of edges at a perimeter of the second surface [fig. 1, see 110 having a surface and four edges at its perimeter], and at least one die-to-die interface being located at one of the plurality of edges [fig. 1, element 1101];
wherein the at least one shoreline interface is adapted to couple to the at least one die-to-die interface [fig. 1, see double sided arrow 1011]; and
wherein at least one of the first or second chiplet is a high bandwidth memory chiplet [fig. 1, HBM Die 121] and at least one of the first or second chiplet is a compute chiplet [fig. 1, Soc Die 110; paragraph 30, “The SOC die includes several components that may vary depending on the specific application and requirements. Commonly it includes a processor, for example, a central processing unit (CPU), responsible for executing instructions and performing computations”].
Referring to claim 12, Ali discloses the electronic circuit of claim 1, wherein the shoreline interface is configured to extend along an entire length of the first chiplet [fig. 1, see 1211 extending along the length of 121, from the top edge of 121 to the bottom edge of 121].
Referring to claim 14, Ali discloses a high bandwidth memory (HBM) chiplet [fig. 1, element 121], comprising:
a first surface [fig. 1, see 121 having a surface and four edges at its perimeter];
a plurality of edges at a perimeter of the first surface [fig. 1, see 121 having a surface and four edges at its perimeter]; and
at least one shoreline interface at one or more of the plurality of edges [fig. 1, element 1211], the at least one shoreline interface extending edge to edge along a length of the HBM chiplet [fig. 1, see 1211 extending along the length of 121, from the top edge of 121 to the bottom edge of 121];
wherein the at least one shoreline interface is adapted to couple to a die-to-die interface [fig. 1, see die-to-die interface 1101 connected to 1211 via double sided arrows 1011] located at one of a plurality of edges of a first connected chiplet [fig. 1, see element 110 with a plurality of edges at its perimeter and 1101 at the left edge].
Referring to claim 20, Ali discloses a compute chiplet [fig. 1, element 110], comprising:
a first surface [fig. 1, see 110 having a surface and four edges at its perimeter];
a plurality of edges at a perimeter of the first surface [fig. 1, see 110 having a surface and four edges at its perimeter]; and
at least one die-to-die interface [fig. 1, element 1101] being located at one of the plurality of edges [fig. 1, left edge of 110];
wherein the at least one die-to-die interface is adapted to be coupled to at least one shoreline interface [fig. 1, element 1211] of a first connected chiplet [fig. 1, element 121], the first connected chiplet comprising at least one shoreline interface extending edge to edge along a length of the first connected chiplet [fig. 1, see 1211 extending along the length of 121, from the top edge of 121 to the bottom edge of 121].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 13, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ali, in view of Dokania et al (hereinafter Dokania), US 20230059491 A1.
Referring to claims 2 and 15, taking claim 2 as exemplary, Ali does not explicitly disclose the electronic circuit of claim 1, wherein the shoreline interface comprises multiple channels.
However, Dokania discloses wherein the shoreline interface comprises multiple channels [paragraphs 89, 99-100, “Each PE is above a corresponding memory unit cell. The architecture of compute die700 allows break up the memory of memory die 401 into as many channels as desired”; “In some embodiments, memory die 720 communicates with compute die 700 above it via GPIOs 725”; “The TSVs through the memory dies can carry signal and power from compute die 402 to C4 bumps. The TSVs between various memory dies can carry signals between the dies in the stack, or power (and ground) to the C4 bumps. In some embodiments, communication channel between compute die 402 or memory dies across the stack is connected through TSVs and micro-bumps or wafer-to-wafer Cu-hybrid bonds”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Dokania in the circuit of Ali, to implement wherein the shoreline interface comprises multiple channels, in order to provide ultra-high bandwidth between DRAM and compute block [Dokania, paragraph 57].
Referring to claim 13, Ali does not explicitly disclose the electronic circuit of claim 1, wherein the shoreline interface is configured to extend along less than an entire length of the first chiplet.
However, Dokania discloses wherein the shoreline interface is configured to extend along less than an entire length of the first chiplet [fig. 6B, element 627].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Dokania in the circuit of Ali, to implement wherein the shoreline interface is configured to extend along less than an entire length of the first chiplet, in order to provide ultra-high bandwidth between DRAM and compute block [Dokania, paragraph 57].
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ali, in view of Dokania, and further in view of Hubbard, US 20200183622 A1.
Referring to claim 9, the modified Ali does not explicitly disclose the electronic circuit of claim 2, wherein the multiple channels of the shoreline interface are configured to be activated or deactivated.
However, Hubbard discloses wherein the multiple channels of the shoreline interface are configured to be activated or deactivated [fig. 3, memory circuit package with active and inactive channels].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Hubbard in the circuit of the modified Ali to implement, wherein the multiple channels of the shoreline interface are configured to be activated or deactivated, in order to lower power consumption [Hubbard, paragraph 31].
Allowable Subject Matter
Claims 3-8, 10-11, and 16-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record taken alone or in combination fails to teach and/or fairly suggest the electronic circuit of claim 2, further comprising a third chiplet having an interface coupled to a second shoreline interface of the first chiplet, in combination with other recited limitations in claim 3.
Claims 4-8 and 10-11 are objected to by virtue of their dependency.
The prior art of record taken alone or in combination fails to teach and/or fairly suggest the HBM chiplet of claim 15, further comprising a second shoreline interface adapted to be coupled to an interface of a second connected chiplet, in combination with other recited limitations in claim 16.
Claims 17-19 are objected to by virtue of their dependency.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FARLEY J ABAD whose telephone number is (571)270-3425. The examiner can normally be reached Mon-Fri 8:30 AM - 7 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached at (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Farley Abad/ Primary Examiner, Art Unit 2181
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