DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending for examination.
This Office Action is Non-Final.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. IT102023000022971, filed on 10/31/2023.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/22/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 16 is objected to because of the following informalities:
Claim 16: change to the following to add clarity to end of each hardware component limitation (device, SoC, SoC – first data structure, device – aux units)
16. A device, comprising:
a system on chip (SoC) including:
a set of detection circuits;
a set of collector error modules (CEMs) coupled to the plurality of detection circuits, each CEM including a plurality of signal processing blocks, each coupled to the set of detection circuits, and a CEM register; a fault control and collection unit (FCCU) coupled to the set of collector error modules, the FCCU including an FCCU register; and
a first data structure in the FCCU register and in each CEM register, the first data structure including:
a first set of data including which of the plurality of signal processing blocks is associated with which of a plurality of inputs of the FCCU[[;]],
a second set of data including a number of input nodes of each of the plurality of signal processing blocks connected to an input of the FCCU[[;]]-, and
a third set of data including identifications of a plurality of tables in a second data structure; and
a plurality of auxiliary electronic control units coupled to the SoC.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 and 7-12 are rejected under 35 U.S.C. 103 as being unpatentable over PANDEY et al. (EP 4206928 A1, as cited in the IDS mailed on 10/22/2024, hereinafter “PANDEY”) in view of SAKAMAKI (US 20110231743 A1).
Regarding Claim 1, PANDEY discloses a method (Fig. 1-2), comprising:
coupling a set of sensing circuits to a set of electronic devices ([0016]: plurality of safety monitors 104 (Fig. 1: shown as circuits) monitor the state of various circuits of SOC 100. [0022]: further coupling of safety monitors 104 to various circuits or memory devices depending on safety monitor functionality);
sensing, via the sensing circuits, a set of sensing signals indicative of an operating state of electronic devices in the set of electronic devices ([0034]: faults generated by plurality of safety monitors 104. [0016]: when safety monitor 104 detects a malfunction ([0022]: of the sensed circuit/memory device), the safety monitor 104 may generate a fault signal FAULT);
applying a logic signal processing to the set of sensing signals ([0035]: encoder 210 aggregates fault signals FAULT and routes aggregated fault signals A_FAULT to fault interface 212… in some embodiments, a [logical] OR gate is used to aggregate a plurality of faults) via coupling a set of signal processing channels to the set of sensing circuits and providing a set of logically combined sensing signals as a result (Fig. 2; [0031]; [0035]: set of signal processing channels “user register 204 – decoder 206- internal register 208 – encoder 210” shown coupled to safety monitors 104, wherein encoder 210 of the set logically aggregates via OR gate and provides a fixed (Q) set of A_FAULT signals), wherein the logically combined sensing signals are indicative of whether the operating state of the electronic devices in the set of electronic devices is an expected operating state or an unexpected operating state ([0035]: OR gate used to aggregate a plurality of faults, where the output of the OR gate is 1 if any of the bits associated with the plurality of faults is 1), wherein the signal processing channels are each included in one of a plurality of collector error module (CEM) circuits, each CEM circuit including a corresponding CEM register (Fig. 2: 204-206-208-210 channel set shown included in error management circuit 120 (“CEM circuit”). [0015]: error management circuit 120 may be one or more error management circuits 120. Fig. 2; [0033]: each error management circuit 120 may include a plurality of user registers 204 + internal registers 208);
providing the logically combined sensing signals in the set of logically combined sensing signals to input channels in a set of input channels of a fault collection and control unit (FCCU) ([0035]: provide aggregated fault signals A_FAULT to fault interface 212 (Fig. 2: fault interface 212 shown as part of FCCU 102 for receiving A_FAULT). [0031]: FCCU 102 has a fixed number (Q) of fault input terminals for receiving faults such that all Q terminals are used. [0038]: fault interface 212 may have N terminals for receiving N fault signals from various sources. I.e., provides A_FAULTs to all fault input terminals of FCCU 102);
storing at least one data structure including data related to the way in which the set of input channels of the FCCU are coupled to the set of sensing circuits via the set of signals processing channel ([0041]: internal registers 208 may include bits for programming error management circuit 120 (e.g., for configuring how to aggregate fault signals). [0031]: For example, implementing FCCU 102 with 256 fault input terminals and having a single error management circuit 120 receiving 1000 fault signals FAULT from associated safety monitors 104 may perform an aggregation such that 256 aggregated fault signals A_FAULT are generated (from the 1000 fault signals FAULT received) by the single error management circuit 120. More generally, in embodiments where FCCU 102 has Q fault input terminals and L safety monitors 104, the aggregated operation performed by each error management circuit 120 may be designed such that FCCU 102 receives Q fault signals. Thus, internal registers 208 stores bits (data structure) for configuring how to aggregate fault signals. Aggregating fault signals involve the way in which all of the set of fault input terminals of FCCU 102 are used to transmit aggregated fault signals from safety monitors 104, wherein encoder 210 of signal processing channel set 204-206-208-210 performs the aggregation and transmission); and
in response to at least one combined sensing signal in the set of combined sensing signals being indicative of the unexpected operating state of the electronic devices in the set of electronic devices ([0043]: processor 110 may, upon identifying that FCCU 102 received a fault from a particular error management circuit 120, issue a read command to such particular error management circuit 120 via user registers 204 to retrieve the status of one or more safety monitors 104 (e.g., to determine which safety monitor 104 has the associated fault signal asserted). [Wingdings font/0xE0] in response to identifying FCCU received an aggregated fault (Fig. 2; [0038]: received by fault interface 212, part of FCCU 102) from the set of aggregated faults ([0031]: fixed number, or Q, aggregated fault signals) indicative of the fault state of the monitored circuits/memory devices in the set of monitored circuits/memory devices ([0022])):
identifying the FCCU input channel among the set of input channels of the FCCU from which the at least one combined sensing signal indicative of the unexpected operating state originates ([0043]: processor 110 may, upon identifying that FCCU 102 received a fault from a particular error management circuit 120, issue a read command to such particular error management circuit 120 via user registers 204 to retrieve the status of one or more safety monitors. [0031]: fault aggregation performed by the one or more error managing circuits 120 such that all of the fault input terminals of FCCU 102 are used. For example, in an embodiment implementing FCCU 102 with 256 fault terminals and having a single error management circuit 120, 256 aggregated fault signals A_FAULT are generated by the single error management circuit 120. Thus, by identifying a particular error management circuit 120 that sent the aggregated fault signals ([0031]), all of the FCCU fault input terminals are also identified);
identifying the electronic device in the set of electronic devices producing the at least one combined sensing signal indicative of the unexpected operating state ([0088]: processor 110 may determine which safety monitor 104 generated a fault by identifying the source of the fault at each error management circuit layer. For example, processor 110 may access FCCU 102 to identify which error management circuit 120 (from the group of error management circuits 120) generated the fault, then access the identified error management circuit 120 to identify which of the error management circuit 120 coupled to it generated the fault, etc. until identify the particular safety monitor 104 generating the fault. [0022]: and thus, identifies the electronic device being monitored by safety monitor 104, as different safety monitors 104 may be responsible for monitoring specific circuits/memory devices); and
providing an interrupt request signal to the identified electronic device in the set of electronic devices ([0024]: interrupt controller 106 is configured to generate 1+ interrupt signals IRQ to schedule interrupt requests to one or more processors. [0018]: generate IRQ_REQ in response to a particular fault).
PANDEY does not disclose:
accessing the data stored in the at least one data structure;
based on the accessed data, identifying the electronic device in the set of electronic devices producing the at least one combined sensing signal indicative of the unexpected operating state; and
However, SAKAMAKI teaches:
storing at least one data structure including data related to the way in which the set of input channels of the FCCU are coupled to the set of sensing circuits via the set of signal processing channels (Fig. 3: packet 71 is one of two data structure stored, including reception error ([0069]: what chip detected the error). Fig. 1; [0084]-[0086]: memory control chip 13 detects the error of packet 71 received from crossbar chip and writes reception error info (memory control chip, memory board, board #0) into the packet. [0046]: reception circuit unit 611 within a chip (e.g., memory control chip 13) detects and corrects error of the received packet 71 transmitted from another chip (e.g., crossbar chip). [0050]-[0051]: units 613-614 within a chip (e.g., memory control chip 13) receives error signal/packet from unit 611 and sends error info notification to board 4 (Fig. 1: and to unit 41 using input line 82). Thus, reception info (memory control chip 13) is stored packet data related to the way the input line 82 of unit 41 is coupled to reception circuit unit 611, the coupling occurring through units 613-614 as the detection and transmission occurs within the single memory control chip 13.
Fig. 4: table 411 is another data structure stored, including an “error transmission source” column ([0072]; [0074]: indicates what chip sent the notification to chip management unit 41, unit 41 as a FCCU that collects and stores fault info in table 411; Fig. 1, [0087]; [0034]: the chip being CPU control chip 12 shown as having a single line for error information 82 to unit 41), “reception error” column ([0077]: indicates which chip received the error information; [0084]-[0086]: the chip being memory control chip 13, also a sensing circuit to detect faults). Thus, table 411 stores data related to the way in which input line 82 of unit 41 is coupled to error detector memory control chip 13 (reception error) via signal/packet processing channel CPU control chip 12 (lists CPU control chip 12 as error transmission source, which uses line 82 to transmit error notification detected by memory control chip 13));
accessing the data stored in the at least one data structure ([0087]: CPU control chip 12 extracts error information of received packet 71. Extracting encompasses accessing);
based on the accessed data, identifying the electronic device in the set of electronic devices producing the at least one intermediate sensing signal indicative of the unexpected operating state ([0050]; [0087]: CPU control chip 12 extracts and sends notification of the error information of packet 71 as error information in another chip. Fig. 3; [0069]; [0084]-[0086]; Fig. 4: error info lists crossbar chip 21 as the transmission error chip where the erroneous packet 71 originated form. Extracting encompasses identifying to populate the notification. [0092]: access data collected in table 411 and further identifies the site at which the error occurred by tracking packet 71 using table 411).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine implementing the packet and error tables taught by SAKAMAKI. One of ordinary skill in the art would be motivated to make this modification in order to allow the user to track the initial error path, the path in which the error of the packet has occurred, and the like (SAKAMAKI: [0080]).
Regarding Claim 2, PANDEY in view of SAKAMAKI teaches the method of claim 1, as referenced above, further comprising:
performing a feedback action with respect to the identified electronic device in the set of electronic devices, the feedback action including at least one of:
ignoring an unexpected operating status (PANDEY: [0052]: command field (CMD) may be applied to error management circuit 120. For example, command 0x02 may be for disabling (masking) a fault of a particular safety monitor 104. [0036]: when masked, no action is taken by FSM 202 (stay in a normal state) – i.e., ignore the fault generated by a safety monitor 104), restoring an expected operating state, and storing the unexpected operating status (other actions regarded as optional / “or” statement. Instant spec: [0055]; [0061]; [0078]; [0084]: recites the same language; doesn’t support requirement for all three events to occur within a single action).
Regarding Claim 3, PANDEY in view of SAKAMAKI teaches the method of claim 1, as referenced above, wherein the storing the at least one data structure includes:
storing a first data structure including an ordered list of signal processing channels associated to the input channels of the FCCU and an associated list of pointers to data structures in a further set of data structures (SAKAMAKI: Fig. 4: table 411 includes ordered list (by item number) of signal processing channels (chip data in error transmission source column) associated to input channels of FCCU (Fig. 1; [0072]; [0074]; [0034]: error transmission source as the chip that sent the error notif using input line 82 – thus transmission source chips uses/are associated with input line 822 of unit 41 serving as a FCCU, see above). Table 411 also includes an associated list of pointers (list of data in “error path – transmission error” column; [0077]: contains transmission source chip data, which points to reception error chip data as the destination in the error path) to data structures in a further set of data structures (list of data in “error path – reception error;” “further set of data structures” interpreted as a sub-table within table 411)); and
populating the data structures in the further set of data structures with data related to signal processing channels and sensing circuits associated to each of the set of input channels of the FCCU (SAKAMAKI: Fig. 4: “reception error” column populated with chip type and of which board. [0077]; [0086]: chips listed in “reception error” column are both signal processing and sensing channels, as reception error is the chip that processed the packet via error detection. “Reception error” column is also mapped in the same row as (i.e., associated to) “error transmission source,” wherein the error transmission source uses input line 82 to send the error notification to unit 41 (see above, Fig. 1-2, [0074])).
Regarding Claim 4, PANDEY in view of SAKAMAKI teaches the method of claim 1, as referenced above, wherein the identifying the FCCU input channel among the set of input channels of the FCCU from which the at least one combined sensing signal indicative of the unexpected operating state originates includes:
storing values of the logically combined sensing signals in the set of logically combined sensing signals received at respective FCCU input channels in the set of FCCU input channels (PANDEY: Fig. 2; [0031]; [0035]-[0038]: fault interface 212 receives logical-OR-aggregated fault signals via all fault input terminals of FCCU 102 and signals a fault condition to FSM 202 when a fault is received. Receiving encompasses storing for some amount of time to detect and signal a fault condition based on the received aggregated signals); and
accessing a stored value of the unexpected operating state signal and identifying the FCCU input channel in the set of FCCU input channels coupled to the at least one combined sensing signal in the set of combined sensing signals being indicative of an unexpected operating state of the electronic devices in the set of electronic devices (PANDEY: [0088]: processor 110 may access FCCU 102 to identify which error management circuit 120 generated the fault, then access the identified error management circuit 120 to identify which error management circuit generated the fault ([0031]: the fault being aggregated fault signal A_FAULT from plurality of A_FAULT signals), until identifying the particular safety monitor 104 generating the fault ([0022]: which also identifies the faulty circuits/devices being monitored). Accessing FCCU 102 to identify which error management circuit 120 encompasses tracing the fault, thus data representative of the fault is effectively stored and accessed. [0031]: identifying a specific error management circuit 120 also identifies all fault input terminals of FCCU 102 since all fault input terminals are used to transmit the aggregated faults).
Regarding Claim 5, PANDEY in view of SAKAMAKI teaches the method of claim 1, as referenced above, wherein accessing the data stored in the at least one data structure includes:
based on the at least one data structure, identifying which signal processing channel in the set of signal processing channels is coupled to the FCCU input channel in the set of FCCU input channels coupled to the at least one combined sensing signal in the set of combined sensing signals being indicative of an unexpected operating state of the electronic devices in the set of electronic devices (SAKAMAKI: [0083]-[0084]: CPU #3, board #1 requests CPU control chip, board #2 to execute read operation. CPU control chip, board #1 sends packet 71 to crossbar chip 21, which sends to memory control chip 13, board #0. [0085]-[0086]: mem control chip 13, board #0 detects error in packet 71 and writes error information in packet 71 (data structure). Error info includes error path, reception error board type, chip type, etc. Fig. 4; [0072]-[0079]: specific error info includes error notification source (the chip that sent the notification to chip management unit 41; Fig. 1: shown part of board 4), error path -- transmission error (board type of transmission source chip, board number, chip type), and reception error (board type of board that received packet having error info, board number, chip type). [0087]: CPU control chip 12, board #0 receives packet 71 from memory control chip 13, board #0 and extracts the error info to send to board 4.
Extracting encompasses identifying said info to send to board 4. Thus, the extracted info from packet 71 (Fig. 3; [0063]: packet data structure) identifies which signal processing channel in the set of signal processing channels (memory chip as error path -- reception error chip) is coupled to the FCCU input channel in the set of FCCU input channels (control chip as error transmission source / input channel to transmit notif to board 4; [0092]: board 4 as FCCU for collecting error info and tracing error path; Fig. 2, [0044]: out of set of all chips also able to send notif to board 4 via units 613-614) coupled to the at least one combined sensing signal in the set of combined sensing signals (packet 71) being indicative of an unexpected operating state (packet 71 data error) of the electronic devices in the set of electronic devices (crossbar chip 21 as error path -- transmission error));
accessing data related to the way in which signal processing channels in the set of signal processing channels are coupled to the set of sensing circuits (SAKAMAKI: [0087]: extracting error information from packet 71 to send to board 4 encompasses accessing the error information. As described above, CPU control chip 12, board #0 accesses error information from packet 71, which relates to the way signal processing channels in the set of signal processing channels (Fig. 2: memory control chip chip) are coupled to the set of sensing circuits (crossbar chip; [0083]-[0084]: senses incoming packet));
collecting the accessed data that corresponds to the signal processing channel coupled to the identified error source, and providing a data structure indicative of the coupling of the identified electronic device in the set of electronic devices and the identified error source (SAKAMAKI: [0092]: in chip management board 4, chip management unit 41 collects the error information (corresponding to signal processing channel coupled to identified error source; see above -- error info notif contains mem control chip as reception error and crossbar chip as transmission error) and provides and stores it in table 411 ("provide a DS"). Fig. 4: table 411 lists devices in transmission error column as the identified error path source).
Regarding Claim 7, PANDEY discloses a system (Fig. 1-2), comprising:
a set of sensing circuits coupled to a set of electronic devices to sense a set of sensing signals indicative of an operating state of electronic devices in the set of electronic devices ([0016]; [0022]; [0033]: safety monitors 104 detect malfunctions of monitored circuits/devices and generates faults (sensed signals));
logic signal processing circuitry coupled to the set of sensing signals via a set of signal processing channels, the logic signal processing circuitry configured to provide a set of logically combined sensing signals (Fig. 1-2; [0015]: set of error management circuits 120 shown coupled to safety monitors 104 via signal processing channels 204-206-208-210. [0031]: error management circuits aggregate fault signals FAULT from safety monitors 104 into aggregated fault signals A_FAULT. [0035]: logical aggregation via OR gate), the logical signal processing circuitry including a plurality of collector error module (CEM) circuits ([0015]: set of error management circuits 120 includes one or more (plurality) of error management circuits 120 ), each CEM circuit including a corresponding CEM register and signal processing channels of the set of signal processing channels (Fig. 2; [0033]: each error management circuit 120 shown including users registers 204 + internal registers 208, and signal processing channels 204-206-208-210 of the total set 204-206-208-210 signal processing channels (across all error management circuit 120));
wherein the logically combined sensing signals are indicative of whether the operating state of the electronic devices in the set of electronic devices is an expected operating state or an unexpected operating state ([0035]: OR gate used to aggregate a plurality of faults, where the output of the OR gate is 1 if any of the bits associated with the plurality of faults is 1);
a fault collection and control unit (FCCU) coupled to the logic signal processing circuitry to receive logically combined sensing signals in the set of logically combined sensing signals at FCCU input channels in a set of FCCU input channels (Fig. 2; [0038]: FCCU 102 coupled to error management circuits 120 receives aggregated fault signals at fault interface 212 terminals);
at least one set of registers storing at least one data structure including data related to a way in which the set of FCCU input channels are coupled to the set of sensing circuits via the set of signal processing channels (([0041]: internal registers 208 may include bits for programming error management circuit 120 (e.g., for configuring how to aggregate fault signals). [0031]: For example, implementing FCCU 102 with 256 fault input terminals and having a single error management circuit 120 receiving 1000 fault signals FAULT from associated safety monitors 104 may perform an aggregation such that 256 aggregated fault signals A_FAULT are generated (from the 1000 fault signals FAULT received) by the single error management circuit 120. More generally, in embodiments where FCCU 102 has Q fault input terminals and L safety monitors 104, the aggregated operation performed by each error management circuit 120 may be designed such that FCCU 102 receives Q fault signals. Thus, internal registers 208 stores bits (data structure) for configuring how to aggregate fault signals. Aggregating fault signals involve the way in which all of the set of fault input terminals of FCCU 102 are used to transmit aggregated fault signals from safety monitors 104, wherein encoder 210 of signal processing channel set 204-206-208-210 performs the aggregation and transmission); and
processing circuitry configured to, in response to at least one combined sensing signal in the set of combined sensing signals being indicative of an unexpected operating state of the electronic devices in the set of electronic devices (([0043]: processor 110 may, upon identifying that FCCU 102 received a fault from a particular error management circuit 120, issue a read command to such particular error management circuit 120 via user registers 204 to retrieve the status of one or more safety monitors 104 (e.g., to determine which safety monitor 104 has the associated fault signal asserted). [Wingdings font/0xE0] in response to identifying FCCU received an aggregated fault (Fig. 2; [0038]: received by fault interface 212, part of FCCU 102) from the set of aggregated faults ([0031]: fixed number, or Q, aggregated fault signals) indicative of the fault state of the monitored circuits/memory devices in the set of monitored circuits/memory devices ([0022])):
identify the FCCU input channel among the set of input channels of the FCCU from which the at least one combined sensing signal indicative of the unexpected operating state originates ([0043]: processor 110 may, upon identifying that FCCU 102 received a fault from a particular error management circuit 120, issue a read command to such particular error management circuit 120 via user registers 204 to retrieve the status of one or more safety monitors. [0031]: fault aggregation performed by the one or more error managing circuits 120 such that all of the fault input terminals of FCCU 102 are used. For example, in an embodiment implementing FCCU 102 with 256 fault terminals and having a single error management circuit 120, 256 aggregated fault signals A_FAULT are generated by the single error management circuit 120. Thus, by identifying a particular error management circuit 120 that sent the aggregated fault signals ([0031]), all of the FCCU fault input terminals are also identified);
, identify the electronic device in the set of electronic devices producing the unexpected operating status sensing signal (([0088]: processor 110 may determine which safety monitor 104 generated a fault by identifying the source of the fault at each error management circuit layer. For example, processor 110 may access FCCU 102 to identify which error management circuit 120 (from the group of error management circuits 120) generated the fault, then access the identified error management circuit 120 to identify which of the error management circuit 120 coupled to it generated the fault, etc. until identify the particular safety monitor 104 generating the fault. [0022]: and thus, identifies the electronic device being monitored by safety monitor 104, as different safety monitors 104 may be responsible for monitoring specific circuits/memory devices); and
provide an interrupt request signal to the identified electronic device in the set of electronic devices ([0024]: interrupt controller 106 is configured to generate 1+ interrupt signals IRQ to schedule interrupt requests to one or more processors. [0018]: generate IRQ_REQ in response to a particular fault).
PANDEY does not disclose:
access the data stored in the at least one data structure;
based on the accessed data, identify the electronic device in the set of electronic devices producing the unexpected operating status sensing signal;
However, SAKAMAKI teaches:
…storing at least one data structure including data related to a way in which the set of FCCU input channels are coupled to the set of sensing circuits via the set of signal processing channels (Fig. 3: packet 71 is one of two data structure stored, including reception error ([0069]: what chip detected the error). Fig. 1; [0084]-[0086]: memory control chip 13 detects the error of packet 71 received from crossbar chip and writes reception error info (memory control chip, memory board, board #0) into the packet. [0046]: reception circuit unit 611 within a chip (e.g., memory control chip 13) detects and corrects error of the received packet 71 transmitted from another chip (e.g., crossbar chip). [0050]-[0051]: units 613-614 within a chip (e.g., memory control chip 13) receives error signal/packet from unit 611 and sends error info notification to board 4 (Fig. 1: and to unit 41 using input line 82). Thus, reception info (memory control chip 13) is stored packet data related to the way the input line 82 of unit 41 is coupled to reception circuit unit 611, the coupling occurring through units 613-614 as the detection and transmission occurs within the single memory control chip 13.
Fig. 4: table 411 is another data structure stored, including an “error transmission source” column ([0072]; [0074]: indicates what chip sent the notification to chip management unit 41, unit 41 as a FCCU that collects and stores fault info in table 411; Fig. 1, [0087]; [0034]: the chip being CPU control chip 12 shown as having a single line for error information 82 to unit 41), “reception error” column ([0077]: indicates which chip received the error information; [0084]-[0086]: the chip being memory control chip 13, also a sensing circuit to detect faults). Thus, table 411 stores data related to the way in which input line 82 of unit 41 is coupled to error detector memory control chip 13 (reception error) via signal/packet processing channel CPU control chip 12 (lists CPU control chip 12 as error transmission source, which uses line 82 to transmit error notification detected by memory control chip 13))
access the data stored in the at least one data structure ([0087]: CPU control chip 12 extracts error information of received packet 71. Extracting encompasses accessing);
based on the accessed data, identify the electronic device in the set of electronic devices producing the unexpected operating status sensing signal ([0050]; [0087]: CPU control chip 12 extracts and sends notification of the error information of packet 71 as error information in another chip. Fig. 3; [0069]; [0084]-[0086]; Fig. 4: error info lists crossbar chip 21 as the transmission error chip where the erroneous packet 71 originated form. Extracting encompasses identifying to populate the notification. [0092]: access data collected in table 411 and further identifies the site at which the error occurred by tracking packet 71 using table 411);
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine implementing the packet and error tables taught by SAKAMAKI. One of ordinary skill in the art would be motivated to make this modification in order to allow the user to track the initial error path, the path in which the error of the packet has occurred, and the like (SAKAMAKI: [0080]).
Regarding Claim 8, PANDEY in view of SAKAMAKI teaches the system of claim 7, as referenced above, wherein the processing circuitry is further configured to perform a feedback action with respect to the identified electronic device in the set of electronic devices, the feedback action including at least one of:
ignoring the unexpected operating status (PANDEY: [0052]: command field (CMD) may be applied to error management circuit 120. For example, command 0x02 may be for disabling (masking) a fault of a particular safety monitor 104. [0036]: when masked, no action is taken by FSM 202 (stay in a normal state) – i.e., ignore the fault generated by a safety monitor 104), restoring an expected operating state, and storing the unexpected operating status (other actions regarded as optional / “or” statement. Instant spec: [0055]; [0061]; [0078]; [0084]: recites the same language; doesn’t support requirement for all three events to occur within a single action).
Regarding Claim 9, PANDEY in view of SAKAMAKI teaches the system of claim 7, as referenced above, wherein the at least one data structure stored in the at least one set of registers includes:
a first data structure including an ordered list of signal processing channels associated to the input channels of the FCCU and an associated list of pointers to data structures in a second set of data structures (SAKAMAKI: Fig. 4: table 411 includes ordered list (by item number) of signal processing channels (chip data in error transmission source column) associated to input channels of FCCU (Fig. 1; [0072]; [0074]; [0034]: error transmission source as the chip that sent the error notif using input line 82 – thus transmission source chips uses/are associated with input line 822 of unit 41 serving as a FCCU, see above). Table 411 also includes an associated list of pointers (list of data in “error path – transmission error” column; [0077]: contains transmission source chip data, which points to reception error chip data as the destination in the error path) to data structures in a second set of data structures (list of data in “error path – reception error;” “second set of data structures” interpreted as a sub-table within table 411)), and wherein the data structures in the second set of data structures are populated with data related to the signal processing channels and the sensing circuits associated to each FCCU input channel in the set of FCCU input channels (SAKAMAKI: Fig. 4: “reception error” column populated with chip type and of which board. [0077]; [0086]: chips listed in “reception error” column are both signal processing and sensing channels, as reception error is the chip that processed the packet via error detection. “Reception error” column is also mapped in the same row as (i.e., associated to) “error transmission source,” wherein the error transmission source uses input line 82 to send the error notification to unit 41 (see above, Fig. 1-2, [0074])).
Regarding Claim 10, PANDEY in view of SAKAMAKI teaches the system of claim 7, as referenced above, wherein the processing circuitry is further configured to, in response to at least one combined sensing signal in the set of combined sensing signals being indicative of an unexpected operating state of the electronic devices in the set of electronic devices:
identify the FCCU input channel among the set of input channels of the FCCU from which the at least one combined sensing signal indicative of the unexpected operating state originates (PANDEY: [0043]: processor 110 may, upon identifying that FCCU 102 received a fault from a particular error management circuit 120, issue a read command to such particular error management circuit 120 via user registers 204 to retrieve the status of one or more safety monitors. [0031]: fault aggregation performed by the one or more error managing circuits 120 such that all of the fault input terminals of FCCU 102 are used. For example, in an embodiment implementing FCCU 102 with 256 fault terminals and having a single error management circuit 120, 256 aggregated fault signals A_FAULT are generated by the single error management circuit 120. Thus, by identifying a particular error management circuit 120 that sent the aggregated fault signals ([0031]), all of the FCCU fault input terminals are also identified);
store values of the logically combined sensing signals in the set of logically combined sensing signals received at respective FCCU input channels in the set of FCCU input channels (PANDEY: Fig. 2; [0031]; [0035]-[0038]: fault interface 212 receives logical-OR-aggregated fault signals via all fault input terminals of FCCU 102 and signals a fault condition to FSM 202 when a fault is received. Receiving encompasses storing for some amount of time to detect and signal a fault condition based on the received aggregated signals); and
access a stored value of the unexpected operating state signal and identify the FCCU input channel in the set of FCCU input channels coupled to the at least one combined sensing signal in the set of combined sensing signals being indicative of an unexpected operating state of the electronic devices in the set of electronic devices (PANDEY: [0088]: processor 110 may access FCCU 102 to identify which error management circuit 120 generated the fault, then access the identified error management circuit 120 to identify which error management circuit generated the fault ([0031]: the fault being aggregated fault signal A_FAULT from plurality of A_FAULT signals), until identifying the particular safety monitor 104 generating the fault ([0022]: which also identifies the faulty circuits/devices being monitored). Accessing FCCU 102 to identify which error management circuit 120 encompasses tracing the fault, thus data representative of the fault is effectively stored and accessed. [0031]: identifying a specific error management circuit 120 also identifies all fault input terminals of FCCU 102 since all fault input terminals are used to transmit the aggregated faults).
Regarding Claim 11, PANDEY in view of SAKAMAKI teaches the system of claim 7, as referenced above, wherein the processing circuitry is further configured to, in response to at least one combined sensing signal in the set of combined sensing signals being indicative of the unexpected operating state of the electronic devices in the set of electronic devices:
based on the at least one data structure, identify which signal processing channel in the set of signal processing channels is coupled to the FCCU input channel in the set of FCCU input channels coupled to the at least one combined sensing signal in the set of combined sensing signals being indicative of the unexpected operating state of the electronic devices in the set of electronic devices (SAKAMAKI: [0083]-[0084]: CPU #3, board #1 requests CPU control chip, board #2 to execute read operation. CPU control chip, board #1 sends packet 71 to crossbar chip 21, which sends to memory control chip 13, board #0. [0085]-[0086]: mem control chip 13, board #0 detects error in packet 71 and writes error information in packet 71 (data structure). Error info includes error path, reception error board type, chip type, etc. Fig. 4; [0072]-[0079]: specific error info includes error notification source (the chip that sent the notification to chip management unit 41; Fig. 1: shown part of board 4), error path -- transmission error (board type of transmission source chip, board number, chip type), and reception error (board type of board that received packet having error info, board number, chip type). [0087]: CPU control chip 12, board #0 receives packet 71 from memory control chip 13, board #0 and extracts the error info to send to board 4.
Extracting encompasses identifying said info to send to board 4. Thus, the extracted info from packet 71 (Fig. 3; [0063]: packet data structure) identifies which signal processing channel in the set of signal processing channels (memory chip as error path -- reception error chip) is coupled to the FCCU input channel in the set of FCCU input channels (control chip as error transmission source / input channel to transmit notif to board 4; [0092]: board 4 as FCCU for collecting error info and tracing error path; Fig. 2, [0044]: out of set of all chips also able to send notif to board 4 via units 613-614) coupled to the at least one combined sensing signal in the set of combined sensing signals (packet 71) being indicative of an unexpected operating state (packet 71 data error) of the electronic devices in the set of electronic devices (crossbar chip 21 as error path -- transmission error));
access data related to a way in which signal processing channels in the set of signal processing channels are coupled to the set of sensing circuits (SAKAMAKI: [0087]: extracting error information from packet 71 to send to board 4 encompasses accessing the error information. As described above, CPU control chip 12, board #0 accesses error information from packet 71, which relates to the way signal processing channels in the set of signal processing channels (Fig. 2: memory control chip chip) are coupled to the set of sensing circuits (crossbar chip; [0083]-[0084]: senses incoming packet));
collect the accessed data that corresponds to the signal processing channel coupled to an identified error source, and provide a data structure indicative of the coupling of the identified electronic device in the set of electronic devices and the identified error source (SAKAMAKI: [0092]: in chip management board 4, chip management unit 41 collects the error information (corresponding to signal processing channel coupled to identified error source; see above -- error info notif contains mem control chip as reception error and crossbar chip as transmission error) and provides and stores it in table 411 ("provide a DS"). Fig. 4: table 411 lists devices in transmission error column as the identified error path source).
Regarding Claim 12, PANDEY in view of SAKAMAKI teaches the system of claim 7, as referenced above, wherein the logically combined sensing signals in the set of logically combined sensing signals are assigned a classification between a normal category, an alert category, and a fault category (PANDEY: [0035]-[0037]: FSM 202 takes specific actions depending on the aggregated fault received and the state of the internal registers 208 (e.g., masked, unmasked, generate interrupt req, reset req, assert error signal). [0034]-[0035]: aggregated fault signals depends on fault signals from safety monitor 104. [0018]; [0075]: internal registers for specifying (assigning) states and actions to safety monitor faults, including normal (masked), alert (e.g., interrupt request in response to a particular fault), and fault (unmasked)).
Claims 6 are rejected under 35 U.S.C. 103 as being unpatentable over PANDEY in view of SAKAMAKI, in further view of Hashimoto (US 20100188200 A1), in further view of Hirakawa et al. (US 6959404 B2, hereinafter “Hirakawa”).
Regarding Claim 6, PANDEY in view of SAKAMAKI teaches the method of claim 1, as referenced above, wherein the at least one data structure includes:
a set of register portions including a normal-to-alert portion (PANDEY: [0075]: internal register 608 contain enable (EN) field to not mask faults (when EN is 1). [0036]-[0037]: unmasked faults move from a normal to fault state, where FSM 202 performs certain actions based on the fault received and state of internal registers 208, including generating an interrupt request (alert). [0018]: internal registers 208 may be programmed to specify what action to take such as generating an interrupt request. The combination of EN field + selected action of internal register 208 forms normal-to-alert portion), a normal-to fault portion (PANDEY: [0075]; [0036]-[0037]: EN field when EN is 1 results in a transition from normal state to fault state upon an unmasked fault), a fault-to-normal portion (PANDEY: [0075]: EN field when EN is 0. [0036]: FSM stays in normal state for masked faults. [0018]; [0037]: action may include resetting the fault, another fault-to-normal portion where FSM 200 moves from a normal state into a fault state, resets to clear the fault, and returns to the normal state))… and
PANDEY in view of SAKAMAKI does not teach:
an alert-to-fault portion
a set of timer registers activated when the normal-to-alert portion includes a non-assigned state.
However, Hashimoto teaches:
an alert-to-fault portion ([0096]: when there is the possible driving area toward the direction to avoid any collision of the driver’s vehicle with an obstacle, the deviation detection ECU 10 sets a value indicating suppression of providing the warning to the warning method flag stored in RAM 13. Thus, RAM 13 stores a flag to transition from a suppressed alert state to remaining in the fault state (driving with obstacle)).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine PANDEY, SAKAMAKI, and Hashimoto by implementing the suppression flag taught by Hashimoto. One of ordinary skill in the art would be motivated to make this modification in order to recover from the fault at a later time when a solution is present (Hashimoto: [0096]).
PANDEY in view of SAKAMAKI, in further view of Hashimoto does not teach:
a set of timer registers activated when the normal-to-alert portion includes a non-assigned state.
However, Hirakawa teaches:
a set of timer registers activated when the normal-to-alert portion includes a non-assigned state (Col 8, lines 36-61: any other writes to watchdog timer reset key bits 321 (which only takes in the ordered sequence 0x5C6 --> 0xA7E) triggers watchdog time-out immediately. Upon watchdog timeout, watchdog flag bit 422 in WDT2CR (watchdog timer second control register) 331 will be set to 1 (activated). When the watchdog timer is in the timeout state, various actions occur including reloading the watchdog timer (Col 6, lines 3-6: which reloads timer register WDTIM 302 with the period value stored in timer register WDPRD 301). Thus, a set of timer registers (WDT2CR, WDTIM, WDPRD) is enabled/used/activated when the normal-to-alert portion (watchdog timer reset key bits -- responsible for state transition from normal watchdog operation to timeout, the timeout triggering an internal maskable watchdog timer interrupt which is an alert) includes a non-assigned state (receives any writes other than assigned 0x5C6 --> 0xA7E)).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine PANDEY, SAKAMAKI, Hashimoto, and Hirakawa by implementing the watchdog timers taught by Hirakawa. One of ordinary skill in the art would be motivated to make this modification in order to prevent system lock-up in case software becomes trapped in loops with no controlled exit (Hirakawa: Col 4, lines 44-45) and prevent watchdog from being accidentally serviced while software is trapped in a dead loop or in some other software failures (Hirakawa: Col 5, lines 1-4).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over PANDEY in view of SAKAMAKI, in further view of Hirakawa.
Regarding Claim 13, PANDEY in view of SAKAMAKI teaches the system of claim 7, as referenced above, wherein the at least one data structure includes a set of register portions (PANDEY: [0018], [0075]: various bitfields and other configuration fields in internal registers)
PANDEY in view of SAKAMAKI does not teach:
…and a set of timer registers.
However, Hirakawa teaches:
wherein the at least one data structure includes a set of register portions and a set of timer registers (Col 5, lines 20-33: memory-mapped timer registers + bitfields of timer registers).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine PANDEY, SAKAMAKI, and Hirakawa by implementing the watchdog timers taught by Hirakawa. One of ordinary skill in the art would be motivated to make this modification in order to prevent system lock-up in case software becomes trapped in loops with no controlled exit (Hirakawa: Col 4, lines 44-45) and prevent watchdog from being accidentally serviced while software is trapped in a dead loop or in some other software failures (Hirakawa: Col 5, lines 1-4).
Claims 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over PANDEY in view of SAKAMAKI, in further view of Hirakawa, in further view of Hashimoto.
Regarding Claim 14, PANDEY in view of SAKAMAKI, in further view of Hirakawa teaches the system of claim 13, as referenced above, normal-to-alert portion (PANDEY: [0075]: internal register 608 contain enable (EN) field to not mask faults (when EN is 1). [0036]-[0037]: unmasked faults move from a normal to fault state, where FSM 202 performs certain actions based on the fault received and state of internal registers 208, including generating an interrupt request (alert). [0018]: internal registers 208 may be programmed to specify what action to take such as generating an interrupt request. The combination of EN field + selected action of internal register 208 forms normal-to-alert portion), a normal-to fault portion (PANDEY: [0075]; [0036]-[0037]: EN field when EN is 1 results in a transition from normal state to fault state upon an unmasked fault), a fault-to-normal portion (PANDEY: [0075]: EN field when EN is 0. [0036]: FSM stays in normal state for masked faults. [0018]; [0037]: action may include resetting the fault, another fault-to-normal portion where FSM 200 moves from a normal state into a fault state, resets to clear the fault, and returns to the normal state)), and…
PANDEY in view of SAKAMAKI, in further view of Hirakawa does not teach:
an alert-to-fault portion.
However, Hashimoto teaches:
an alert-to-fault portion ([0096]: when there is the possible driving area toward the direction to avoid any collision of the driver’s vehicle with an obstacle, the deviation detection ECU 10 sets a value indicating suppression of providing the warning to the warning method flag stored in RAM 13. Thus, RAM 13 stores a flag to transition from a suppressed alert state to remaining in the fault state (driving with obstacle)).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine PANDEY, SAKAMAKI, Hirakawa, and Hashimoto by implementing the suppression flag taught by Hashimoto. One of ordinary skill in the art would be motivated to make this modification in order to recover from the fault at a later time when a solution is present (Hashimoto: [0096]).
Regarding Claim 15, PANDEY in view of SAKAMAKI, in view of Hirakawa, in further view of Hashimoto teaches the system of claim 14, as referenced above, wherein the set of timer registers are activated when the normal-to-alert portion includes a non-assigned state (Hirakawa: Col 8, lines 36-61: any other writes to watchdog timer reset key bits 321 (which only takes in the ordered sequence 0x5C6 --> 0xA7E) triggers watchdog time-out immediately. Upon watchdog timeout, watchdog flag bit 422 in WDT2CR (watchdog timer second control register) 331 will be set to 1 (activated). When the watchdog timer is in the timeout state, various actions occur including reloading the watchdog timer (Col 6, lines 3-6: which reloads timer register WDTIM 302 with the period value stored in timer register WDPRD 301). Thus, a set of timer registers (WDT2CR, WDTIM, WDPRD) is enabled/used/activated when the normal-to-alert portion (watchdog timer reset key bits -- responsible for state transition from normal watchdog operation to timeout, the timeout triggering an internal maskable watchdog timer interrupt, which is an alert) includes a non-assigned state (receives any writes other than assigned 0x5C6 --> 0xA7E)).
Claims 16 is rejected under 35 U.S.C. 103 as being unpatentable over PANDEY in view of SAKAMAKI, in further view of KAWASHIMA (US 20200151132 A1).
Regarding Claim 16, PANDEY discloses a device (Fig. 1-2), comprising:
a system on chip (SoC) (Fig. 1; [0015]: SOC 100) including:
a set of detection circuits (Fig. 1; [0022]: safety monitors 104);
a set of collector error modules (CEMs) coupled to the plurality of detection circuits (Fig. 2; [0032]: error management circuits 102), each CEM including a plurality of signal processing blocks (Fig. 2; [0033]: each error management circuits 120 containing chain of signal processing blocks 204-206-208-210), each coupled to the set of detection circuits, and a CEM register (Fig. 2; [0041]: internal registers);
a fault control and collection unit (FCCU) coupled to the set of collector error modules (Fig. 2; [0033]: FCCU 102 coupled to each error management circuits 102)…
a first data structure in… each CEM register ([0041]: bits in each internal registers 208), the first data structure including:
a first set of data including which of the plurality of signal processing blocks is associated with which of a plurality of inputs of the FCCU ([0041]: internal registers 208 may include bits for programming error management circuit 120 (e.g., for configuring how to aggregate fault signals). [0031]: For example, implementing FCCU 102 with 256 fault input terminals and having a single error management circuit 120 receiving 1000 fault signals FAULT from associated safety monitors 104 may perform an aggregation such that 256 aggregated fault signals A_FAULT are generated (from the 1000 fault signals FAULT received) by the single error management circuit 120. More generally, in embodiments where FCCU 102 has Q fault input terminals and L safety monitors 104, the aggregated operation performed by each error management circuit 120 may be designed such that FCCU 102 receives Q fault signals. Thus, internal registers 208 stores bits (data structure) for configuring how to aggregate fault signals. Aggregating fault signals involve mapping each error management circuit 120 to use all Q fault input terminals of FCCU 102);
a second set of data including a number of input nodes of each of the plurality of signal processing blocks connected to an input of the FCCU (Fig. 2; [0041]; [0031]: safety monitors 104 shown as input nodes of error management circuits 120 ([0033]: and thus input nodes of signal processing blocks 204-206-208-210). Safety monitors 104 having their enable bit asserted (1) may be aggregated by encoder 210 and routed to FCCU 102 via fault input terminals of FCCU 102); and
a of auxiliary electronic control unit coupled to the SoC (Fig. 12; [0103]: CPU 1202 coupled to SoC 1201, SOC 1201 may be implemented as SoC 100. CPU 1202 takes action based on received error signal to control various electronic vehicle components).
PANDEY does not disclose:
…the FCCU including an FCCU register
a first data structure in the FCCU register, the first data structure including:
a first set of data including which of the plurality of signal processing blocks is associated with which of a plurality of inputs of the FCCU;
a second set of data including a number of input nodes of each of the plurality of signal processing blocks connected to an input of the FCCU; and
a third set of data including identifications of a plurality of tables in a second data structure;
a first data structure in each CEM register, the first data structure including:
a third set of data including identifications of a plurality of tables in a second data structure;
and a plurality of auxiliary electronic control units coupled to the SoC.
However, SAKAMAKI teaches:
…the FCCU including an FCCU register (Fig. 1: chip management unit 41 including error information table 411)
a first data structure in the FCCU register (Fig. 2: error information table 411), the first data structure including:
a first set of data including which of the plurality of signal processing blocks is associated with which of a plurality of inputs of the FCCU (Fig. 1; Fig. 4; [0074]: “error transmission source” column includes packet/signal processing chips that transmitted the error information to unit 41, shown via (associated with) input line 82);
a second set of data including a number of input nodes of each of the plurality of signal processing blocks connected to an input of the FCCU (Fig. 1; Fig. 4; [0077]; [0084]-[0087]: second set “error path – transmission error” contains chip info that are that identifies where the erroneous packet 71 occurred. Once received by chips listed in “error transmission source” column, “error transmission source” chips send a notification to unit 41 using input line 82. I.e., “error path – transmission error” chips are input nodes (whether directly or indirectly) to “error transmission source” chips, shown connected to input line 82 of unit 41); and
a third set of data including identifications of a plurality of tables in a second data structure (Fig. 4; [0077]: third set “error path – transmission error” contains chip info that identifies where the erroneous packet 71 occurred, thus identifies the source of the erroneous packet 71 received by reception chips listed in a plurality of tables in sub-table “error-path – reception error” column, a second data structure);
a first data structure in each CEM register (Fig. 3; [0044]-[0053]: each chip includes reception circuit unit 611 configured to receive packet 71 structure. Each chip regarded as CEM to extract, generate, and select error info from packet 71), the first data structure including:
a third set of data including identifications of a plurality of tables in a second data structure (Fig. 3-4; [0051]; [0086]-[0091]: packet 71 contains reception chip info, which identifies a plurality of entries in table 411 (plurality of entries being plurality of sub-tables));
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine implementing the packet and error tables taught by SAKAMAKI. One of ordinary skill in the art would be motivated to make this modification in order to allow the user to track the initial error path, the path in which the error of the packet has occurred, and the like (SAKAMAKI: [0080]).
PANDEY in view of SAKAMAKI does not teach:
and a plurality of auxiliary electronic control units coupled to the SoC.
However, KAWASHIMA teaches:
and a plurality of auxiliary electronic control units coupled to the SoC ([0045]: central ECU 30 may be coupled to one or more auxiliary ECUs via third bus 31).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine PANDEY, SAKAMAKI, and KAWASHIMA by implementing the aux ECUS taught by KAWASHIMA. One of ordinary skill in the art would be motivated to make this modification in order to expand the functions of the central ECU / SOC, implement new functions not provided to the central ECU 30, transmit control data for expansion or implementation of the functions (SAKAMAKI: [0046]).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over PANDEY in view of SAKAMAKI, in view of KAWASHIMA, in further view of Krishnani et al. (US 20240300537 A1, hereinafter “Krishnani”).
Regarding Claim 17, PANDEY in view of SAKAMAKI, in view of KAWASHIMA teaches the device of claim 16, as referenced above, wherein each of the plurality of auxiliary electronic control units includes a processing unit configured to produce a control signal for a vehicle system (KAWASHIMA: [0045]: aux ECUs include a processor, and may transmit control data for expansion or implementation of functions. [0038]; [0054]: central ECU 30 outputs control data such that control data passes from central ECU 30 (aux ECU) to actuator 20 to provide operation mechanisms in a vehicle (e.g, braking, driving force, steering, lights, etc.). [0008]: processor performs advanced processing of selecting and transmitting data).
PANDEY in view of SAKAMAKI, in view of KAWASHIMA does not teach:
wherein each of the plurality of auxiliary electronic control units includes… a data storage unit configured to store a data exchanged with the SoC
However, Krishnani teaches:
wherein each of the plurality of auxiliary electronic control units includes… a data storage unit configured to store a data exchanged with the SoC (Fig. 1; [0037]: mailboxes to which processor 150 of auxiliary safety unit writes to/read from and from which processor 140 of safety island 110 (shown within SoC 104) writes to/reads from).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine PANDEY, SAKAMAKI, KAWASHIMA, and Krishnani by implementing the mailboxes taught by Krishnani. One of ordinary skill in the art would be motivated to make this modification in order to reduce wire length since wire length increases with the number of ECUs in order to connect the ECUs, causing waveform distortion of signal propagation through the bus (KAWASHIMA: [0006]).
Allowable Subject Matter
Claims 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The elements of Claims 18 and 20 were neither found through a search of prior art nor considered obvious by the Examiner. In particular, the prior art of record does not teach nor suggest, in combination with the remaining limitations and in the context of their claims as a whole:
Claim 18: “wherein each CEM includes: a first signal processing block of the plurality of signal processing blocks including a first input node configured to receive a first input signal, a second input node that is not connected, and a third input node that is not connected; a second signal processing block of the plurality of signal processing blocks including a first input node configured to receive the first input signal, a second input node configured to receive a second detected signal, and a third input node that is not connected; and a third signal processing block of the plurality of signal processing blocks including a first input node configured to receive the first input signal, a second input node configured to receive the second detected signal, and a third input node configured to receive a third detected signal.”
Claim 20: “wherein the second data structure includes: a table key including data regarding a plurality of connected nodes of each signal processing block; a set of a plurality of FCC channel numbers associated to each CEM channel of the respective CEM signal processing block; a set of a number corresponding to a location of a CEM channel in each CEM; a set of a plurality of CEM channel identifications; and a set of a plurality of identifications of a plurality of peripherals of the auxiliary electronic control units.”
The following references were found and considered by the Examiner to be the most-related prior art with regards to the claimed invention of the instant application:
Nisar et al. (US 5673419 A, hereinafter “Nisar”)
SAKAMAKI
Yamada (US 20100256860 A1)
Tanaka (US 20040010322 A1)
Nisar: Col 7, lines 1-9: even output of the parity circuit 310 connects to an input of a three-input XOR gate 320, while the odd output of the parity circuit 310 remains unconnected
SAKAMAKI: As cited above, second table structure interpreted differently depending on CEM / FCCU register. Fig. 3: in CEM register, contains stage numbers as table keys (rows == sub-tables) regarding packet processing chips, a set of board numbers, board number also a location. Fig. 4: second table structure mapped to “reception error” column as sub-tables, including item number as a table key and board number to identify reception chip. However, does not list FCC / channel IDs (implicit in Fig. 1, since only line 82 is used).
Yamada: [0006]: In order to achieve the control, an ECU is configured to communicate with various sensors and actuators. A plurality of ECUs mounted on the same vehicle are electrically and communicably connected to each other via LAN and communication IDs are assigned to the ECUs
Tanaka: [0086]: ID code of each ECU and the ID code assigned to parts to be controlled (various sensors or actuators) may be stored.
Although conceptually similar to the claimed invention of the instant application, Nisar, SAKAMAKI, Yamada, and Tanaka do not teach the limitations listed above. Additional modifications were deemed nonobvious by the Examiner.
Prior Art of Record
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Nisar et al. (US 5673419 A, hereinafter “Nisar”) – see above
Yamada (US 20100256860 A1) – see above
Tanaka (US 20040010322 A1) – see above
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CATHERINE MARIE NGUYEN whose telephone number is (571)272-6160. The examiner can normally be reached M-F 7:30 AM - 4:30 PM ET.
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/C.M.N./Examiner, Art Unit 2114
/ASHISH THOMAS/Supervisory Patent Examiner, Art Unit 2114