DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner Notes
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Specification
The disclosure is objected to because of the following informalities: Paragraph [0001], line 2, -- now US Patent No. 12,131,226 issued on Oct. 29, 2024,-- should be inserted after “Patent Application No. 18/311,746,”. Appropriate correction is required.
Claim Objections
Claim 1 is objected to because of the following informalities: line 9, “a unitary quantum gate” should be changed to --the unitary quantum gate--, it appears this unitary quantum gate is the same unitary quantum gate recited in line 1. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 17 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The recitation such as “obtaining data representing a pre-defined control pulse for the unitary quantum gate,” and “applying the pre-defined control pulse to the one or more qubits to implement the unitary quantum gate” (emphasis added), as recited in the claim, are not described in the application as originally filed. At the time of filing, the data representing a pre-defined control pulse for the unitary quantum gate, which recited in the claim, was not defined as a feature of the present invention. Therefore, the above recitations in the claims are seen as new matter. Applicant is required to cancel the new matter in the reply to this Office action.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-8 are rejected on the ground of nonstatutory double patenting as being unpatentable over Claims 1, 5, 2, 3, 7, 8, 17, 19 and 20 of U.S. Patent No. 11,055,627. Although the claims at issue are not identical, they are not patentably distinct from each other because they can be interpreted to describe substantially identical, very similar claimed limitations, or being obvious which are shown below:
Instant application 18/923,184
U.S. Patent No. 11,055,627
Claim 1: A method for implementing a unitary quantum gate on one or more qubits, the method comprising: defining a universal quantum control cost function, wherein the control cost function comprises a gate fidelity penalty term (see claim 5 of 11,055,627) and a qubit leakage penalty term representing during a time dependent Hamiltonian evolution that realizes the unitary quantum gate;
adjusting parameters of the time dependent Hamiltonian evolution to vary a control cost according to the control cost function such that quantum gate fidelity is increased, and qubit leakage errors are reduced;
generating a control pulse for a unitary quantum gate using the adjusted parameters; and applying the control pulse to the one or more qubits to implement the unitary quantum gate.
Claim 1: A method for implementing a unitary quantum gate on one or more qubits, the method comprising: designing a control pulse for the unitary quantum gate, comprising: defining a universal quantum control cost function, wherein the control cost function comprises a qubit leakage penalty term representing i) coherent qubit leakage, and ii) incoherent qubit leakage across all frequency components during a time dependent Hamiltonian evolution that realizes the unitary quantum gate;
adjusting parameters of the time dependent Hamiltonian evolution to vary a control cost according to the control cost function such that leakage errors are reduced;
generating the control pulse using the adjusted parameters; and applying the control pulse to the one or more qubits to implement the unitary quantum gate.
Claim 5: The method of claim 1, wherein the universal control cost function further comprises a gate fidelity penalty term.
Claims 2-8 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 2, 3, 7, 8, 17, 19 and 20 of U.S. Patent No. 11,055,627, respectively, because they are substantially identical.
Claims 9-16 are rejected on the ground of nonstatutory double patenting as being unpatentable over Claims 1, 2, 3, 7, 8, 17, 19, 20 and 21 of U.S. Patent No. 11,055,627. Although the claims at issue are not identical, they are not patentably distinct from each other because they can be interpreted to describe substantially identical, very similar claimed limitations, or being obvious which are shown below:
Instant application 18/923,184
U.S. Patent No. 11,055,627
Claim 9: An apparatus for implementing a single qubit unitary quantum gate, the apparatus comprising: one or more classical processors; a quantum device in data communication with the one or more classical processors, wherein the quantum device comprises: one or more qubits; one or more control pulse drivelines; one or more couplers, each coupler coupling a corresponding qubit to a control pulse driveline; a control pulse generator configured to generate control pulses on the one or more drivelines;
wherein the apparatus is configured to perform operations comprising: defining a universal quantum control cost function, wherein the control cost function comprises a gate fidelity penalty term and a qubit leakage penalty term representing qubit leakage during a time dependent Hamiltonian evolution that realizes the unitary quantum gate; adjusting parameters of the time dependent Hamiltonian evolution to vary a control cost according to the control cost function such that quantum gate fidelity is increased, and qubit leakage errors are reduced; generating a control pulse for the unitary quantum gate using the adjusted parameters; and applying the control pulse to the one or more qubits to implement the unitary quantum gate (see claim 1 of 11,055,627).
Claim 21: An apparatus for implementing a single qubit unitary quantum gate, the apparatus comprising: one or more classical processors; a quantum device in data communication with the one or more classical processors, wherein the quantum device comprises: one or more qubits; one or more control pulse drivelines; one or more couplers, each coupler coupling a corresponding qubit to a control pulse driveline; a control pulse generator configured to generate control pulses on the one or more drivelines; wherein the apparatus is configured to perform the method of claim 1.
Claim 1: A method for implementing a unitary quantum gate on one or more qubits, the method comprising: designing a control pulse for the unitary quantum gate, comprising: defining a universal quantum control cost function, wherein the control cost function comprises a qubit leakage penalty term representing i) coherent qubit leakage, and ii) incoherent qubit leakage across all frequency components during a time dependent Hamiltonian evolution that realizes the unitary quantum gate;
adjusting parameters of the time dependent Hamiltonian evolution to vary a control cost according to the control cost function such that leakage errors are reduced; generating the control pulse using the adjusted parameters; and applying the control pulse to the one or more qubits to implement the unitary quantum gate.
Claims 10-16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 2, 3, 7, 8, 17, 19 and 20 of U.S. Patent No. 11,055,627, respectively, because they are substantially identical.
Claim 17 is rejected on the ground of nonstatutory double patenting as being unpatentable over Claim 1 of U.S. Patent No. 12,131,226. Although the claims at issue are not identical, they are not patentably distinct from each other because they can be interpreted to describe substantially identical, very similar claimed limitations, or being obvious which are shown below:
Instant application 18/923,184
U.S. Patent No. 12,131,226
Claim 17: A method for implementing a unitary quantum gate on one or more qubits, the method comprising: obtaining data representing a pre-defined control pulse for the unitary quantum gate, wherein the pre-defined control pulse: is dependent on a universal quantum control cost function that comprises a gate fidelity penalty term and a qubit leakage penalty term that represents qubit leakage during a time dependent Hamiltonian evolution that realizes the unitary quantum gate; and comprises adjusted values of parameters of the time dependent Hamiltonian evolution that produce a control cost of the universal quantum control cost function with increased quantum gate fidelity and reduced leakage errors; and applying the pre-defined control pulse to the one or more qubits to implement the unitary quantum gate.
Claim 1: A method for implementing a unitary quantum gate on one or more qubits, the method comprising: obtaining, by quantum hardware and from a classical processor, data specifying a control pulse for the unitary quantum gate, wherein the control pulse: is dependent on a universal quantum control cost function that comprises a qubit leakage penalty term that represents qubit leakage during a time dependent Hamiltonian evolution that realizes the unitary quantum gate; and comprises adjusted values of parameters of the time dependent Hamiltonian evolution that produce a control cost of the universal quantum control cost function with reduced leakage errors; and applying, by the quantum hardware, the control pulse to the one or more qubits to implement the unitary quantum gate.
Claims 1-8 are rejected on the ground of nonstatutory double patenting as being unpatentable over Claims 1-3 and 5-9 of U.S. Patent No. 11,657,315. Although the claims at issue are not identical, they are not patentably distinct from each other because they can be interpreted to describe substantially identical, very similar claimed limitations, or being obvious which are shown below:
Instant application 18/923,184
U.S. Patent No. 11,657,315
Claim 1: A method for implementing a unitary quantum gate on one or more qubits, the method comprising: defining a universal quantum control cost function, wherein the control cost function comprises a gate fidelity penalty term (see claim 3 of 11,657,315) and a qubit leakage penalty term representing during a time dependent Hamiltonian evolution that realizes the unitary quantum gate; adjusting parameters of the time dependent Hamiltonian evolution to vary a control cost according to the control cost function such that quantum gate fidelity is increased, and qubit leakage errors are reduced;
generating a control pulse for a unitary quantum gate using the adjusted parameters; and applying the control pulse to the one or more qubits to implement the unitary quantum gate.
Claim 3: The method of claim 1, wherein the universal control cost function further comprises a total runtime penalty term (see claim 1 of 11,657,315).
Claim 1: A method for implementing a unitary quantum gate on one or more qubits, the method comprising: defining a universal quantum control cost function, wherein the control cost function comprises a total runtime penalty term and a qubit leakage penalty term representing qubit leakage during a time dependent Hamiltonian evolution that realizes the unitary quantum gate; adjusting parameters of the time dependent Hamiltonian evolution to vary a control cost according to the control cost function such that total quantum gate runtime and qubit leakage errors are reduced; generating a control pulse for the unitary quantum gate using the adjusted parameters; and applying the control pulse to the one or more qubits to implement the unitary quantum gate.
Claim 3: The method of claim 1, wherein the universal control cost function further comprises a gate fidelity penalty term.
Claims 2, 4, 5, 6, 7 and 8 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 2, 5, 6, 7, 8 and 9 of U.S. Patent No. 11,657,315, respectively, because they are substantially identical.
Claims 9-16 are rejected on the ground of nonstatutory double patenting as being unpatentable over Claims 10-12 and 14-18 of U.S. Patent No. 11,657,315. Although the claims at issue are not identical, they are not patentably distinct from each other because they can be interpreted to describe substantially identical, very similar claimed limitations, or being obvious which are shown below:
Instant application 18/923,184
U.S. Patent No. 11,657,315
Claim 9: An apparatus for implementing a single qubit unitary quantum gate, the apparatus comprising: one or more classical processors; a quantum device in data communication with the one or more classical processors, wherein the quantum device comprises: one or more qubits; one or more control pulse drivelines; one or more couplers, each coupler coupling a corresponding qubit to a control pulse driveline; a control pulse generator configured to generate control pulses on the one or more drivelines; wherein the apparatus is configured to perform operations comprising: defining a universal quantum control cost function, wherein the control cost function comprises a gate fidelity penalty term (see claim 12 of 11,657,315) and a qubit leakage penalty term representing qubit leakage during a time dependent Hamiltonian evolution that realizes the unitary quantum gate; adjusting parameters of the time dependent Hamiltonian evolution to vary a control cost according to the control cost function such that quantum gate fidelity is increased, and qubit leakage errors are reduced; generating a control pulse for the unitary quantum gate using the adjusted parameters; and applying the control pulse to the one or more qubits to implement the unitary quantum gate.
Claim 11: The apparatus of claim 9, wherein the universal control cost function further comprises a total runtime penalty term (see claim 10 of 11,657,315).
Claim 10: An apparatus for implementing a single qubit unitary quantum gate, the apparatus comprising: one or more classical processors; a quantum device in data communication with the one or more classical processors, wherein the quantum device comprises: one or more qubits; one or more control pulse drivelines; one or more couplers, each coupler coupling a corresponding qubit to a control pulse driveline; a control pulse generator configured to generate control pulses on the one or more drivelines; wherein the apparatus is configured to perform operations comprising: defining a universal quantum control cost function, wherein the control cost function comprises a total runtime penalty term and a qubit leakage penalty term representing qubit leakage during a time dependent Hamiltonian evolution that realizes the unitary quantum gate; adjusting parameters of the time dependent Hamiltonian evolution to vary a control cost according to the control cost function such that total quantum gate runtime and qubit leakage errors are reduced; generating a control pulse for the unitary quantum gate using the adjusted parameters; and applying the control pulse to the one or more qubits to implement the unitary quantum gate.
Claim 12: The apparatus of claim 10, wherein the universal control cost function further comprises a gate fidelity penalty term.
Claims 10, 12, 13, 14, 15 and 16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 11, 14, 15, 16, 17 and 18 of U.S. Patent No. 11,657,315, respectively, because they are substantially identical.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAI L NGUYEN whose telephone number is 571-272-1747. The examiner can normally be reached on Monday-Friday from 09:00am to 06:00pm Eastern time.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch can be reached on 571-270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and
https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HAI L NGUYEN/Primary Examiner, Art Unit 2843 March 23, 2026