DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The Information Disclosure Statements filed on 31 December 2024 and 11 June 2025 have been considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-6 of U.S. Patent No. 12,141,473 contains every element of claims 2, 3, 5, 7, and 12-21 of the instant application and as such anticipates claims 2, 3, 5, 7, and 12-21 of the instant application.
Claim Correspondence
Instant Application
U.S. Patent No. 12,141,473
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“A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896, 225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obviousness-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). “ ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 2-5, 7, and 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tawada et al. (Pub. No. US 2005/0015648).
Claim 2:
Tawada et al. disclose a memory system, comprising:
one or more memory devices [fig. 1; pars. 0022-0023 – “The HDD 10 is roughly composed of a head disk assembly unit (hereinafter referred to as an HDA unit) 11 and a printed circuit board unit (hereinafter referred to as a PCB unit) 12.”]; and
processing circuitry coupled with the one or more memory devices [fig. 1; par. 0027 – “The PCB unit 12 includes a read/write IC (read/write channel) 121, a CPU 122, a flash ROM 123, a CPU-RAM 124, a disk controller (hereinafter referred to as an HDC) 125, a buffer RAM 126, a gate array 127, and a CPU bus 128. These elements 121 to 128 are mounted on a printed circuit board (PCB; not shown). The CPU 122, the flash ROM 123, the CPU-RAM 124, the HDC 125, and the gate array 127 are interconnected by the CPU bus 128.”], the processing circuitry configured to cause the memory system to:
receive a first read command that comprises a first indicator value associated with partial execution of the first read command, the first indicator value indicating a first subset of operations to suppress of a sequence of operations associated with the first read command [fig. 1; pars. 0033-0034, 0058 – A read command having a time limit Ttl is received via the host interface. The read operation is suppressed according to the Ttl value if it is predicted that it will take longer than the time limit to execute the read operation (“The HDC 125 is also connected to the host 20 via a host interface 30.” … “The HDC 125 receives commands (read/write commands and the like) transferred by the host 20 and controls the data transfer between the host 20 and the HDC 125.” … “Thus, in the present embodiment, it is predicted beforehand whether a read command with a time limit can be executed in the HDD 10 within the time limit Ttl.” … “Then, if the read command requests a read operation exceeding the basic ability of the HDD 10, the HDD 10 transfers dummy data to the host 20 instead of executing this command.”)];
perform the first read command in accordance with the first indicator value, wherein performing the first read command comprises suppressing the first subset of operations [fig. 6; par. 0038, 0058 – An entry for the command is placed in the command queue (operation performed). The read operation is suppressed if it is predicted that it will take longer than the time limit to execute the read operation (operation suppressed). (“The commands received by the HDC 125 are queued by the HDC 125 in the order of the reception in a queue buffer provided in the buffer RAM 126. The CPU 122 dequeues and executes the commands in the queue buffer, one by one in the order of reception.” … “Then, if the read command requests a read operation exceeding the basic ability of the HDD 10, the HDD 10 transfers dummy data to the host 20 instead of executing this command.”)];
receive a second read command that comprises a second indicator value associated with partial execution of the second read command, the second indicator value indicating a second subset of operations to suppress of the sequence of operations associated with the second read command [fig. 1; pars. 0033-0034, 0058 – Another read command having a time limit Ttl may be received via the host interface. The read operation is suppressed according to the Ttl value if it is predicted that it will take longer than the time limit to execute the read operation (“The HDC 125 is also connected to the host 20 via a host interface 30.” … “The HDC 125 receives commands (read/write commands and the like) transferred by the host 20 and controls the data transfer between the host 20 and the HDC 125.” … “Thus, in the present embodiment, it is predicted beforehand whether a read command with a time limit can be executed in the HDD 10 within the time limit Ttl.” … “Then, if the read command requests a read operation exceeding the basic ability of the HDD 10, the HDD 10 transfers dummy data to the host 20 instead of executing this command.”)]; and
perform the second read command in accordance with the second indicator value, wherein performing the second read command comprises suppressing the second subset of operations [fig. 6; par. 0038, 0058 – Another command may be received. An entry for the command is placed in the command queue (operation performed). The read operation is suppressed if it is predicted that it will take longer than the time limit to execute the read operation (operation suppressed). (“The commands received by the HDC 125 are queued by the HDC 125 in the order of the reception in a queue buffer provided in the buffer RAM 126. The CPU 122 dequeues and executes the commands in the queue buffer, one by one in the order of reception.” … “Then, if the read command requests a read operation exceeding the basic ability of the HDD 10, the HDD 10 transfers dummy data to the host 20 instead of executing this command.”)].
Claim 3 (as applied to claim 2 above):
Tawada et al. disclose, wherein the processing circuitry is further configured to:
output a first response indicating completion of the first read command in response to suppressing the first subset of operations [fig. 6; par. 0058 – Dummy data is returned to the host. (“Then, if the read command requests a read operation exceeding the basic ability of the HDD 10, the HDD 10 transfers dummy data to the host 20 instead of executing this command.”)]; and
output a second response indicating completion of the second read command in response to suppressing the second subset of operations [fig. 6; par. 0058 – Dummy data is returned to the host for another command. (“Then, if the read command requests a read operation exceeding the basic ability of the HDD 10, the HDD 10 transfers dummy data to the host 20 instead of executing this command.”)].
Claim 4 (as applied to claim 3 above):
Tawada et al. disclose,
wherein a duration between receiving the first read command and outputting the first response is indicative of one or more timing errors associated with the memory system [fig. 1; pars. 0033-0034, 0058 – Receiving the response may be indicative of a timing error regarding the Ttl value. (“The HDC 125 is also connected to the host 20 via a host interface 30.” … “The HDC 125 receives commands (read/write commands and the like) transferred by the host 20 and controls the data transfer between the host 20 and the HDC 125.” … “Thus, in the present embodiment, it is predicted beforehand whether a read command with a time limit can be executed in the HDD 10 within the time limit Ttl.” … “Then, if the read command requests a read operation exceeding the basic ability of the HDD 10, the HDD 10 transfers dummy data to the host 20 instead of executing this command.”)].
Claim 5 (as applied to claim 2 above):
Tawada et al. disclose,
wherein performance of the first read command, performance of the second read command, or both are indicative of one or more performance metrics of the memory system in accordance with suppressing the first subset of operations, suppressing the second subset of operations, or both [fig. 1; pars. 0033-0034, 0058 – The performance or suppression of the commands is indicative of the system being able to performs the operations in the allotted time. (“The HDC 125 is also connected to the host 20 via a host interface 30.” … “The HDC 125 receives commands (read/write commands and the like) transferred by the host 20 and controls the data transfer between the host 20 and the HDC 125.” … “Thus, in the present embodiment, it is predicted beforehand whether a read command with a time limit can be executed in the HDD 10 within the time limit Ttl.” … “Then, if the read command requests a read operation exceeding the basic ability of the HDD 10, the HDD 10 transfers dummy data to the host 20 instead of executing this command.”)].
Claim 7 (as applied to claim 2 above):
Tawada et al. disclose,
wherein the first indicator value indicates to suppress one or more first operations performed by the processing circuitry and one or more second operations performed by a storage controller of the memory system, and wherein the second indicator value indicates to suppress one or more third operations performed by the storage controller [fig. 1; pars. 0033-0034, 0058 – Read commands having a time limit Ttl is received via the host interface. The read operation is suppressed according to the Ttl value if it is predicted that it will take longer than the time limit to execute the read operation (“The HDC 125 is also connected to the host 20 via a host interface 30.” … “The HDC 125 receives commands (read/write commands and the like) transferred by the host 20 and controls the data transfer between the host 20 and the HDC 125.” … “Thus, in the present embodiment, it is predicted beforehand whether a read command with a time limit can be executed in the HDD 10 within the time limit Ttl.” … “Then, if the read command requests a read operation exceeding the basic ability of the HDD 10, the HDD 10 transfers dummy data to the host 20 instead of executing this command.”)].
Claim 11 (as applied to claim 2 above):
Tawada et al. disclose,
wherein the first indicator value, the second indicator value, or both are received in accordance with a command protocol or via a subset of pins from a plurality of pins [fig. 1; pars. 0033-0034, 0058 – Read commands having a time limit Ttl is received via the host interface. The read command is in accordance with the command protocol. (“The HDC 125 is also connected to the host 20 via a host interface 30.” … “The HDC 125 receives commands (read/write commands and the like) transferred by the host 20 and controls the data transfer between the host 20 and the HDC 125.” … “Thus, in the present embodiment, it is predicted beforehand whether a read command with a time limit can be executed in the HDD 10 within the time limit Ttl.” … “Then, if the read command requests a read operation exceeding the basic ability of the HDD 10, the HDD 10 transfers dummy data to the host 20 instead of executing this command.”)].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tawada et al. (Pub. No. US 2005/0015648) as applied to claim 2 above, and further in view of Cho et al. (Pub. No. US 2021/0034514).
Claim 10 (as applied to claim 2 above):
Tawada et al. disclose all the limitations above but do not specifically disclose,
wherein the first read command, the second read command, or both comprises a Universal Flash Storage protocol information unit, and wherein the first indicator value, the second indicator value, or both are included in one or more fields of the Universal Flash Storage protocol information unit.
In the same field of endeavor, Cho et al. disclose,
wherein the first read command, the second read command, or both comprises a Universal Flash Storage protocol information unit, and wherein the first indicator value, the second indicator value, or both are included in one or more fields of the Universal Flash Storage protocol information unit [pars. 0194 – “For example, the CMD UPIU defined by the UFS interface may have the packet format illustrated in FIG. 14A. For example, the CMD UPIU may include the following fields: Trans Type, Flags, Logical Unit Number (LUN), Task Tag, Initiation Device Identifier/Command Set Type (IID/CST), Error History Source (EHS) Length, Data Segment Length, Expected Data Transfer Length, Command Descriptor Block (CDB), Header, Reserved, etc.”].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Tawada et al. to include a UFS storage device, as taught by Tawada et al., in order to improve performance by providing a high speed flash memory storage device.
Allowable Subject Matter
Claims 6, 8, and 9 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art does not disclose the limitations of the listed claims in conjunction with the limitations of the base claim and intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ogawa (U.S. Patent No. 7,587,552) discloses, “A computer system comprising: a host computer; a first storage system that processes an I/O request issued from the host computer; and a second storage system that receives host I/O information and performance information from the first storage system and reproduces, based on the host I/O information and performance information, the internal processing conditions of the first storage system at the time the I/O request was processed, thereby simulating I/O performance of the first storage system, wherein the second storage system changes the settings for tuning parameters into various settings while reproducing internal processing conditions of the first storage system at the time the I/O request was processed, thereby testing whether any improvement has been made in the performance.” [claim 1]
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LARRY T MACKALL whose telephone number is (571)270-1172. The examiner can normally be reached Monday - Friday, 9am-5pm.
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LARRY T. MACKALL
Primary Examiner
Art Unit 2131
10 January 2026
/LARRY T MACKALL/Primary Examiner, Art Unit 2139