Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 6-8, 11, 14-15, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Breen et al., US Patent Appl. Pub. No. 2011/0051479 in view of Buterbaugh et al., US Patent Appl. Pub. No. 2010/0102790.
Regarding claim 1, Breen discloses an electronic device (FIG(s) 1-3), comprising:
a processor (FIG. 2, 230, FIG. 3, 320, paragraph 0021, lines 12-13, paragraph 0023, lines 7-10);
a first power circuit (FIG. 3, 330A) coupled to the processor and including a first set of power transistors (FIG, 1, power stage 115, Q1, Q2), the first power circuit to provide power to the processor (FIG. 3, 315);
a second power circuit (FIG. 3, 330B) coupled to the processor and including a second set of power transistors (FIG, 1, power stage 115, Q1, Q2), the second power circuit to provide power to the processor (FIG. 3, 315); and
a voltage regulator controller (FIG. 2, 210, FIG. 3, 320) coupled to the processor and to the first and second power circuits (FIG(s) 2 and 3), the voltage regulator controller to:
receive a current usage prediction from the processor (FIG. 2, paragraph 0022, lines 1-4, lines 6-8); and
drive the first and second power circuits to provide power to the processor in accordance with the current usage prediction (paragraph 0022, lines 8-11).
Breen does not specifically state measuring first current and second current drawn from respective first power circuit and second power circuit by the processor, the voltage regulator controller receiving the measurements of first and second currents drawn by the processor from the first and second power circuits, determine that the first power circuit is sufficient to provide the first and second currents drawn, and cease driving the second power circuit and continue driving the first power circuit to provide power to the processor based on the first and second currents drawn.
Buterbaugh teaches a voltage regulator (FIG. 1, 100) including plurality of phase modules (i.e. first and second power circuits – FIG. 1, 104, 106), each including its own current sensing module (FIG. 1, 110, 112) for sensing/measuring the output current drawn from each phase module during operation of the processor (FIG. 1, 156) and communicating the sensed current values to a service processor (voltage regulator controller – FIG. 1, 130), which in turn dynamically disables/enables different number of phase modules in the voltage regulator according to the power requirements derived from the current measurements (paragraph 0020, lines 12-17, paragraph 0021, lines 1-7, lines 11-12, paragraph 0022). Buterbaugh further teaches disabling one or more phases (i.e. ceasing driving the second power circuit) while continuing operation with the remaining phase(s) based on reduced currents drawn by the phase modules (i.e. determine that the first power circuit is sufficient to provide the first and second currents drawn, and cease driving the second power circuit and continue driving the first power circuit to provide power to the processor based on the first and second currents drawn – paragraph 0024, lines 1-8, paragraph 0025, lines 9-13, lines 24-30). Accordingly, the regulated power from the voltage regulator delivered to electrical components is optimized, thus, efficient power delivery is achieved (paragraph 0005, lines 1-7, paragraph 0006, lines 1-3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the above described voltage regulator and functionality, as suggested by Buterbaugh with the device disclosed by Breen in order to implement measuring first current and second current drawn from respective first power circuit and second power circuit by the processor, the voltage regulator controller receiving the measurements of first and second currents drawn by the processor from the first and second power circuits, determine that the first power circuit is sufficient to provide the first and second currents drawn, and cease driving the second power circuit and continue driving the first power circuit to provide power to the processor based on the first and second currents drawn.
One of ordinary skill in the art would be motivated to do so in order to achieve efficient power delivery.
Regarding claims 7 and 14, The combination of Breen with Buterbaugh discloses a device and method including all claim limitations, as addressed above for claim 1.
Regarding claims 2, 8, and 15, Breen further discloses the device and method, wherein the voltage regulator controller is to adjust power outputs of the first and second power circuits (controlling the power output of phase(s) by disabling/enabling respective phase(s)) in response to a temperature measurement received from the first power circuit (paragraph 0034, lines 1-8, lines 10-13, FIG. 6, 625, 630-YES, 635, paragraph 0036, lines 1-8).
Regarding claims 6, 11, and 18, Buterbaugh further teaches the device and method, wherein determining that the first power circuit is sufficient to provide the first and second currents drawn comprises comparing a current supply capability of the first power circuit with the first and second currents drawn (comparison between the currents drawn by the first and second phase modules with the current ratings of each phase to determine whether the selected active first phase(s) can deliver sufficient current after disabling other phase(s) – paragraph 0018, paragraph 0025, lines 9-13, lines 24-30).
Claim(s) 5, 12-13, and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Breen et al., US Patent Appl. Pub. No. 2011/0051479 in view of Buterbaugh et al., US Patent Appl. Pub. No. 2010/0102790, and further in view of “Stuck in the middle – mean vs. median” (referred hereafter as NPL1).
Regarding claims 5, 12-13, and 19-20 Breen and Buterbaugh disclose the device and method, as per claims 1, 7, and 14, respectively.
With respect to claims 5, 12, and 19, Breen and Buterbaugh do not specifically state the measurement of the first current drawn is a median of multiple measurements of current drawn by the processor from the first power circuit.
With respect to claims 13 and 20 Breen and Buterbaugh do not specifically state the measurement of the first current drawn is a mean of multiple measurements of current drawn by the processor from the first power circuit.
NPL1 teaches utilizing both mean and medium functions to derive representative values for a plurality of measurements (NPL1, Example section). NPL1 further teaches utilizing the mean for calculating the standard deviation (and other statistical testing procedures), which is the most prominent measure to assess the variability in a set of data (NPL1, Mean vs. median: PROs and CONs section). NPL1 further teaches utilizing the median to counteract the effect of false measurements in the data set (NPL1, Mean vs. median: PROs and CONs section).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the above described mean and median functions, as described by NPL1 with the device and method disclosed by Breen and Buterbaugh in order to implement he measurement of the first current drawn is a median of multiple measurements of current drawn by the processor from the first power circuit and the measurement of the first current drawn is a mean of multiple measurements of current drawn by the processor from the first power circuit. One of ordinary skill in the art would be motivated to do so in order to statistically assess the variability in the set of current measurements and/or counteract the effect of false current measurements in the set of current measurements.
Allowable Subject Matter
Claims 3-4, 9-10, and 16-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEFAN STOYNOV whose telephone number is (571)272-4236. The examiner can normally be reached 8AM - 4:30PM.
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/STEFAN STOYNOV/ Primary Examiner, Art Unit 2175
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