Prosecution Insights
Last updated: July 17, 2026
Application No. 18/923,301

INTEGRATED SOLID-STATE RELAY

Non-Final OA §103§112
Filed
Oct 22, 2024
Priority
Feb 05, 2024 — provisional 63/549,663
Examiner
PERENY, TYLER J
Art Unit
Tech Center
Assignee
Integense Microelectronics Inc.
OA Round
1 (Non-Final)
95%
Grant Probability
Favorable
1-2
OA Rounds
3m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 95% — above average
95%
Career Allowance Rate
161 granted / 170 resolved
+34.7% vs TC avg
Moderate +6% lift
Without
With
+6.2%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
27 currently pending
Career history
197
Total Applications
across all art units

Statute-Specific Performance

§103
80.3%
+40.3% vs TC avg
§102
1.4%
-38.6% vs TC avg
§112
18.4%
-21.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 170 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 2-3, 6-7, 12-13, 16-17, & 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claims 2 & 6 recite the limitation "the electronic device" in line 2. There is insufficient antecedent basis for this limitation in the claims. For examination purposes, examiner has interpreted “the electronic device” to read “the transistor die”. By virtue of their dependency on claims 2 & 6, claims 3 & 7 are also rejected. Claim 12 & 16 recite the limitation "the electronic device" in line 2. There is insufficient antecedent basis for this limitation in the claims. For examination purposes, examiner has interpreted “the electronic device” to read “the switch die”. By virtue of their dependency on claims 12 & 16, claims 13 & 17 are also rejected. Claim 20 recites the limitation "the solid-state relay device" in line 1. There is insufficient antecedent basis for this limitation in the claims. For examination purposes, examiner has interpreted “the solid-state relay device” to read “the relay device”. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 4, 11, 14, & 20 are rejected under 35 U.S.C. 103 as being unpatentable over Pigott et al. (US 2015/0004902 A1), hereinafter Pigott, in view of Kerber et al. (US 2011/0176339 A1), hereinafter Kerber. Regarding claim 1, Pigott discloses, in figures 3 & 7, a solid-state relay device comprising: a transmitter die (Para [0066], “first communication circuitry 714 includes transmitter circuitry”…included in the first IC die 710 [IC die 330 of FIG. 3]) including a pair of input terminals (bond pads 750) coupled to a pair of transmitter output terminals (720, 722); and a receiver die (Para [0066], “second communication circuitry 734 includes receiver circuitry”…included in the second IC die 730 [IC die 310 of FIG. 3]) including a pair of receiver input terminals (terminals from secondary coil 732 to 734), a pair of output terminals (Para [0064], “other ones of first and second bond pads 750, 752 may be used to receive input signals, convey output signals”) and a coupler region (dielectric structure 740), wherein the transmitter die is attached to a top surface of the receiver die (FIG. 3 depicts the first transmitter die 330 attached to a top surface of the receiver die 310), wherein the coupler region includes: a transmit coil connected to the pair of receiver input terminals (transmit coil 712 connected to the terminals to 734); a receiver coil positioned proximate the transmit coil and connected to the pair of output terminals (receiver coil 732 proximate the transmit coil 712 and connected to 720, 722); receiver circuitry (734); and a shield layer positioned between the receiver circuitry and the receiver coil (Para [0065], “the dielectric structure 740 is arranged so that it is present across the entire area of overlap of the coils 712, 732”…positioned between the receiver circuitry 734 and the receiver coil 732), but fails to disclose a transistor die including a transistor having a gate terminal, a source terminal, and a drain terminal; and wherein at least one output terminal of the pair of output terminals is attached to the gate terminal. However, Kerber discloses, in figure 9, a transistor die including a transistor having a gate terminal, a source terminal, and a drain terminal (Para [0053], “switching element 120, such as an MOSFET or an IGBT”…that may included in a separate die than receiver circuit 5 and transmitter circuit 4); and wherein at least one output terminal of the pair of output terminals is attached to the gate terminal (pair of output terminals 51.sub.1, 52.sub.2 of the receiver circuit 5 is attached to the gate terminal of switching element 120 via controller 140). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the transistor of Kerber in the solid-state relay device of Pigott, to achieve the benefit of selectively isolating a portion of the solid-state relay device based on the mode of operation (Pigott, Para [0053]-[0055]). Regarding claim 4, Pigott in view of Kerber disclose the solid-state relay device of claim 1, and Pigott continues to disclose, in figure 1, 3, & 7, wherein the transmitter die is attached to a top surface of the receiver die (FIG. 3 depicts the first transmitter die 330 attached to a top surface of the receiver die 310) and wherein the receiver die is attached to a top surface of the transistor die (Para [0019], “second circuit 120 may include an array of IGBTs”…the bonding pads 752 of the receiver die [210, 310] are connected to the second circuit 120 that is formed on a separate die. An attachment, defined by Merriam-Webster as the connection or joining between two things, is established to a top surface of the transistor die formed by second circuit 120 via bonding pads 752 [352] to a lead 372 corresponding to second circuit 120). Regarding claim 10, Pigott in view of Kerber disclose the solid-state relay device of claim 1, and Pigott continues to disclose, in figure 1, 3, & 7, an encapsulant that at least partially encapsulates the transmitter die and the receiver die (Para [0041], “inductive communication device 300 may include a support structure 370 and encapsulation 380”), but fails to disclose the transistor die partially encapsulated. However, It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the partial encapsulation of the transistor die since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. [i.e., incorporating standard protection techniques for the packaged device] (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415‐421, 82 USPQ2d 1385). Regarding claim 11, Pigott discloses, in figures 3 & 7, a relay device comprising: a transmitter die (Para [0066], “first communication circuitry 714 includes transmitter circuitry”…included in the first IC die 710 [IC die 330 of FIG. 3]) including an input (bond pads 750) coupled to a transmitter output (720, 722); and a receiver die (Para [0066], “second communication circuitry 734 includes receiver circuitry”…included in the second IC die 730 [IC die 310 of FIG. 3]) including a receiver input (terminals from secondary coil 732 to 734), an output (Para [0064], “other ones of first and second bond pads 750, 752 may be used to receive input signals, convey output signals”) and a coupler region (dielectric structure 740), wherein the receiver input is connected to the transmitter output (terminals from secondary coil 732 to 734 connected to 720, 722), wherein the coupler region includes: a transmit coil connected to the receiver input (transmit coil 712 connected to the terminals to 734); a receiver coil connected to the output (receiver coil 732 connected to 720, 722); receiver circuitry (734); and a shield positioned between the receiver circuitry and the receiver coil (Para [0065], “the dielectric structure 740 is arranged so that it is present across the entire area of overlap of the coils 712, 732”…positioned between the receiver circuitry 734 and the receiver coil 732), but fails to disclose a switch die including a solid-state switch having a source, a drain, and a gate; and wherein the output is coupled to the gate. However, Kerber discloses, in figure 9, a switch die including a solid-state switch having a source, a drain, and a gate (Para [0053], “switching element 120, such as an MOSFET or an IGBT”…that may included in a separate die than receiver circuit 5 and transmitter circuit 4); and wherein the output is coupled to the gate (pair of output terminals 51.sub.1, 52.sub.2 of the receiver circuit 5 is attached to the gate terminal of switching element 120 via controller 140). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the transistor of Kerber in the solid-state relay device of Pigott, to achieve the benefit of selectively isolating a portion of the solid-state relay device based on the mode of operation (Pigott, Para [0053]-[0055]). Regarding claim 14, Pigott in view of Kerber disclose the relay device of claim 11, and Pigott continues to disclose, in figure 1, 3, & 7, wherein the transmitter die is attached to a top surface of the receiver die (FIG. 3 depicts the first transmitter die 330 attached to a top surface of the receiver die 310) and wherein the receiver die is attached to a top surface of the switch die (Para [0019], “second circuit 120 may include an array of IGBTs”…the bonding pads 752 of the receiver die [210, 310] are connected to the second circuit 120 that is formed on a separate die. An attachment, defined by Merriam-Webster as the connection or joining between two things, is established to a top surface of the transistor die formed by second circuit 120 via bonding pads 752 [352] to a lead 372 corresponding to second circuit 120). Regarding claim 20, as best understood based on the 35 U.S.C. 112(b) rejection made above, Pigott in view of Kerber disclose the relay device of claim 11, and Pigott continues to disclose, in figure 1, 3, & 7, an encapsulant that at least partially encapsulates the transmitter die and the receiver die (Para [0041], “inductive communication device 300 may include a support structure 370 and encapsulation 380”), but fails to disclose the switch die partially encapsulated. However, It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the partial encapsulation of the switch die since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. [i.e., incorporating standard protection techniques for the packaged device] (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415‐421, 82 USPQ2d 1385). Claims 2-3 & 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Pigott in view of Kerber as applied to claims 1, 4, 11, 14, & 20 above, and further in view of Naoya et al. (JP 2022147622 A), hereinafter Naoya. Regarding claim 2, as best understood based on the 35 U.S.C. 112(b) rejection made above, Pigott in view of Kerber disclose the solid-state relay device of claim 1, and Kerber continues to disclose, in figure 9, wherein the transistor is a first transistor and the source terminal is a first source terminal (Para [0053], “switching element 120, such as an MOSFET or an IGBT”), but fail to disclose wherein the transistor die further comprises a second transistor having a second source terminal, wherein the first source terminal is connected to the second source terminal. However, Naoya discloses, in figure 1 & 4, wherein the transistor die (switch circuit 400 is a semiconductor chip) further comprises a second transistor having a second source terminal (second transistor 402), wherein the first source terminal is connected to the second source terminal (transistor 401 and transistor 402 have a common source connection to node N5). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the transistor structure of Naoya in the transistor die of Pigott and Kerber, to achieve the benefit of selectively operating an output-side device coupled to the output of the receiver (Naoya, pg. 3, paragraph 2). Regarding claim 3, the combination of Pigott, Kerber, and Naoya disclose the solid-state relay device of claim 2, and Naoya continues to disclose, in figure 4, wherein the second transistor includes a second gate terminal connected to the at least one output terminal of the pair of output terminals (second transistor 402 includes a gate terminal connected to the output terminal SC of the receiver 300). Regarding claim 12, as best understood based on the 35 U.S.C. 112(b) rejection made above, Pigott in view of Kerber disclose the relay device of claim 11, and Kerber continues to disclose, in figure 9, wherein the solid-state switch is a first solid-state switch and the source is a first source (Para [0053], “switching element 120, such as an MOSFET or an IGBT”), but fail to disclose wherein the switch die further comprises a second solid-state switch having a second source, wherein the first source is connected to the second source. However, Naoya discloses, in figure 1 & 4, wherein the switch die (switch circuit 400 is a semiconductor chip) further comprises a second solid-state switch having a second source (second transistor 402), wherein the first source is connected to the second source (transistor 401 and transistor 402 have a common source connection to node N5). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the transistor structure of Naoya in the switch die of Pigott and Kerber, to achieve the benefit of selectively operating an output-side device coupled to the output of the receiver (Naoya, pg. 3, paragraph 2). Regarding claim 13, the combination of Pigott, Kerber, and Naoya disclose the relay device of claim 12, and Naoya continues to disclose, in figure 4, wherein the second solid-state switch includes a second gate coupled to the output (second transistor 402 includes a gate terminal connected to the output terminal SC of the receiver 300). Claims 9 & 19 are rejected under 35 U.S.C. 103 as being unpatentable over Pigott in view of Kerber as applied to claims 1, 4, 11, 14, & 20 above, and further in view of Fabbro et al. (US 2023/0101061 A1), hereinafter Fabbro. Regarding claim 9, Pigott in view of Kerber disclose the solid-state relay device of claim 1, but fail to disclose an energy storage device coupled to the gate terminal and arranged to apply power to the gate terminal in response to an input signal at the input terminals. However, Fabbro discloses, in figure 2 & 3, an energy storage device coupled to the gate terminal (capacitors of voltage conversion device 322 [210] coupled to the gate of transistor 326) and arranged to apply power to the gate terminal in response to an input signal at the input terminals (Para [0038], “voltage conversion device 210 may be configured to convert the energy transferred by the energy transfer device 206 from the input voltage associated with the input source 204 to an output voltage capable of controlling, such as turning on, the switch 212”). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the energy storage of Fabbro in the solid-state relay device of Pigott and Kerber, to achieve the benefit of driving the gate of the transistor in differing modes of operation (Fabbro, Para [0038]). Regarding claim 19, Pigott in view of Kerber disclose the relay device of claim 11, but fail to disclose an energy storage device coupled to the gate and arranged to apply power to the gate in response to an input signal at the input. However, Fabbro discloses, in figure 2 & 3, an energy storage device coupled to the gate (capacitors of voltage conversion device 322 [210] coupled to the gate of transistor 326) and arranged to apply power to the gate in response to an input signal at the input (Para [0038], “voltage conversion device 210 may be configured to convert the energy transferred by the energy transfer device 206 from the input voltage associated with the input source 204 to an output voltage capable of controlling, such as turning on, the switch 212”). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the energy storage of Fabbro in the solid-state relay device of Pigott and Kerber, to achieve the benefit of driving the gate of the transistor in differing modes of operation (Fabbro, Para [0038]). Allowable Subject Matter Claims 5, 8, 15, & 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 6-7 & 16-17 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Brauchler et al. (US 10,992,346 B2) [Figure 1. Discloses an embodiment of a transformer-based system or galvanic isolation device includes a first coil, a second coil aligned with the first coil across a gap, and a first capacitor coupled between the first coil and a first voltage reference. A first electrode of the first capacitor may be formed from a conductive electrode structure that is electrically isolated from the first coil, and a second electrode of the first capacitor may be formed from at least a portion of the first coil. The system or device also may include a second capacitor coupled between the second coil and a second voltage reference. The first and second coils may form portions of first and second IC die, respectively, and the system or device may also include one or more dielectric components within the gap between the IC die, where the dielectric component(s) are positioned directly between the first and second coils.] Sonntag et al. (US 2016/0352328 A1) [Figure 4A. Discloses an oscillator supplying a clock signal having a frequency determined in part according to a received current. A transmit side charge pump is coupled to the clock signal and boosts a voltage supplied to the charge pump to generate a boosted voltage. A driver circuit drives a transmit signal having a frequency based on the clock signal and a voltage based on the boosted voltage to a capacitive isolation communication path. A receive side charge pump is coupled to the isolation capacitors of the isolation communication path and boosts a voltage of the received signal on the receive side of the isolation communication path and supplies a gate signal with the boosted voltage to a gate of at least one transistor.] Any inquiry concerning this communication or earlier communications from the examiner should be directed to TYLER J PERENY whose telephone number is (571)272-4189. The examiner can normally be reached M-F 7:30-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Taelor Kim can be reached at (571) 270-7166. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TYLER J PERENY/ Examiner, Art Unit 2836
Read full office action

Prosecution Timeline

Oct 22, 2024
Application Filed
Jul 06, 2026
Non-Final Rejection mailed — §103, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
95%
Grant Probability
99%
With Interview (+6.2%)
2y 0m (~3m remaining)
Median Time to Grant
Low
PTA Risk
Based on 170 resolved cases by this examiner. Grant probability derived from career allowance rate.

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