DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event a determination of the status of the application as subject to AIA 35 U.S.C. 102, 103, and 112 (or as subject to pre-AIA 35 U.S.C. 102, 103, and 112) is incorrect, any correction of the statutory basis for a rejection will not be considered a new ground of rejection if the prior art relied upon and/or the rationale supporting the rejection, would be the same under either status.
Notice of Claim Interpretation
Claims in this application are not interpreted under 35 U.S.C. 112(f) unless otherwise noted in an office action.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 16 April 2026 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 4, 8, and 16 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claims 4, 8, and 16 include the phrase “in response to the determination”. It is unclear whether this is intended to refer to the determinations in claims 1 and 13 or the determinations in claims 4, 8, and 16.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4, 5, 9, 11-14, 16, 17, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Blake et al. (US 2004/0230750) in view of Iyengar et al. (US 2020/0272521).
In regards to claims 1, 13, and 20, Blake teaches a system, comprising:
one or more memories collectively containing one or more programs (“In a tightly coupled system there is a shared memory model wherein programs or applications can be run on any processor or node in the system.”, paragraph 0004);
one or more processors, wherein the one or more processors are configured to, individually or collectively, perform an operation (“In a tightly coupled system there is a shared memory model wherein programs or applications can be run on any processor or node in the system.”, paragraph 0004) comprising:
receiving, by a first node of a plurality of nodes, a memory access request from a requesting device, the memory access request comprising a target address for data stored in a memory system (“Once the incoming remote storage access arrives, it is processed by being sent through the processing pipeline 15. As part of this processing step, portions of the address are applied to the cache directory 14”, paragraph 0049; );
determining, by checking a tracking table maintained at the first node, that data corresponding to the target address is stored in a remote memory, wherein the remote memory belongs to a second node of the plurality of nodes and comprises one or more memory modules, and the tracking table comprises address information across the memory system of the first node (“If the cache directory and memory configuration table determine that the data is resident in the local memory 12 (via a memory configuration table 19) but not in the local cache 13 (via cache directory 14), then the RAT bit from memory coherent directory 16 is used to determine whether the address must be broadcast to the other nodes in the SMP complex.”, paragraph 0053; “RAT bits are set only when a remote storage access comes in to the storage region owning node from another node, and obtains data that will be cached in another node.”, paragraph 0048; "These components are illustrated again in FIG. 3, which illustrates in greater detail some of the components contained within one node. In addition to local memory 12, local cache 13, cache directory 14, pipeline 15, and memory coherent directory 16, this figure also illustrates an optional memory configuration table 19, and interconnections between these elements.", paragraph 0033; "Each node shall have a number of elements to form an autonomous computing unit, including typically one or more processors 11, a local memory 12 (accessible by all nodes), a local cache 13 (also accessible by all nodes), and a cache directory 14.", paragraph 0031);
in response to the determination, initiating a search in the remote memory to identify a memory module that comprises the data corresponding to the target address, wherein the search in the remote memory is performed prior to completing a search in a local memory (“If the RAT bit is on, then the address must be broadcast to the other nodes to search the caches on the other nodes for the latest version of data (which in the exemplary embodiment may exist in a changed state on these other nodes) before accessing the local memory.”, paragraph 0054);
receiving the data corresponding to the target address from the identified memory module in the remote memory (“The result of this search may be that the data is returned from cache on a remote node”, paragraph 0054); and
updating the tracking table with an entry corresponding to the target address (“RAT bits are set only when a remote storage access comes in to the storage region owning node from another node, and obtains data that will be cached in another node.”, paragraph 0048; “an additional request 21 is routed through the processing pipeline 15 to set the RAT bit in the memory coherent directory 16 corresponding to the referenced region of storage”, paragraph 0050).
Blake fails to teach that the nodes are drawers, wherein the memory system is a distributed memory system, the distributed memory system comprising a plurality of drawers, each drawer comprising a respective memory;
wherein the remote memory belongs to one of the plurality of drawers, and the address information is across the plurality of drawers within the distributed memory system.
Iyengar teaches that the nodes are drawers, wherein the memory system is a distributed memory system, the distributed memory system comprising a plurality of drawers, each drawer comprising a respective memory (“FIG. 1 depicts a distributed symmetric multiprocessing (SMP) system 100 (hereafter ‘system 100’) in accordance with one or more embodiments. System 100 can include 4 processing units or ‘drawers.’”, paragraph 0031; “Although FIG. 2 depicts only drawer 102, it should be appreciated that a similar configuration is contemplated for drawers 104, 106, and 108, and/or other drawers in system 100. … Each respective CP chip may be connected to system memory (e.g., system memory 212, system memory 214, system memory 216, and system memory 218).”, paragraph 0033; See also figure 2);
wherein the remote memory belongs to one of the plurality of drawers (“FIG. 1 depicts a distributed symmetric multiprocessing (SMP) system 100 (hereafter ‘system 100’) in accordance with one or more embodiments. System 100 can include 4 processing units or ‘drawers.’”, paragraph 0031; “Although FIG. 2 depicts only drawer 102, it should be appreciated that a similar configuration is contemplated for drawers 104, 106, and 108, and/or other drawers in system 100. … Each respective CP chip may be connected to system memory (e.g., system memory 212, system memory 214, system memory 216, and system memory 218).”, paragraph 0033; See also figure 2), and the address information is across the plurality of drawers within the distributed memory system (“Intra-drawer coherency communication may be performed using pass-through and a combination of these bus-lines, 118.”, paragraph 0031)
in order to scale the system to a larger number of processors (paragraph 0002).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Blake with Iyengar such that the nodes are drawers, wherein the memory system is a distributed memory system, the distributed memory system comprising a plurality of drawers, each drawer comprising a respective memory;
wherein the remote memory belongs to one of the plurality of drawers, and the address information is across the plurality of drawers within the distributed memory system
in order to scale the system to a larger number of processors (id.).
In regards to claims 2 and 14, Blake further teaches that the operation further comprises:
buffering the data fetched from the remote memory (“the data will be returned to and cached in another node”, paragraph 0050); and
sending the data to the requesting device (“the data will be returned to and cached in another node”, paragraph 0050).
In regards to claims 4 and 16, Blake further teaches that the operation further comprises:
receiving, by the first node of the plurality of nodes, a second memory access request from a second requesting device, the second memory access request comprising a second target address (“Once the incoming remote storage access arrives, it is processed by being sent through the processing pipeline 15. As part of this processing step, portions of the address are applied to the cache directory 14”, paragraph 0049);
determining, by checking the tracking table maintained at the first node, that data corresponding to the second target address is stored in the local memory of the first node, wherein the local memory comprises one or more memory modules (“If the RAT bit is off, this indicates that no part of this region of memory has ever been cached by any other node, this allows the data to be obtained immediately from the local memory 12 with no search of any other node.”, paragraph 0053);
in response to the determination, initiating a search in the local memory to identify a memory module that comprises the data corresponding to the second target address (“If the RAT bit is off, this indicates that no part of this region of memory has ever been cached by any other node, this allows the data to be obtained immediately from the local memory 12 with no search of any other node.”, paragraph 0053);
receiving the data corresponding to the second target address from the identified memory module in the local memory (“If the RAT bit is off, this indicates that no part of this region of memory has ever been cached by any other node, this allows the data to be obtained immediately from the local memory 12 with no search of any other node.”, paragraph 0053);
updating the tracking table with an entry corresponding to the second target address (“RAT bits are set only when a remote storage access comes in to the storage region owning node from another node, and obtains data that will be cached in another node.”, paragraph 0048; “an additional request 21 is routed through the processing pipeline 15 to set the RAT bit in the memory coherent directory 16 corresponding to the referenced region of storage”, paragraph 0050); and
sending the data corresponding to the second target address to the second requesting device (“The data will be returned from wherever the most recent copy is found, which could be a remote cache, or the local memory of this node.”, paragraph 0059).
Iyengar further teaches the first node is the first drawer of the plurality of drawers (“FIG. 1 depicts a distributed symmetric multiprocessing (SMP) system 100 (hereafter ‘system 100’) in accordance with one or more embodiments. System 100 can include 4 processing units or ‘drawers.’”, paragraph 0031; “Although FIG. 2 depicts only drawer 102, it should be appreciated that a similar configuration is contemplated for drawers 104, 106, and 108, and/or other drawers in system 100. … Each respective CP chip may be connected to system memory (e.g., system memory 212, system memory 214, system memory 216, and system memory 218).”, paragraph 0033; See also figure 2).
In regards to claims 5 and 17, Blake further teaches that determining that the data corresponding to the target address is stored in the remote memory comprises:
identifying an entry corresponding to the target address exists in the tracking table (“The fourth line of TABLE 1 indicates that if the requested data is not found in the local cache, and if the Memory Configuration Table indicates that the target address is assigned to memory on another node, that the address must be broadcast to remote nodes regardless of the setting of the RAT bit (in some applications, the Memory Coherent Directory may not even have an entry for addresses that are assigned to memory on remote nodes, so a RAT bit may not even be available).”, paragraph 0060); and
determining that the data corresponding to the target address is stored in the remote memory based on the entry (“The fourth line of TABLE 1 indicates that if the requested data is not found in the local cache, and if the Memory Configuration Table indicates that the target address is assigned to memory on another node, that the address must be broadcast to remote nodes regardless of the setting of the RAT bit (in some applications, the Memory Coherent Directory may not even have an entry for addresses that are assigned to memory on remote nodes, so a RAT bit may not even be available).”, paragraph 0060).
In regards to claim 9, Blake further teaches that the memory access request comprises a write operation (“In addition, to the above methods and means for limiting or controlling memory coherency traffic on the communication links between or within the nodes, hardware facilities are provided on the node that owns the data to allow it to be updated from another node without the RAT bit being set, which will also limit the memory coherency traffic.”, paragraph 0064), the method further comprising:
receiving new data from the requesting device (“In addition, to the above methods and means for limiting or controlling memory coherency traffic on the communication links between or within the nodes, hardware facilities are provided on the node that owns the data to allow it to be updated from another node without the RAT bit being set, which will also limit the memory coherency traffic.”, paragraph 0064); and
send the new data to the local memory or the remote memory based on the target address (“In addition, to the above methods and means for limiting or controlling memory coherency traffic on the communication links between or within the nodes, hardware facilities are provided on the node that owns the data to allow it to be updated from another node without the RAT bit being set, which will also limit the memory coherency traffic.”, paragraph 0064).
In regards to claims 11 and 19, Blake further teaches that the tracking table comprises one or more parameters, and wherein the one or more parameters are selected from the group consisting of input/output domain identifier, address range, page size, local access indicator, remote access indicator (“RAT bits are set only when a remote storage access comes in to the storage region owning node from another node, and obtains data that will be cached in another node.”, paragraph 0048), static allocation indicator, dynamic allocation indicator, and target drawer identifier.
In regards to claim 12, Blake further teaches that the tracking table is constructed using predefined address mappings (“Memory coherent directory 16 contains "Remote Access Tag" (RAT) bits associated with each storage increment, one bit per configurable block size or storage region, that record whether data anywhere within the local memory storage region has been accessed and cached by any other node.”, paragraph 0043) and updated by tracking one or more memory access requests processed by a memory management unit (“RAT bits are set only when a remote storage access comes in to the storage region owning node from another node, and obtains data that will be cached in another node.”, paragraph 0048).
Claims 3, 10, 15, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Blake et al. (US 2004/0230750) in view of Iyengar et al. (US 2020/0272521) and Intel (“SCC External Architecture Specification (EAS)”).
In regards to claims 3 and 15, Blake in view of Iyengar teaches claims 1 and 13. Blake in view of Iyengar fails to teach that receiving the data corresponding to the target address from the identified memory module in the remote memory comprises receiving the data in increments via an interconnect, each increment having a defined size, wherein the defined size is a fraction of a total block size of the data. Intel teaches that receiving the data corresponding to the target address from the identified memory module in the remote memory comprises receiving the data in increments via an interconnect, each increment having a defined size, wherein the defined size is a fraction of a total block size of the data (“Figures 10, 11, 12, and 13 show the format of the flit structures used on the mesh. … Packetization into flits is handled in the interface driver provided with the Management Console software.”, page 42; See also figure 13). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Blake with Iyengar and Intel such that receiving the data corresponding to the target address from the identified memory module in the remote memory comprises receiving the data in increments via an interconnect, each increment having a defined size, wherein the defined size is a fraction of a total block size of the data in order to reduce buffering requirements.
In regards to claims 10 and 18, Blake in view of Iyengar teaches claims 1 and 13. Blake in view of Iyengar fails to teach detecting an error during the process of receiving the data corresponding to the target address from the identified memory module in the remote memory; and
initiating an error handling process, comprising at least one of:
retrying to fetch the data from the remote memory;
reporting the error to the requesting device; or
including the error into a diagnostic log.
Intel teaches detecting an error during the process of receiving the data corresponding to the target address from the identified memory module in the remote memory (“Error checking is done end-to-end, primarily through parity bits on mesh packets. Parity checks on packets are done on the following fields: route field, commands, and data. Parity generation is done at the mesh interface (MIF) by the MIU.”, page 24); and
initiating an error handling process (“Error signals are sent to agents if a parity error is detected.”, page 24), comprising at least one of:
retrying to fetch the data from the remote memory (“In such cases, a retry mechanism is used by the agents.”, page 24);
reporting the error to the requesting device (“Error signals are sent to agents if a parity error is detected.”, page 24); or
including the error into a diagnostic log.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Blake with Iyengar and Intel to include detecting an error during the process of receiving the data corresponding to the target address from the identified memory module in the remote memory; and
initiating an error handling process, comprising at least one of:
retrying to fetch the data from the remote memory;
reporting the error to the requesting device; or
including the error into a diagnostic log
in order to reduce data corruption.
Claims 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Blake et al. (US 2004/0230750) in view of Iyengar et al. (US 2020/0272521) and Safranek et al. (US 2004/0003184).
In regards to claim 6, Blake further teaches receiving, by the first node of the plurality of nodes, a second memory access request from a second requesting device, the second memory access request comprising a second target address (“Once the incoming remote storage access arrives, it is processed by being sent through the processing pipeline 15. As part of this processing step, portions of the address are applied to the cache directory 14”, paragraph 0049).
Blake in view of Iyengar fails to teach confirming, by checking the tracking table maintained at the first drawer, that there is no entry corresponding to the second target address in the tracking table; and
in response to the confirmation, initiating a search in the local memory of the first drawer, wherein the local memory comprises one or more memory modules.
Safranek teaches confirming, by checking the tracking table maintained at the first node, that there is no entry corresponding to the second target address in the tracking table (“If a remote node accesses a local cache line where it misses in snoop filter 64, a cacheable access (read with snoop) is issued by coherency controller switch 60 to the local node.”, paragraph 0034); and
in response to the confirmation, initiating a search in the local memory of the first node, wherein the local memory comprises one or more memory modules (“In the cacheable access, there is a snoop of the local processor bus and a memory read to the memory of that node.”, paragraph 0034).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Blake with Iyengar and Safranek to include confirming, by checking the tracking table maintained at the firs drawer, that there is no entry corresponding to the second target address in the tracking table; and
in response to the confirmation, initiating a search in the local memory of the first drawer, wherein the local memory comprises one or more memory modules
in order to reduce storage space.
In regards to claim 7, Blake further teaches determining that a memory module in the local memory comprises data corresponding to the second target address (“If the RAT bit is off, this indicates that no part of this region of memory has ever been cached by any other node, this allows the data to be obtained immediately from the local memory 12 with no search of any other node.”, paragraph 0053);
receiving the data corresponding to the second target address from the identified memory module in the local memory (“If the RAT bit is off, this indicates that no part of this region of memory has ever been cached by any other node, this allows the data to be obtained immediately from the local memory 12 with no search of any other node.”, paragraph 0053);
updating the tracking table maintained at the first node with an entry corresponding to the second target address (“RAT bits are set only when a remote storage access comes in to the storage region owning node from another node, and obtains data that will be cached in another node.”, paragraph 0048; “an additional request 21 is routed through the processing pipeline 15 to set the RAT bit in the memory coherent directory 16 corresponding to the referenced region of storage”, paragraph 0050); and
sending the data corresponding to the second target address to the second requesting device (“The data will be returned from wherever the most recent copy is found, which could be a remote cache, or the local memory of this node.”, paragraph 0059).
In regards to claim 8, Blake further teaches determining that no memory module in the local memory comprises data corresponding to the second target address (“The fourth line of TABLE 1 indicates that if the requested data is not found in the local cache, and if the Memory Configuration Table indicates that the target address is assigned to memory on another node”, paragraph 0060);
in response to the determination, initiating a remote search in the remote memory (“the address must be broadcast to remote nodes”, paragraph 0060);
identifying that a memory module in the remote memory comprises the data corresponding to the second target address (“In this case, data will be returned from a remote cache or from remote memory.”, paragraph 0060);
receiving the data corresponding to the second target address from the identified memory module in the remote memory (“In this case, data will be returned from a remote cache or from remote memory.”, paragraph 0060);
updating the tracking table maintained at the first node with an entry corresponding to the second target address (“RAT bits are set only when a remote storage access comes in to the storage region owning node from another node, and obtains data that will be cached in another node.”, paragraph 0048); and
sending the data corresponding to the second target address to the second requesting device (“The result of this search may be that the data is returned from cache on a remote node”, paragraph 0054).
Response to Arguments
Applicant's arguments filed 16 April 2026 have been fully considered but they are not persuasive.
The Examiner disagrees that Blake’s memory coherency directory 16 does not teach a tracking table comprising address information across the plurality of nodes. Blake teaches that the memory coherency directory 16 does include address information (“Also, a portion of the address is applied to memory coherent directory 16.”, paragraph 0052). Blake’s memory coherency directory 16 does track across the plurality of nodes (“If the RAT bit is off, this indicates that no part of this region of memory has ever been cached by any other node”, paragraph 0053; “If the RAT bit is on, then the address must be broadcast to the other nodes to search the caches on the other nodes for the latest version of data (which in the exemplary embodiment may exist in a changed state on these other nodes)”, paragraph 0054). Blake does teach the pre-search step (“If the RAT bit is on, then the address must be broadcast to the other nodes to search the caches on the other nodes for the latest version of data (which in the exemplary embodiment may exist in a changed state on these other nodes) before accessing the local memory.”, paragraph 0054), since the memory coherency directory 16 is accessed to determine the RAT bit before accessing the local memory.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN SADLER whose telephone number is (571)270-7699. The examiner can normally be reached Monday - Friday 8am - 5pm.
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/Nathan Sadler/Primary Examiner, Art Unit 2139 29 June 2026
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