Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US20190086730) in view of Kavalieros et al (US20190080731) further in view of Duranton (US2003015975).
Regarding Claim 1. Huang teaches A circuitry for adjusting image data to-be rendered on a display device (Huang, abstract, the invention describes a driving apparatus which comprises a first substrate including: a storage unit electrically connected to a display module, the storage unit saving display parameters of the display module, wherein the display parameters include a gamma correction code, a common electrode voltage setting code, and an uneven brightness distribution compensation module code; and a second substrate including: a control module electrically coupled to the storage unit, for reading the display parameters saved in the storage unit and adjusting driving parameters for the display module, wherein the display module electrically is coupled to the first substrate through a serial peripheral interface, and an integrated circuit bus electrically is coupled to a timing control unit and a programmable gamma correction buffer circuit unit.), comprising:
Huang fails to explicitly teach, however, Kavalieros teaches a non-volatile memory, comprising a plurality of memory cells (Kavalieros, abstract, the invention describes methods for providing data to be used in an in-memory computation at a memory device. In an embodiment a memory device comprises a first memory array and circuitry, coupled to the first memory array, to perform a data computation based on data stored at the first memory array. Prior to the computation , the first memory array receives the data from a second memory array of the memory device . The second memory array extends horizon tally in parallel with, but is offset vertically from, the first memory array. In another embodiment, a single integrated circuit die includes both the first memory array and the second memory array.
[0015] Embodiments discussed herein variously provide techniques and mechanisms for providing data to be used in an in-memory computation at a memory device. As used herein in the context of "in-memory computing," "in memory compute operation," "in-memory data computation" and related phrases, the term "in-memory" refers to the characteristic of an action being performed locally at a memory device which includes both a memory array and interface logic by which the memory device is to couple to, and communicate with, some memory controller, processor or other external agent.
[0016] For example, a memory device may include a first array of memory cells
(or "memory array") and circuitry, coupled thereto, which is operable to detect a logic state based on one or more bits currently stored by the first array. Such circuitry may
perform one or more data computations based on the logic state).
Huang teaches method of adjusting display brightness evenness by using display controller with embedded memory. Kavalieros teaches method in an in-memory computation at a memory device. Therefore, it would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention, to modify the display brightness evenness method (taught in Huang), to further implement in-memory computation by using coupled circuitry and memory array with plurality of memory cells (taught in Kavalieros), so as to improve the speed and/or energy efficiency of data provisioning (Kavalieros, [0002, 0018]).
The combination of Huang and Kavalieros further teaches a non-volatile memory array having a plurality of memory cells configured to store luminance correction data of the display device (Huang, [0032] FIG. 4 illustrates a display device according to one embodiment of the present invention. FIG. 5 illustrates a communication architecture according to one embodiment of the present invention. Please refer to FIGS. 4 and 5, in one embodiment of the present invention, a driving apparatus 11 of a display device comprises: a display module 160; a first substrate 50 including: a storage unit 110 electrically connected to the display module 160, the storage unit 110 saving display parameters of the display module 160, wherein the display parameters include a gamma correction code 112, a common electrode voltage setting code 114, and an uneven brightness distribution compensation module code 116; a second substrate 60 including: a control module (not shown) electrically coupled to the storage unit 110.);
The combination of Huang and Kavalieros fails to explicitly teach, however, Duranton teaches geometry correction data of the display device (Duranton, abstract, the invention describes a device 11 for correcting geometrical faults of a cathode ray tube 10. This device comprises means 111 for adjusting spatial digital factors, these spatial digital factors controlling a digital circuit 112 for spatially processing images displayed on the screen 10. These adjusting means are controlled by control signals 16 which may be generated by a user by means of a remote control unit 12 and a control interface 113. The correction may also be automatic when the faults are due to certain characteristics of the image to be displayed, such as brilliance. In this case, measuring means 110 evaluate the brilliance of the image and generate a control signal 17 as a function of this brilliance.
[0027] FIG. 3 illustrates a correction of an image size fault. An image 21 displayed on a screen 20 of the cathode ray tube 10 does not occupy the whole screen 20 because of geometrical faults of the cathode ray tube 10. The zoom factors are stored in a memory of the digital circuit 112 in the form of words of 16 bits, 12 of which correspond to a fractional decimal part of the zoom factor. … When the digital circuit 112 receives the control signal, an adder adds the vertical zoom zV to this increment. A result of this addition is then stored in the register of the digital circuit 112, which applies this new vertical zoom factor zV to the image displayed on the cathode ray tube 10. The user touches this key several times until the size of the image 21 corresponds to the size of the screen 20. There is also a key with which the height of the image 21 can be reduced, as well as keys for increasing or decreasing the width of the image 21. In this example, the adjusting means 111 correspond to a set of circuits allowing, on the basis of the control signal, a modification of the vertical zoom factor zV. The adjusting means 111 particularly comprise an adder, a subtracter and means for writing a result in a register of the digital circuit 112.
[0029] The zoom factors may also be used for automatic correction of faults related to characteristics of the image 21, for example, brilliance.).
Huang, Kavalieros and Duranton are analogous art because they all teach method of correcting display brightness evenness. Duranton further teaches an integrated circuitry for correcting geometric distortions. Therefore, it would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention, to modify the display brightness evenness method with embedded memory (taught in Huang and Kavalieros), to further use the saved zoom factor for fixing geometrical faults (taught in Duranton), so as to automatically fix the geometrical distortion (Duranton, [0008]).
The combination of Huang, Kavalieros and Duranton further teaches a luminance adjusting circuit configured to receive the luminance correction data from the non-volatile memory and adjust the image data based on the luminance correction data (Huang, [0032], as shown in Fig 4 & 5, a second substrate 60 including: a control module (not shown) electrically coupled to the storage unit 110, the control module for reading the display parameters saved in the storage unit 110 and
adjusting driving parameters for the display module 160; wherein the display module 160 is electrically coupled to the first substrate 50 through a serial peripheral interface
150; and an integrated circuit bus 140 electrically is coupled to timing control unit 120 and a programmable gamma correction buffer circuit unit 130 separately.
[0038], refers to FIG. 5, in one embodiment of the present invention, in a production line, a present driving method for a display device is provided. At first, a
common electrode voltage is adjusted to an optimal voltage value for each display
panel. The above-mentioned common electrode voltage setting code 114 is saved in
the storage unit 110. And, processes of gamma correction and mura compensation are performed to form a gamma correction code 112 and an uneven brightness distribution compensation module code 116. Then, the gamma correction code 112 and the uneven brightness distribution compensation module code 116 are saved in the storage unit 110, wherein different codes are saved in different addresses so that the timing control unit 120 can read them correctly. Therefore, each panel can have their own matching information (codes or parameters), so that it is unnecessary to provide an extra control board for each panel.); and
a geometry adjusting circuit configured to receive the geometry correction data from the non-volatile memory and perform spatial manipulation of pixels in the image data based on the geometry correction data (Duranton, [0027] FIG. 3 illustrates a correction of an image size fault. An image 21 displayed on a screen 20 of the cathode ray tube 10 does not occupy the whole screen 20 because of geometrical faults of the cathode ray tube 10. The zoom factors are stored in a memory of the digital circuit 112 in the form of words of 16 bits, 12 of which correspond to a fractional decimal part of the zoom factor. … When the digital circuit 112 receives the control signal, an adder adds the vertical zoom zV to this increment. A result of this addition is then stored in the register of the digital circuit 112, which applies this new vertical zoom factor zV to the image displayed on the cathode ray tube 10. The user touches this key several times until the size of the image 21 corresponds to the size of the screen 20. There is also a key with which the height of the image 21 can be reduced, as well as keys for increasing or decreasing the width of the image 21. In this example, the adjusting means 111 correspond to a set of circuits allowing, on the basis of the control signal, a modification of the vertical zoom factor zV. The adjusting means 111 particularly comprise an adder, a subtracter and means for writing a result in a register of the digital circuit 112.).
Regarding Claim 4. The combination of Huang, Kavalieros and Duranton further teaches The circuitry of claim 1, wherein the non-volatile memory array further comprises a serial data interface coupled to the luminance adjusting circuit and the geometry adjusting circuit (Huang, [0032], as shown in Fig 4 & 5, a second substrate 60 including: a control module (not shown) electrically coupled to the storage unit 110, the control module for reading the display parameters saved in the storage unit 110 and adjusting driving parameters for the display module 160; wherein the display module 160 is electrically coupled to the first substrate 50 through a serial peripheral interface 150; and an integrated circuit bus 140 electrically is coupled to timing control unit 120 and a programmable gamma correction buffer circuit unit 130 separately.).
Regarding Claim 5. The combination of Huang, Kavalieros and Duranton further teaches The circuitry of claim 1, wherein the non-volatile memory array further comprises a parallel data interface coupled to the luminance adjusting circuit and the geometry adjusting circuit (Kavalieros, abstract, the invention describes methods for providing data to be used in an in-memory computation at a memory device. In an embodiment a memory device comprises a first memory array and circuitry, coupled to the first memory array, to perform a data computation based on data stored at the first memory array. Prior to the computation, the first memory array receives the data from a second memory array of the memory device. The second memory array extends horizon tally in parallel with, but is offset vertically from, the first memory array. In another embodiment, a single integrated circuit die includes both the first memory array and the second memory array.).
The reasoning for combination of Huang, Kavalieros and Duranton is the same as described in Claim 1.
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US20190086730) in view of Kavalieros et al (US20190080731), Duranton (US2003015975) further in view of Cho et al (US20180048914).
Regarding Claim 2. The combination of Huang, Kavalieros and Duranton fails to explicitly teach, however, Cho teaches The circuitry of claim 1, wherein the plurality of memory cells in the non-volatile memory are further configured to store sub-pixel rendering correction data (Cho, abstract, the invention describes an image processing method includes performing subpixel rendering operation on a first image data to generate a second image data; and encoding the second image data to generate a third image data which has a size smaller than a size of the second image data.
[0049] To sum up, in the image processing unit according to embodiments of the present invention, the image enhancement and subpixel rendering operation are performed before the compression encoding/decoding and buffering storage operations. Therefore, the subpixel rendering unit efficiently reduces the size of image data to be stored in the frame buffer. As a result, the frame buffer size may be reduced by performing subpixel rendering operation earlier than the encoding process, and the physical size and cost of the apparatus using the image processing unit or the image processing method according to embodiments of the present invention may be reduced.).
Huang, Kavalieros, Duranton and Cho are analogous art because they all teach method of correcting display image. Cho further teaches a correction circuitry based on subpixel data. Therefore, it would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention, to modify the display brightness evenness method with embedded memory (taught in Huang, Kavalieros and Duranton), to further use the saved subpixel data to render display image (taught in Cho), so as to provide an efficient image compression method (Cho, [0006]).
Regarding Claim 3. The combination of Huang, Kavalieros, Duranton and Cho further teaches The circuitry of claim 2, further comprising: a sub-pixel rendering circuit configured to increase an apparent resolution of the image data by adjusting each sub-pixel individually based on the sub-pixel rendering correction data (Cho, [0026] More details of subpixel rendering operation are described as follows. The subpixel rendering unit 210 implements the subpixel rendering (SPR) technology, which renders pixel data based on the physical subpixel arrangement of the display panel 112 to increase the visual display resolution. For example, FIG. 3 is a schematic diagram of pixels of a full-color (or called true-color) display panel of RGB stripe type. Each pixel (e.g., a pixel p_ll) includes three subpixels (e.g., the red subpixel r_ll, the green subpixel g_ll and the blue subpixel b_ll). However, subpixels of the display panel 112 in FIG.1 or FIG. 2 may be arranged in different patterns or subpixel geometry. FIG. 4 is a schematic diagram of pixels of the display panel 112 of an exemplary subpixel arrangement according to an example of the present disclosure.).
Claims 6 are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US20190086730) in view of Kavalieros et al (US20190080731), Duranton (US2003015975) further in view of Seiler (US20210049981).
Regarding Claim 6. The combination of Huang, Kavalieros and Duranton fails to explicitly teach, however, Seiler teaches The circuitry of claim 1, wherein the luminance correction data comprises pixel-wise brightness and color correction data (Seiler, abstract, the invention relates to artificial reality, such as virtual reality and augmented reality. In one embodiment, a computing system may access a first rendered frame generated at a first frame rate based on a first viewing direction of a user. The system may generate, based on the first rendered frame, subframes at a second frame rate higher than the first frame rate. The system may generate a first subframe by determining a second viewing direction of the user based on sensor data, determining, based on the second viewing direction, at least a first viewing region encompassing a foveal focus point of the user and a second viewing region excluding the first viewing region, determining, for the first subframe, color values corresponding to the first viewing region using a first sampling resolution and color values corresponding to the second viewing region using a second sampling resolution lower than the first sampling resolution. The system may output subframes for display at the second frame rate.
[0079] In particular embodiments, the display block 215 may receive pixel color values from the pixel block 214, covert the format of the data to be more suitable for the scanline output of the display, apply one or more brightness corrections to the pixel color values, and prepare the pixel color values for output to the display. In particular embodiments, the display block 215 may each include a row buffer and may process and store the pixel data received from the pixel block 214.).
Huang, Kavalieros, Duranton and Seiler are analogous art because they all teach method of correcting display image. Seiler further teaches color and brightness correction at pixel level. Therefore, it would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention, to modify the display brightness evenness method with embedded memory (taught in Huang, Kavalieros and Duranton), to further use the pixel color and brightness data to render display image (taught in Seiler), so as to provide image display on the foveal region of the user to reduce the power consumption and computational resources usage of the rendering process (Seiler, [0002-0003]).
Claims 11 are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US20190086730) in view of Kavalieros et al (US20190080731), Duranton (US2003015975) further in view of Osmanis et al (US20220311984).
Regarding Claim 11. The combination of Huang, Kavalieros and Duranton fails to explicitly teach, however, Osmanis teaches The circuitry of claim 1, wherein the geometry correction data further comprises pixel-wise correction data for varifocal display and multi-focal display (Osmanis, abstract, the invention describes a system for rendering three-dimensional image content for a multi-focal display device. The system includes a first processing sub-system configured to divide the three-dimensional image content into a plurality of virtual depth planes, associate each of the plurality of virtual depth planes with one of a first set of displays and a second set of displays of the multi-focal display device, and generate a first array including the plurality of virtual depth planes. The system also includes a transmission sub-system configured to provide a data channel for transmission of the generated first array. The system further includes a second processing sub-system configured to receive the generated first array and to render the three-dimensional image content in the multi-focal display device based thereon.
[0069] In particular, the compressed graphical data stream may be decompressed by a dedicated hardware decoder/encoder, which can be a part of the second processing sub-system or a separate unit communicably coupled to the second processing sub-system. As the graphical data are decompressed, they are buffered within the random-access memory of the processing unit which is accessible by the dedicated graphics processing unit. The dedicated graphics processing unit optionally can perform a calculation (data manipulation) on the received graphical data. The calculation or data manipulation may include any one of or a combination of: data reformatting, "boundary-pixel" removal, geometrical transformation (pixel shift, perspective correction, image stretching/compression and similar), image pixel arrangement reformatting (pixel scrambling).).
Huang, Kavalieros, Duranton and Osmanis are analogous art because they all teach method of display brightness/geometry correction. Osmanis further teaches geometry correction for multi-focal and/or varifocal display. Therefore, it would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention, to modify the display brightness evenness method with embedded memory (taught in Huang, Kavalieros and Duranton), to further apply to multi-focal and/or varifocal display (taught in Osmanis), so as to properly render 3D image content without distortion (Osmanis, [0003-0008]).
Claims 12 are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US20190086730) in view of Kavalieros et al (US20190080731), Duranton (US2003015975) further in view of Wiki ("Phase change memory", 2018).
Regarding Claim 12. The combination of Huang, Kavalieros and Duranton fails to explicitly teach, however, Wiki teaches The circuitry of claim 1, wherein the non-volatile memory array includes one of a resistive random-access memory, a phase-change random access memory, a ferroelectric random-access memory, or a spin-transfer torque magnetic random-access memory (Wiki, page 1, par 1, Phase change memory (also known as PCM, PCME, PRAM, PCRAM, OUM (ovonic unified memory) and C-RAM or CRAM (chalcogenide RAM)) is a type of non-volatile random access memory. PRAMs exploit the unique behaviour of chalcogenide glass.
Page 3, par 2, PRAM can offer much higher performance in applications where writing quickly is important, both because the memory element can be switched more quickly, and also because single bits may be changed to either 1 or O without needing to
first erase an entire block of cells. PRAM's high performance, thousands of times faster
than conventional hard drives, makes it particularly interesting in nonvolatile memory
Kavalieros, [0039] Memory device 110 may include any of a variety of types of
memory technology wherein memory cells are arranged in rows and columns-e.g., where data stored by said cells is accessible via word lines and bit lines, or an equivalent thereof. In one embodiment, memory device 110 includes static random access memory (or "SRAM"). However, any of various additional or alternative types of memory cell technologies may be adapted.).
The combination of Huang, Kavalieros and Duranton teaches method of adjusting display brightness evenness by using display controller with embedded ontime programmable memory storing error correction data. Wiki teaches a fast performance memory Phase-change random access memory. Therefore, it would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention, to modify the display brightness evenness method with embedded memory (taught in Huang, Kavalieros and Duranton), to further use the phase-change random access memory (taught in Wiki) for storing pixel brightness data, so as to achieve higher performance (Wiki, page 3, par 2).
Claims 13 are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US20190086730) in view of Kavalieros et al (US20190080731), Duranton (US2003015975) further in view of Takeda et al (WO2015141730).
Regarding Claim 13. The combination of Huang, Kavalieros and Duranton fails to explicitly teach, however, Takeda teaches The circuitry of claim 1, wherein the non-volatile memory array includes a redundant memory section configured to correct an error of the luminance data (Takeda, abstract, the invention describes methods of providing a cache memory and an error correction circuit capable of reducing overhead caused by an error correction process. The cache memory comprises a cache memory section accessible on a per cache line basis; and a
redundant code storage section that stores a first redundant code for correcting errors in
each unit of cache line data stored, on a per cache line basis, in the cache memory
section and a second redundant code for correcting errors in a portion of the data in
each unit of cache line data.
[0018-0023] FIG. 3 is a block diagram of a processor system 2 in which the inside of the cache memory 1 of FIG. 1 is more embodied. The processor core 3 has, for example, a multi-core configuration, and has a plurality of cores ·11. An L1 cache 6 is connected to each core 11. Since the L 1 cache 6 is required to have high speed, it is composed of, for example, a SRAM (Static Random Access Memory). The processor core 3 may have a single core configuration. In this case, only one L1 cache 6 is provided. The L2 cache 7 of FIG. 1 has a data cache unit 12, a tag unit 13, a redundant code storage unit 14, a cache controller 15, and an error correction controller 16. The redundant code storage unit 14 stores a first storage unit 14a for storing a first redundant code for error-correcting each cache line data stored in the data cache unit 12, and a part of the data of each cache line data. It has a second storage unit 14b for storing a second redundant code for error correction. The type of the fast redundant code and the second redundant code may be any.).
The combination of Huang, Kavalieros and Duranton teaches method of adjusting
display brightness evenness by using display controller with embedded on-time
programmable memory including plurality of memory cells. Takeda teaches memory
with redundant section for error correction. Therefore, it would have been obvious to a
person with ordinary skill in the art before the effective filing date of the claimed
invention, to modify the display brightness evenness method with embedded on-time
programmable memory including plurality of memory cells (taught in Huang, Kavalieros and Duranton), to further implement extra redundant section for error correction (taught in
Takeda), so as to reduce the overhead of error correction processing (Takeda, [0006-
0007]).
Claims 14-15, 17 are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US20190086730) in view of Kavalieros et al (US20190080731), Duranton (US2003015975) further in view of Thompson et al (US20180350296).
Claim 14 is similar in scope as Claim 1 and thus is rejected using same rationale. Claim 14 further requires:
The combination of Huang, Kavalieros and Duranton fails to explicitly teach, however, Thompson teaches deburn-in circuit configured to receive the deburn-in correction data from the nonvolatile memory array and dynamically adjust pixel output of the image data to compensate for darkening or discoloration (Thompson, abstract, the invention describes a data processing system which stores a long-term history of pixel luminance values in a secure memory and uses those values to create burn-in compensation values. Those values are used to mitigate burn-in effect on a display. The long-term history can be updated over time with new, accumulated pixel luminance values.
[0054] The embodiment shown in FIG. 7D uses one or more sets of regions that can be selectively located in locations that are anticipated to possibly experience high bum-in or show high burn-in effects, such as regions that are anticipated to frequently have high display intensity contrast (between dark pixels and bright pixels).).
Huang, Kavalieros, Duranton and Thompson are analogous art because they all teach method of display brightness/geometry correction. Thompson further teaches using saved burn-in data to compensate the pixel color/luminance value. Therefore, it would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention, to modify the display brightness evenness method with embedded memory (taught in Huang, Kavalieros and Duranton), to further use saved burn-in data to compensate the pixel color/luminance value (taught in Thompson), so as to provide even brightness for the display degrading overtime (Thompson, [0002-0003]).
Regarding Claim 15. The combination of Huang, Kavalieros, Duranton and Thompson further teaches The circuitry of claim 14, wherein the deburn-in correction data comprises estimated pixel lifetimes generated based on analysis of appearance and usage patterns of the display device (Thompson, [0054] The embodiment shown in FIG. 7D uses one or more sets of regions that can be selectively located in locations that are anticipated to possibly experience high bum-in or show high burn-in effects, such as regions that are anticipated to frequently have high display intensity contrast (between dark pixels and bright pixels). For example, a region of a user interface that is often used by users and contains a high display intensity contrast can be a target for a set of selectively located regions in which TBIM values are generated and collected (and provided to a developer for use as described herein). Certain applications are used more frequently than other applications by users, and the higher usage of those applications will tend to have a higher chance of causing bum-in effects, particularly in regions of the user interface where there is a high display intensity contrast such as a dark line that separates regions of the U1, and bright pixels are immediately next to the dark line. By placing these selectively located regions in such areas, information about burn-in and about the mitigation of burn-in can be captured and used by, for example, a developer of hardware or software used in the device that includes the display. In the example shown in FIG. 7D, the display 755 has been logically separated into three regions that each contain a set of selectively located regions.).
The reasoning for combination of Huang, Kavalieros, Duranton and Thompson is the same as described in Claim 14.
Regarding Claim 17. The combination of Huang, Kavalieros, Duranton and Thompson further teaches The circuitry of claim 14, wherein the deburn-in circuit is further configured to: apply stress to underused pixels during idle periods of the display device by increasing a current or maintaining the pixels in an active state for a prolonged duration to accelerate aging of the underused pixels (Thompson, [0036], … The burn in compensation values can be based on a model about pixel aging for different luminance levels over the lifetime of a pixel, optionally for different operating temperature levels over the lifetime of the pixels and optionally for both continuous pixel drive and for pulse width modulation drive. The model can be derived from data obtained from testing of displays in a development lab. The displays can be stress tested with different luminance levels and different temperature levels and with either continuous drive or pulse width modulation drive over time. The stress testing can be accelerated aging tests, and measurements taken over time during this stress testing produce measured luminance levels that are output from the pixels and show the effect of aging, such as reduced luminance output from the pixels. The data from these stress tests can be used to generate one or more models about pixel aging, and then compensation values can be calculated (using techniques known in the art) and stored (for example, in a table) for different levels of aging.).
The reasoning for combination of Huang, Kavalieros, Duranton and Thompson is the same as described in Claim 14.
Claims 16 are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Kavalieros et al, Duranton, Thompson et al further in view of Bi et al (US20140375704).
Regarding Claim 16. The combination of Huang, Kavalieros, Duranton and Thompson fails to explicitly teach, however, Bi teaches The circuitry of claim 14, wherein to dynamically adjust pixel output of the image data, the deburn-in circuit is further configured to: modify a drive voltage and/or current supplied to each pixel, wherein the modification is performed to restore intended luminance and color balance of each pixel (Bi, abstract, the invention describes display driver circuitry in the display analyzing the data to detect static data. The image data may contain static frames of data or static portions of a frame of data. In response to detection of static data, the display driver circuitry can take actions to avoid display damage due to bum-in effects. The display driver circuitry may reduce a peak luminance value associated with a peak luminance control algorithm, may reduce display brightness, may map image data to reduced brightness levels, or may take other actions to ensure that display pixels in the display are not damaged. Temperature information may be used in determining how to classify information as static data and in determining how significantly to reduce display pixel drive currents in response to the detection of static image data.
[0117] The value of VREGOUT2 may be used in producing the voltages on path 214. For example, VREGOUT2 may be used in producing voltage V255 (as an example). If desired, optional circuitry such as resistor ladder 256 may be used in adjusting VREGOUT2 to compensate for manufacturing variations. As shown in FIG.17, resistor ladder 256 has a chain of resistors that are coupled between terminals 258 and 264. A fixed voltage may be provided to terminal 264. If desired, the fixed voltage provided to terminal 264 and the voltages applied to terminals 236, 234, and 246 may be adjusted using adjustable voltage supply circuits (e.g., to compensate circuitry 66 for variations in display pixel array 52 and other manufacturing variations).).
Huang, Kavalieros, Duranton, Thompson and Bi are analogous art because they all teach method of display brightness/geometry correction. Bi further teaches using changing pixel voltage to compensate the pixel color/luminance value. Therefore, it would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention, to modify the display brightness evenness method with embedded memory (taught in Huang, Kavalieros, Duranton and Thompson), to further change pixel voltage to compensate the pixel color/luminance value (taught in Bi), so as to reduce burn-in effects due to displaying static image content (Bi, [0009]).
Claims 18 are rejected under 35 U.S.C. 103 as being unpatentable over Su et al (US20220059015) in view of Lee et al (KR20190027495).
Regarding Claim 18. Su teaches A circuitry in an electronic device supporting an always-on-display (AOD) mode (Su, abstract, the invention teaches A micro light emitting diode (micro LED) display and a controller thereof are provided. The micro LED display includes a circuit board, a plurality of micro LED devices, and the controller. The micro LED devices are disposed on a first surface of the circuit board. The micro LED devices respectively have a plurality of pixel arrays. The controller is carried by the circuit board and is configured to transmit a plurality of control signals to respectively control display statuses of the pixel arrays of the micro LED devices.
[0049] On the other hand, the core circuit 620 may also operate in an always-on-display (AOD) mode. In the always-on-display mode, the core circuit 620 may suspend the interface circuit 610 from receiving the display data DSPI from the outside, have the memory provide the display data DSPI to serve as the basis for generating the control signal DataX, and start a charge pump circuit to generate a boost power.), comprising:
a screen (Su, [0055] Referring to FIG. 7, FIG. 7 is a schematic view showing a controller in a micro LED display according to another embodiment of the disclosure.);
a non-volatile memory array (NVM) configured to store AOD information being displayed on the display panel in the AOD mode, wherein the AOD information comprises static content to be displayed during the AOD mode (Su, [0051] In the always-on-display mode, the display data DSPI provided by the memory may be a static display picture of one single image, or a dynamic picture of a plurality of images, and the disclosure is not limited thereto.
[0055] Referring to FIG. 7, FIG. 7 is a schematic view showing a controller in a micro LED display according to another embodiment of the disclosure. A controller 700 includes an interface circuit 710, a color engine circuit 720, a de-mura part 731, a data driving circuit 740, a static memory 750, a gal11llla circuit 760, an instruction control circuit 770, a non-volatile memory 780, an analog controller 790, a voltage regulator 7100, an oscillator 7110, an open/ short circuit detector 7120, a timing controller 7130, a latch 7140, a driving selection circuit 7150, a scan driving circuit 7160, and a temperature sensor 7170.);
a random-access memory (RAM) configured to receive image data to be displayed on the screen in a non-AOD mode (Su, [0049] On the other hand, the core circuit 620 may also operate in an always-on-display (AOD) mode. In the always-on-display mode, the core circuit 620 may suspend the interface circuit 610 from receiving the display data DSPI from the outside, have the memory provide the display data DSPI to serve as the basis for generating the control signal DataX, and start a charge pump circuit to generate a boost power.
Therefore, in the non-AOD mode, the interface circuit 610 is receiving display data DSPI from the outside.);
Su fails to explicitly teach, however, Lee teaches one or more processors (Lee, abstract, the invention describes a display device which comprises: a display panel driving only pixels within a partial area of a screen capable of fingerprint recognition in a specific driving mode; an image sensor facing the partial area of the screen; and a display panel driving circuit driving the pixels of the display panel. The brightness of the partial area of the screen is increased in the certain driving mode and a fingerprint on the partial area is recognized when the image sensor is driven.
[0021] The display device of the present invention can be applied to a mobile information terminal. Mobile information terminals include mobile phones, smartphones, tablet computers, laptop computers, wearable devices, etc.
It is considered inherited that a computer includes processor(s) such as CPU/GPU.); and
a memory storing instructions which, when executed by the one or more processors, cause the circuitry to:
selectively activate a subset of the plurality of pixels on the display panel based on the AOD information, wherein remaining pixels on the display panel are deactivated during the AOD mode to reduce power consumption (Lee, [0021] … When the AOD function is activated, the mobile information terminal does not display the entire screen but displays only some pixels on the screen (partial display) to always display simple AOD information such as the date and time. If AOD information is always displayed on pixels in the same location, the degradation of those pixels progresses faster than other pixels, which may result in afterimages. To improve this, the AOD area on the screen can be moved within the fingerprint recognition area. The present invention displays AOD information at a location on the screen where fingerprint recognition is possible, and displays an image, symbol, character, etc. that guides fingerprint input in the AOD area.).
Su and Lee are analogous art because they both teach display with always-on mode. Lee further teaches activating partial pixel in the screen when in the AOD mode. Therefore, it would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention, to modify the AOD display (taught in Su), to further include circuits that activating only part of the display pixels (taught in Lee), so as to prevent pixel degradation and save power (Lee, [0021]).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Huang (US20190086730) in view of Kavalieros et al (US20190080731) further in view of further in view of Bi et al (US20140375704).
Regarding Claim 20. Kavalieros teaches A circuitry for a touch and display panel (Kavalieros, abstract, the invention describes methods for providing data to be used in an in-memory computation at a memory device. In an embodiment a memory device comprises a first memory array and circuitry, coupled to the first memory array, to perform a data computation based on data stored at the first memory array. Prior to the computation , the first memory array receives the data from a second memory array of the memory device . The second memory array extends horizon tally in parallel with, but is offset vertically from, the first memory array. In another embodiment, a single integrated circuit die includes both the first memory array and the second memory array.
[0101] Depending on its applications, computing device 800 may include other components that may or may not be physically and electrically coupled to the board 802. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).), comprising:
a touch sensing module configured to receive user touch input from the touch and display panel, wherein the user touch input corresponds to image data to be displayed on the touch and display panel (It is considered inherited that a touchscreen display such as a smart phone includes touch sensing to receive user touch input for display image data such as video and pictures.);
a display module comprising a first non-volatile memory array and a second non-volatile memory array (Kavalieros, abstract, the invention describes methods for providing data to be used in an in-memory computation at a memory device. In an embodiment a memory device comprises a first memory array and circuitry, coupled to the first memory array, to perform a data computation based on data stored at the first memory array. Prior to the computation, the first memory array receives the data from a second memory array of the memory device. The second memory array extends horizon tally in parallel with, but is offset vertically from, the first memory array. In another embodiment, a single integrated circuit die includes both the first memory array and the second memory array.
[0016] For example, a memory device may include a first array of memory cells
(or "memory array") and circuitry, coupled thereto, which is operable to detect a logic state based on one or more bits currently stored by the first array. Such circuitry may perform one or more data computations based on the logic state), wherein:
the first non-volatile memory array comprises a plurality of memory cells
preprogrammed to store luminance correction data, the second non-volatile memory array comprises a plurality of memory cells configured to receive and store the image data to be displayed on the touch and display panel (Kavalieros, [0016] For example, a memory device may include a first array of memory cells (or "memory array") and circuitry, coupled thereto, which is operable to detect a logic state based on one or more bits currently stored by the first array. Such circuitry may perform one or more data computations based on the logic state), and
Kavalieros fails to explicitly teach, however, Huang teaches a logic circuit configured to generate digital data based on the luminance
correction data and the image data (Huang, [0032] FIG. 4 illustrates a display device according to one embodiment of the present invention. FIG. 5 illustrates a communication architecture according to one embodiment of the present invention. Please refer to FIGS. 4 and 5, in one embodiment of the present invention, a driving apparatus 11 of a display device comprises: a display module 160; a first substrate 50 including: a storage unit 110 electrically connected to the display module 160, the storage unit 110 saving display parameters of the display module 160, wherein the display parameters include a gamma correction code 112, a common electrode voltage setting code 114, and an uneven brightness distribution compensation module code 116; a second substrate 60 including: a control module (not shown) electrically coupled to the storage unit 110.
[0038], refers to FIG. 5, in one embodiment of the present invention, in a production line, a present driving method for a display device is provided. At first, a
common electrode voltage is adjusted to an optimal voltage value for each display
panel. The above-mentioned common electrode voltage setting code 114 is saved in
the storage unit 110. And, processes of gamma correction and mura compensation are performed to form a gamma correction code 112 and an uneven brightness distribution compensation module code 116. Then, the gamma correction code 112 and the uneven brightness distribution compensation module code 116 are saved in the storage unit 110, wherein different codes are saved in different addresses so that the timing control unit 120 can read them correctly. Therefore, each panel can have their own matching information (codes or parameters), so that it is unnecessary to provide an extra control board for each panel.);
Kavalieros teaches method in touchscreen display brightness adjustment. Huang teaches method of adjusting display brightness evenness by using display controller with embedded memory. Therefore, it would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention, to modify touchscreen display brightness adjustment (taught in Kavalieros), to further implement i the display brightness evenness method (taught in Huang), so as to provide the display with even luminance.
The combination of Kavalieros and Huang fails to explicitly teach, however, Bi teaches an input/output interface configured to convert the digital data into analog data and output the analog data to the touch and display panel for rendering (Bi, abstract, the invention describes display driver circuitry in the display analyzing the data to detect static data. The image data may contain static frames of data or static portions of a frame of data. In response to detection of static data, the display driver circuitry can take actions to avoid display damage due to bum-in effects. The display driver circuitry may reduce a peak luminance value associated with a peak luminance control algorithm, may reduce display brightness, may map image data to reduced brightness levels, or may take other actions to ensure that display pixels in the display are not damaged. Temperature information may be used in determining how to classify information as static data and in determining how significantly to reduce display pixel drive currents in response to the detection of static image data.
[0101] To accurately represent images on display 14, display 14 uses gamma curve selection circuitry to implement an appropriate gamma curve shape under a variety of operating conditions. An illustrative gamma curve is shown in FIG. 14A. As shown in FIG. 14A, gamma curve 200 maps different digital gray levels in an image to corresponding brightness values for the display pixels in display 14. The shape of curve 200 may be coarsely defined by points 201, which may correspond to a set of digital-to-analog converter input voltages (V255, Vl 91 , ... VO). In a color display, each color (red, green, and blue) may have a corresponding gamma curve. Maintaining a satisfactory gamma curve shape for each color under a variety of brightness and peak luminance control settings allows display 14 to present accurate images to a user. Care should be taken when adjusting gamma curve shape in response to different operating conditions. For example, linear scaling of a gamma curve when display brightness is reduced by 50% due to a user brightness change would result in suboptimal performance for a display.).
Kavalieros teaches method in touchscreen display brightness adjustment. Huang teaches method of adjusting display brightness evenness by using display controller with embedded memory. Bi further teaches using changing pixel voltage to compensate the pixel color/luminance value. Therefore, it would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention, to modify touchscreen display brightness adjustment (taught in Kavalieros and Huang), to further implement changing pixel voltage to compensate the pixel color/luminance value (taught in Bi), so as to provide the display with even luminance.
Allowable Subject Matter
Claims 7-10, 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 7, it recites “The circuitry of claim 1, wherein the geometry correction data is selected from a group consisting of shape information of the display device for Fringe adjustment, Foveation correction data for foveated display, and Wobulation correction data for wobulated display” in the context of Claim 7.
The prior arts of record either alone or in combination fails to teach or suggest the above quoted limitation of Claim 7. Therefore, Claim 7 is allowable over prior art.
Claims 8-10 depend from Claim 7 with respective additional limitations. Therefore, Claims 8-10 are allowable over prior art.
Regarding Claim 19, it recites “wherein the NVM is further configured to store multiple predefined AOD display configurations, and the circuitry is configured to switch between the predefined AOD display configurations based on the device status information, including battery level, usage patterns, or time of day.”in the context of Claim 19.
The prior arts of record either alone or in combination fails to teach or suggest the above quoted limitation of Claim 19. Therefore, Claim 19 is allowable over prior art.
Conclusion
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/Xin Sheng/ Primary Examiner, Art Unit 2619
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