Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is sent in response to Applicant’s Communication received on 06 August 2026 for application number 18/923,467. The Office hereby acknowledges receipt of the following and placed of record in file: Oath/Declaration, Abstract, Specification, Drawings, and Claims.
Claims 1, 2, 10, 11, 16, and 17 are currently amended.
Claims 1 – 20 are presented for examination.
Continued Prosecution Application
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after allowance or after an Office action under Ex Parte Quayle, 25 USPQ 74, 453 O.G. 213 (Comm'r Pat. 1935). Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant's submission filed on 06 August 2026 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Sen et al. [hereafter as Sen], US Pub. No. 2021/0019069 A1 in view of Lee et al. [hereafter as Lee], US Pub. No. 2023/0359566 A1 and further in view of Eliasmith et al. [hereafter as Eliasmith], US Pub. No. 2014/0156577 A1.
As per claim 1, Sen discloses a method, comprising:
storing data in a plurality of memory devices [memory pool media] connected to a computer express link fabric [“Flexible interface 1872 can communicate with memory controllers 1878 using any type of connection (e.g., UPI, PCIe, CXL, DDR, and so forth)…. using memory pool media 1880.”] [0102];
receiving, in the computer express link fabric, first memory access requests identifying memory addresses in the mapped memory space [“Flexible interface 1872 can communicate with memory controllers 1878 using any type of connection (e.g., UPI, PCIe, CXL, DDR, and so forth)... flexible interface 1872 can output a request in a form read or write N bytes at address X and memory controllers 1878 could map the read or write into a format appropriate for the media.”] [0102];
routing, by the computer express link fabric according to the mapping, the first memory access requests [output a request] to the plurality of memory devices [“Flexible interface 1872 can communicate with memory controllers 1878 using any type of connection (e.g., UPI, PCIe, CXL, DDR, and so forth)... flexible interface 1872 can output a request in a form read or write N bytes at address X and memory controllers 1878 could map the read or write into a format appropriate for the media.”] [0102];
options selected to route the first memory access requests to the plurality of memory devices [“FIG. 20A depicts an example memory node system. Memory node 2000 can use a fabric interface 2002, ML engine 2004 (or inference engine), memory controller (MCU) 2006, lower latency memory 2010, medium latency memory 2012, and higher latency memory 2014 (e.g., high-capacity media (HCM)). Various examples of operations of flexible fabric interface 2002 and memory controller 2006 are described herein. Media in memory pool can be a heterogenous mix of memory and storage (e.g., DRAM, 3D XPoint, 2LM, SSD, hard disk drive, and so forth) where each memory media has different latency characteristics among lower latency (e.g., DRAM), medium latency (e.g., 3D XPoint or 2LM), and higher latency (e.g., SSD or hard disk drive).”] [para. 0113].
However, Sen does not explicitly disclose storing data specifying mapping of first portions of a mapped memory space to second portions of random access memory cells;
measuring rewards for options.
Lee teaches storing data specifying mapping of first portions of a mapped memory space to second portions of random access memory cells [“map data that is stored in a nonvolatile memory of the storage device to the memory through the second interface in an initialization operation; storing, by the memory, the map data in a volatile memory of the memory in the initialization operation…”] [para. 0008].
Sen and Lee are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Sen with Lee in order to modify Sen for “storing data specifying mapping of first portions of a mapped memory space to second portions of random access memory cells” as taught by Lee. One of ordinary skill in the art would be motivated to combine Sen with Lee before the effective filing date of the claimed invention to improve a system by providing a “link …between the CXL storage … and the CXL memory …, a computing system with improved performance is provided.” [Lee, para. 0071].
However, Sen and Lee do not explicitly disclose measuring rewards for options.
Eliasmith teaches measuring rewards for options [“An open square end of the line connecting reward evaluation subsystem 308 and action selection controller 318 indicates that this connection can modulate connection weights. Modulating connection weights may involve simple enabling or disabling connections, however, modulation may further involve modifying a connection weight matrix underlying the connection.”] [para. 0091].
Sen, Lee, and Eliasmith are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Sen and Lee with Eliasmith in order to modify Sen and Lee for “measuring rewards for options” as taught by Eliasmith. One of ordinary skill in the art would be motivated to combine Sen and Lee with Eliasmith before the effective filing date of the claimed invention to improve a system by providing “where the system can learn to choose an option, out of a set of available choices, that results in what is anticipated to produce the highest immediate reward based on past history.” [Eliasmith, para. 0072].
Claims 10 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Sen et al. [hereafter as Sen], US Pub. No. 2021/0019069 A1 in view of Lee et al. [hereafter as Lee], US Pub. No. 2023/0359566 A1 and further in view of Hyatt [hereafter as Hyatt], US Patent No. 12,423,226 B2.
As per claim 10, Sen discloses a system, comprising:
a computer express link fabric [“Flexible interface 1872 can communicate with memory controllers 1878 using any type of connection (e.g., UPI, PCIe, CXL, DDR, and so forth)... flexible interface 1872 can output a request in a form read or write N bytes at address X and memory controllers 1878 could map the read or write into a format appropriate for the media.”] [0102] having:
a controller [“Flexible interface 1872 can communicate with memory controllers 1878 using any type of connection (e.g., UPI, PCIe, CXL, DDR, and so forth)…. using memory pool media 1880.”] [0102] configured to:
storing data in a plurality of memory devices [memory pool media] connected to a computer express link fabric [“Flexible interface 1872 can communicate with memory controllers 1878 using any type of connection (e.g., UPI, PCIe, CXL, DDR, and so forth)…. using memory pool media 1880.”] [0102].
However, Sen does not explicitly disclose a plurality of computer express link switches;
a plurality of computer express link connections among the computer express link switches; and
store data specifying mapping of first portions of a mapped memory space to second portions of random access memory cells; and
select options to control the computer express link switches in routing according to the mapping, first memory access requests to the plurality of memory devices.
Lee teaches store data specifying mapping of first portions of a mapped memory space to second portions of random access memory cells [“map data that is stored in a nonvolatile memory of the storage device to the memory through the second interface in an initialization operation; storing, by the memory, the map data in a volatile memory of the memory in the initialization operation…”] [para. 0008].
Sen and Lee are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Sen with Lee in order to modify Sen to “store data specifying mapping of first portions of a mapped memory space to second portions of random access memory cells” as taught by Lee. One of ordinary skill in the art would be motivated to combine Sen with Lee before the effective filing date of the claimed invention to improve a system by providing a “link …between the CXL storage … and the CXL memory …, a computing system with improved performance is provided.” [Lee, para. 0071].
However, Sen and Lee do not explicitly disclose a plurality of computer express link switches;
a plurality of computer express link connections among the computer express link switches; and
select options to control the computer express link switches in routing according to the mapping, first memory access requests to the plurality of memory devices.
Hyatt teaches a plurality of computer express link switches [“…multiple “Resource Composer” entities, each connecting to different switches within a CXL Fabric and exposing various logical devices to different PCEs. Some Resource Composers connect to the switch via a single CXL link (supporting data, control, and status management), while others utilize multiple CXL links to enhance bandwidth availability. This diversity in connections underscores the system's adaptability to different bandwidth and communication requirements.”] [col. 19, lines 51-62];
a plurality of computer express link connections among the computer express link switches [“FIG. 9 illustrates a Multi-Host, Multi-Resource Composer System Interconnected via switch fabric. This figure underscores the system's scalability and versatility, illustrating the presence of multiple “Resource Composer” entities, each connecting to different switches within a CXL Fabric and exposing various logical devices to different PCEs. Some Resource Composers connect to the switch via a single CXL link (supporting data, control, and status management), while others utilize multiple CXL links to enhance bandwidth availability. This diversity in connections underscores the system's adaptability to different bandwidth and communication requirements.”] [col. 19, lines 51-62] [“The memory pool in the system, integral for managing and allocating DRAM across different hosts, incorporates a switch and address mapping tables for directing memory access requests originating from PCE2 to various memory sources.”] [col. 12, lines 19-23]; and
select options to control the computer express link switches in routing according to the mapping, first memory access requests to the plurality of memory devices [“FIG. 9 illustrates a Multi-Host, Multi-Resource Composer System Interconnected via switch fabric. This figure underscores the system's scalability and versatility, illustrating the presence of multiple “Resource Composer” entities, each connecting to different switches within a CXL Fabric and exposing various logical devices to different PCEs. Some Resource Composers connect to the switch via a single CXL link (supporting data, control, and status management), while others utilize multiple CXL links to enhance bandwidth availability. This diversity in connections underscores the system's adaptability to different bandwidth and communication requirements.”] [col. 19, lines 51-62] [“The memory pool in the system, integral for managing and allocating DRAM across different hosts, incorporates a switch and address mapping tables for directing memory access requests originating from PCE2 to various memory sources.”] [col. 12, lines 19-23].
Sen, Lee, and Hyatt are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Sen and Lee with Hyatt in order to modify Sen and Lee “a plurality of computer express link switches;
a plurality of computer express link connections among the computer express link switches; and
select options to control the computer express link switches in routing according to the mapping, first memory access requests to the plurality of memory devices” as taught by Hyatt. One of ordinary skill in the art would be motivated to combine Sen and Lee with Hyatt before the effective filing date of the claimed invention to improve a system by providing where a “topological framework enables the switches associated with memory pool … and memory pool … to communicate seamlessly with one another.” [Hyatt, col. 15, lines 27-29].
Claim 16 is rejected with like reasoning.
Conclusion
STATUS OF CLAIMS IN THE APPLICATION
CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1 – 20 have received a first action on the merits and are subject of a first action non-final. Claim 1, 10, and 16 are rejected under a 103 rejection.
Allowable Subject Matter
Claims 2, 11, and 17 are objected to as being dependent upon a rejected based claim, but are considered as containing allowable subject matter. These claims would be allowable if rewritten in independent form to include all of the limitations of the base claim and any intervening claims. Claims 3 – 9, 12 – 15, and 18 – 20 depend from claims 2, 11, and 17 and are objected to as considered containing allowable subject matter due to their dependency.
The following is a statement of reasons for the indication of allowable subject matter: for dependent claims 2, 11, and 17 the prior art of record, neither anticipates, nor renders obvious using a reinforcement learning technique and the measured rewards selected routing options for updating information to select options for routing second memory access requests to memory devices that are received in a computer express link fabric (CXL). The prior art of record teaches a computer express link fabric and using a reinforcement learning technique for memory accesses, however this is with regards to a memory controller communicating requests into a proper format based on different memory technologies, and it does not teach selecting options for routing second memory access requests to memory devices via a CXL based on updating the routing information using measure rewards and reinforcement learning. The prior art of record also teaches measured rewards and reinforcement learning, but not with regards to using them for updating selected routing options for updating information to select options for routing second memory access requests to memory devices that are received in a computer express link fabric (CXL). Claims 3 – 9, 12 – 15, and 18 – 20 depend from claims 2, 11, and 17 and would be allowable based on their dependency.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD WADDY JR whose telephone number is (571)272-5156. The examiner can normally be reached M-Th 8am-5pm.
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/EW/Examiner, Art Unit 2135
/MARK A GIARDINO JR/Primary Examiner, Art Unit 2135
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