DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
1. The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “configured to” in claims 1-20.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claims 1-7, 9-20 are rejected under 35 U.S.C. 103 as being unpatentable over Shrader (Pub. No. US20160124872) in view of Benisty et al. (Pub. No. US 20230221889)
As per claim 1, Shrader discloses a method, comprising:
receiving, in a computer express link switch (fig.16, memory switch 210) having a plurality of ports (fig.6, host/leaf links), an incoming memory access request (paragraph 29, line 4, incoming traffic/requests, and routes the traffic/request to the appropriate leaf link);
identifying, by the computer express link switch, a plurality of options to route the incoming memory access request (paragraph 58, lines 11-13, identify context for commands and transactions received in the requests from the external host processors' requests during operation of the memory appliance.);
routing, by the computer express link switch according to an option selected from the plurality of options, the incoming memory access request to a port among the plurality of ports (paragraph 29, line 4, the low-latency memory switch 210 inspects an address associated with the incoming traffic/requests, and routes the traffic/request to the appropriate leaf link.);
Shrader discloses all the limitations as the above but does not explicitly discloses determining, by the computer express link switch, a latency of a response to the incoming memory access request; and updating, by the computer express link switch, information configured to select the option from the plurality of options based on the latency. However, Benisty discloses this. (paragraph 24, in response to determining that the queue is associated with the second processor, selecting a second data path to the queue, wherein the first and second data paths have different latency and/or throughput attributes. In addition, the controller 102 interacts simultaneously with the host's CPU and GPU while using different access attributes (e.g., access latency) for each. The controller 102 detects requests per submission queue and utilizes the link with different configuration settings based on the destination of each packet with different attributes and several data path configurations as further cited in paragraph 72)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Benisty with the teaching of Shrader so as to provide a system for reducing latency to make system more efficient and so as to yield the predicatable result so as to control efficiently, thus enhance the system performance.
As per claims 9 and 15, Shrader discloses a computer express link switch (fig.16, memory switch 210), comprising:
a plurality of ports (fig.6, host/leaf links); and
a circuit configured to: perform an allocation of resources connected to the ports to implement portions of a mapped memory space (paragraph 29, line 4, the low-latency memory switch 210 inspects an address associated with the incoming traffic/requests, and routes the traffic/request to the appropriate leaf link);
receive memory access requests having memory addresses in the mapped memory spaces (paragraph 58, lines 11-13, identify context for commands and transactions received in the requests from the external host processors' requests during operation of the memory appliance.);
route, according to the allocation, the memory access requests to the ports to receive responds (paragraph 22, allocate resources from a shared pool to various applications and OS instances);
Shrader discloses all the limitations as the above but does not explicitly discloses make an adjustment to the allocation to measure an average latency of responses in a time interval of a predetermined length following the adjustment; and update, based on the average latency and using a reinforcement learning technique, information configured to select options to adjust the allocation in implementing the portions of the mapped memory space. However, Benisty discloses this. (paragraph 68, adapting the data path may include changing the attributes of the TLP, such as maximum packet size and maximum read request size and/or other control fields in the TLP, based on the destination. In addition at paragraph 24, selecting a second data path to the queue, wherein the first and second data paths have different latency and/or throughput attributes, and the controller 102 interacts simultaneously with the host's CPU and GPU while using different access attributes (e.g., access latency) for each. The controller 102 detects requests per submission queue and utilizes the link with different configuration settings based on the destination of each packet size with different attributes and several data path configurations as further cited in paragraph 72)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Benisty with the teaching of Shrader so as to provide a system for reducing latency to make system more efficient and so as to yield the predicatable result so as to control efficiently, thus enhance the system performance.
As per claim 10, Shrader discloses the method further comprising: determining, by the computer express link switch, a next state of the computer express link switch at a time of routing of a next memory access request (paragraph 69, Turnaround time of the PCIe link is the time from the data storage device 100 issuing a read request until getting back the data); and
identifying, by the computer express link switch, a maximum value among a column of the reward table corresponding to the next state of the computer express link switch (paragraph 69, lines 1-3, a maximum number of outstanding transactions issued on a PCIe link is adapted based on the destination (e.g., CPU or GPU));
wherein the expected reward value is updated using a sum of a reward value as a function of the latency and the maximum value multiplied by a predetermined discount factor. (paragraph 67-68, lists (SGL) fetching, data transfer, completion posting, and interrupt posting with an NVMe command and destination. The controller 102 adapts the data path based on the results and data path configurations that are changed dynamically based on the current outstanding transactions.)
As per claims 11 and 17, Shrader discloses wherein the allocation includes allocating a portion of random access memory of a memory device connected directly to a first port of the plurality of ports to implement a first portion of the mapped memory space (paragraph 24, respective memory resource that can be partially or wholly allocated to each of the processors in the compute tier); and the adjustment includes allocating a portion of a storage space of a memory sub-system, addressable using logical block addressing addresses and connected directly to a second port of the plurality of ports, to implement the first portion of the mapped memory space (paragraph 29, The low-latency memory switch 210 inspects an address associated with the incoming traffic/requests, and routes the traffic/request to the appropriate leaf link).
As per claims 12 and 18, Shrader discloses wherein the allocation includes allocating a portion of a storage space of a memory sub-system(paragraph 24, respective memory resource that can be partially or wholly allocated to each of the processors in the compute tier), addressable using logical block addressing addresses and connected directly to a second port of the plurality of ports, to implement a first portion of the mapped memory space (paragraph 29, The low-latency memory switch 210 inspects an address associated with the incoming traffic/requests, and routes the traffic/request to the appropriate leaf link); and the adjustment includes allocating a portion of random access memory of a memory device connected directly to a first port of the plurality of ports to implement the first portion of the mapped memory space (paragraph 45, responds to requests by granting access and providing physical/logical access methods and memory attributes or denying access based on policy, authentication or resource constraints.)
As per claims 13 and 19, Shrader discloses wherein the allocation includes allocating a portion of random access memory of a first memory device connected directly to a first port of the plurality of ports to implement a first portion of the mapped memory space(paragraph 24, respective memory resource that can be partially or wholly allocated to each of the processors in the compute tier); and the adjustment includes allocating a portion of resources over a computer express link fabric (fig.6, link fabric) directly to one or more second ports of the plurality of ports to implement the first portion of the mapped memory space(paragraph 29, The low-latency memory switch 210 inspects an address associated with the incoming traffic/requests, and routes the traffic/request to the appropriate leaf link).
As per claims 14 and 20, Shrader discloses wherein the allocation includes allocating a portion of resources over a computer express link fabric directly to one or more second ports of the plurality of ports to implement a first portion of the mapped memory space (paragraph 24, respective memory resource that can be partially or wholly allocated to each of the processors in the compute tier); and the adjustment includes allocating a portion of random access memory of a first memory device connected directly to a first port of the plurality of ports to implement the first portion of the mapped memory space(paragraph 29, The low-latency memory switch 210 inspects an address associated with the incoming traffic/requests, and routes the traffic/request to the appropriate leaf link).
As per claims 16, Shrader discloses wherein the allocation includes allocating a portion of random access memory of a first memory device connected directly to a first port of the plurality of ports to implement a first portion of the mapped memory space(paragraph 24, respective memory resource that can be partially or wholly allocated to each of the processors in the compute tier); and the adjustment includes allocating a portion of random access memory of a second memory device connected directly to a second port of the plurality of ports to implement the first portion of the mapped memory space(paragraph 29, The low-latency memory switch 210 inspects an address associated with the incoming traffic/requests, and routes the traffic/request to the appropriate leaf link).
4. Claims 2-8 are rejected under 35 U.S.C. 103 as being unpatentable over Shrader (Pub. No. US20160124872) in view of Benisty et al. (Pub. No. US 20230221889) and further in view of Yu et al. (Pub. No. US 20220303230)
As per claim 2, Shrader discloses all the limitations as the above but does not explicitly disclose wherein the updating is according to a reinforcement learning technique. However, Yu discloses this. (paragraph 63, the AI model can use or include one or more of: a reinforcement learning scheme, Q-learning scheme, deep-Q learning, or Asynchronous Advantage Actor-Critic (A3C), combinatorial neural network, recurrent combinatorial neural network)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Yu with the teaching of Shrader in view of Benisty so as to provide a system with directly from trial-and-error (experiences) without needing to know the environment's rules (model), making it versatile so as to yield the predicatable result so as to control efficiently, thus enhance the system performance.
As per claim 3, Shrader discloses wherein the information includes a reward table having a plurality of rows corresponding to the plurality of ports respectively (paragraph 23, The resources of a data center rack 100 typically found in a single server system are split into tiers and physically separated into separate enclosures (or even into separate racks or rows within a datacenter))
As per claim 4, Benistry discloses wherein the reward table further includes a plurality of columns corresponding to a plurality of states of the computer express link switch. (paragraph 79, the memory elements may be arranged in the single memory device level in an ordered array, such as in a plurality of rows and/or columns.)
As per claim 5, Benistry discloses the method further comprising: determining, by the computer express link switch, a current state of the computer express link switch at a time of the routing of the incoming memory access request (paragraph 69, turnaround time of the PCIe link is the time from the data storage device 100 issuing a read request until getting back the data); wherein the updating includes updating an expected reward value in the reward table at a row corresponding to the port selected according to the option and at a column corresponding to the current state (paragraph 67-68, lists (SGL) fetching, data transfer, completion posting, and interrupt posting with an NVMe command and destination. the controller 102 adapts the data path based on the results and data path configurations that are changed dynamically based on the current outstanding transactions.)
As per claim 6, Benistry discloses the method further comprising: determining, by the computer express link switch, a next state of the computer express link switch at a time of routing of a next memory access request (paragraph 69, turnaround time of the PCIe link is the time from the data storage device 100 issuing a read request until getting back the data); and
identifying, by the computer express link switch, a maximum value among a column of the reward table corresponding to the next state of the computer express link switch (paragraph 69, lines 1-3, a maximum number of outstanding transactions issued on a PCIe link is adapted based on the destination (e.g., CPU or GPU));
wherein the expected reward value is updated using a sum of a reward value as a function of the latency and the maximum value multiplied by a predetermined discount factor. (paragraph 67-68, lists (SGL) fetching, data transfer, completion posting, and interrupt posting with an NVMe command and destination. The controller 102 adapts the data path based on the results and data path configurations that are changed dynamically based on the current outstanding transactions.)
As per claim 7, Benistry disclsoes wherein the expected reward value is replaced with a weighted average of the expected reward value and the sum. (paragraph 67-68, lists (SGL) fetching, data transfer, completion posting, and interrupt posting with an NVMe command and destination. The controller 102 adapts the data path based on the results and data path configurations that are changed dynamically based on the current outstanding transactions.)
As per claim 8, Shrader in view of Benisty disclose all the limitations as the above but does not explicitly disclose wherein the reinforcement learning technique is a Q- learning technique. However, Yu discloses this. (paragraph 63, the AI model can use or include one or more of: a reinforcement learning scheme, Q-learning scheme, deep-Q learning, or Asynchronous Advantage Actor-Critic (A3C), combinatorial neural network, recurrent combinatorial neural network)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Yu with the teaching of Shrader in view of Benisty so as to provide a system with directly from trial-and-error (experiences) without needing to know the environment's rules (model), making it versatile so as to yield the predicatable result so as to control efficiently, thus enhance the system performance.
Response to Amendment
5. Applicant's amendment filed on 3/31/2026 have been fully considered but does not place the application in condition for allowance.
a. In response to Applicant’s arguments that Shrader discloses “memory switch” not “compute express link switch”. Examiner respectfully disagrees. As Shrader notes at (paragraph 25, Examiner further cited for clarification), In one embodiment, the link 206 may comprise an existing high speed link such as DDRx, PCIe, SAS, SATA, QPI, and the like, or it may be a new dedicated link. Furthermore, the low-latency memory switch 210 may manage traffic/requests from many incoming host links 208 from many different processors/servers. The host links 208 to the memory appliance may hook into the CPU processors/servers via host links 208 through an existing DDR channel as further cited in paragraph 65. Thus, the prior art teaches the invention as claimed and the amended claims do not distinguish over the prior art as applied.
Applicant' s arguments are thus not persuasive towards patentability of the claims as presented and the rejections of record are maintained.
6. The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
HSIEH et al. [Pub. No. US20250181544] discloses the method includes determining, by the PCIe device, a latency tolerance reporting (LTR) value based on the measured throughput.
Conclusion
7. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIM T HUYNH whose telephone number is (571)272-3635 or via e-mail addressed to [kim.huynh3@uspto.gov]. The examiner can normally be reached on M-F 7.00AM- 4:00PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tsai Henry can be reached at (571)272-4176 or via e-mail addressed to [Henry.Tsai@USPTO.GOV].
The fax phone numbers for the organization where this application or proceeding is assigned are (571)273-8300 for regular communications and After Final communications. Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-2100.
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/K. T. H./
Examiner, Art Unit 2184
/HENRY TSAI/ Supervisory Patent Examiner, Art Unit 2184
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