DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 12-18 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 7/28/2026.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2 and 4-6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bogus et al. (USPN 10,895,601).
With respect to claim 1, Bogus et al. discloses in Figs. 1B, 2A-3, a driving apparatus (Fig. 2A, further details of 116 disclosed in Figs. 2D-2F and operations disclosed in Figs. 1B and 2G-3) of a power semiconductor (18 and 19), comprising:
a first circuit (one of 108 and 110);
a second circuit (other one of 108 and 110 with the circuit that generates CLK of Figs. 2D-2F);.
a state signal generation unit (116, further details disclosed in Figs. 2D-2F) that generates a first state signal (output of 116 to 104) indicating a state of the first circuit with a digital value of multiple bits (116 generates multiple bits, i.e., at least two of HS_ERR1, LS_ERR1, HS_ERR2, LS_ERR2 and DZ_ERR, that indicate the state of at least one of the high side and low side circuitry); and
a communication control unit (114, 112, 130, 128 and 140) that controls an output period in which the first circuit outputs the first state signal based (104 controls when 116 outputs the output of 116, since 104 controls when the multiple bits are output according to the DH_ON and DH_ON signals, see Figs. 2D-2H) on a loaded-state signal indicating a transition timing of ON/OFF of the power semiconductor (at least one of IN, DH_ON and DL_ON wherein each of the above signals indicate when at least one of 18 and 19 are turned on and/or off).
With respect to claim 2, the driving apparatus according to claim 1, wherein the communication control unit permits output of the first state signal after a predetermined stop period elapses from a timing at which the ON/OFF of the power semiconductor transits (220C and 220D of Fig. 2E generated HS_ERR2 and LS_ERR2 according to a predetermined stop period from when the de-assertion of DH_ON and DL_ON, i.e., stop, to a rising edge of SH. Thus, the stop period is from de-assertion to the rise of SH, see Col. 11 line 62 to Col. 12 line 3).
With respect to claim 4, the driving apparatus according to claim 2, wherein the communication control unit controls the stop period according to a characteristic of the power semiconductor (according to the value, i.e., high rising edge , of SH which is a characteristic of the activation times of 18 and 19).
With respect to claim 5, the driving apparatus according to claim 2, wherein the communication control unit controls the stop period according to a magnitude of a power supply voltage that is applied to the power semiconductor (the stop period is controlled, at least in part, by 114 which controls 116, see also Figs. 2D-2F. Furthermore, the output of 114 is controlled according to the magnitude of the power supply voltage VDH applied to 18/19, since 112 generates a voltage that is equal to VDH scaled by n. The voltage generated by 112 is applied to the input of 114. Thus, the stop period is controlled according to a magnitude of VDH).
With respect to claim 6, the driving apparatus according to claim 2, wherein the communication control unit controls the stop period according to a capacity of a load that is connected to the power semiconductor (both 128 and 130/SH are dependent upon the capacity of the load, i.e., the current draw of the load. The above elements control, at least in part, the stop period through the control of COMP and 104).
Claim(s) 10-11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Paganini et al. (USPAPN 2020/0244265).
With respect to claim 10, Paganini et al. discloses, in Fig. 2, a driving apparatus (5a) of a power semiconductor (1a), comprising:
a low side circuit (20) that operates with a first reference voltage (Vcc),
a high side circuit (10) that operates with a second reference voltage that is higher than the first reference voltage (Vb, which is a boosted/bootstrapped voltage that is larger than Vcc, see paragraph 0058),
a state signal generation unit (15) that generates a high side state signal indicating a state of the high side circuit (output of 15) with a digital value of multiple bits (outputs according to the multiple anomalous events, short circuits, overcurrent, over voltage, etc., events, see paragraph 0060, see also info bits to microcontroller from 23), and
a transmission unit (13 with 31) that transmits (output of 31 to 23), by converting a reference voltage of the high side state signal according to the first reference voltage (high voltage value from 10/13), the high side state signal (output of 15 from 13/31), which is obtained by converting the reference voltage, to the low side circuit (converted to the low power supply to 23/20 via 31, see paragraph 0061).
With respect to claim 11, the driving apparatus according to claim 10, wherein the low side circuit has a transmission unit that transmits the high side state signal to an outside (23 transmits “Info Bits” from 15/13/31 to the outside of 20 to microcontroller 5b).
Allowable Subject Matter
Claims 3, 7-9 and 19-21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thomas J. Hiltunen whose telephone number is (571)272-5525. The examiner can normally be reached 9:00AM-5:30PM EST M-F.
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/THOMAS J. HILTUNEN/Primary Examiner, Art Unit 2836
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