DETAILED ACTION
Claims 1-2, 5-9, 12-16, and 19-20 rejected under 35 USC § 102.
Claims 3-4, 10-11, and 17-18 rejected under 35 USC § 103.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 5-9, 12-16, and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Thampi et al., U.S. PG-Publication No. 2020/0401434 A1 (hereinafter THAMPI).
Claim 1
THAMPI discloses a computer, comprising: a hardware platform having a central processing unit (CPU), a memory, and a hardware clock. ¶ 0014: Host machine 100 includes hardware platform 102, processors 114, and memory 116. ¶ 0017: The hardware platform includes NIC 121, with a “high precision clock onboard the NIC” used to generate timestamps for PTP synchronization packets.
THAMPI discloses a hypervisor executing on the CPU and managing the hardware platform. Host machine 100 executed hypervisor 132, which includes operating system components that “operate the hardware platform 102 directly” and provides virtual hardware resources to the VMs.
THAMPI discloses a first virtual machine (VM) supported by the hypervisor and having a passthrough connection to the hardware clock. ¶ 0027: PTP VM 105 executes “atop a hypervisor 132,” with NIC 121 directly assigned to that VM. ¶ 0029: NIC 121 is directly assigned to PTP VM 105 using “PCI pass-through functionality,” allowing the VM to use the NIC as a native device.
THAMPI discloses first guest software executing in the first VM, the first guest software including a first system clock synchronized by communication with the hardware clock via the passthrough connection. ¶ 0023: PTP daemon 155 runs within operating system 153 of PTP VM 105. It obtains timing information from the clock signal or hardware timestamps of the directly assigned NIC and generates parameters for synchronizing the VM’s systems clock. ¶ 0029: The guest OS uses a NIC driver to control the NIC through its native device assignment and make it available to the PTP daemon for deriving the system clock or its parameters. ¶ 0043: The PTP daemon generates clock parameters using the NIC and performs a timestamp transformation to generate the PTP VM’s system clock.
THAMPI discloses a second VM supported by the hypervisor. PTP VM 105 executes on hypervisor 132 “along with other VMs 104a, 104b.”
THAMPI discloses second guest software executing in the second VM, the second guest software including a second system clock synchronized with the first system clock via a first portion of the memory shared between the first VM and the second VM, the first portion of the memory managed by the hypervisor. ¶ 0030: PTP VM 105 and recipient VMs share clock memory 204 using “a shared memory feature of the hypervisor 132.” Data written by the PTP VM becomes available in the recipient’s VMs’ memory. ¶ 0030: Recipient VMs run time sync application 161, which obtains parameters from clock memory 203 and uses them to “synchronize their respective system clocks.” ¶ 0033: The VMs generate their system clocks using “the same clock parameters 201,” producing precise synchronization among members of the PTP time domain.
Claim 2
THAMPI discloses wherein the hardware clock is part of a network interface controller (NIC) of the hardware platform. ¶ 0017: Hardware platform 102 includes NIC 121, and a “high precision clock onboard the NIC” generates timestamps for incoming and outgoing PTP synchronization packets.
Claim 5
THAMPI discloses wherein the hypervisor includes a first interface configured to write to the first portion of the memory, and wherein the first guest software is configured update the first portion of the memory via the first interface using output of the first system clock. ¶ 0044: PTP daemon 155 publishes clock parameters to clock memory 203 “using a memory sharing feature of hypervisor 132.” The daemon writes to a page established by the hypervisor for sharing with other VMs. ¶ 0032: Clock parameters generated by PTP VM 105 can include “a multiplier and a shift value applied to a common clock” shared by the VMs and host. ¶ 0043: The PTP daemon uses the parameters to generate its system clock. The parameters describe “how to transform a shared host clock to arrive at the current precise time” and are published to clock memory 203.
Claim 6
THAMPI discloses wherein the hypervisor includes a second interface
configured to read from the first portion of the memory, and wherein the second guest software is configured to read from the first portion of the memory via the second interface to update the second system clock. ¶ 0030: Clock memory 203 is shared using “a shared memory feature of the hypervisor 132.” Recipient VMs run time sync application 161 to obtain parameters from that memory and “synchronize their respective system clocks.” ¶ 0049: The recipient application obtains parameters published by the PTP VM through the hypervisor’s memory sharing feature. The shared pages appear as part of the recipient VM’s memory, and their contents are used to derive its clock.
Claim 7
THAMPI discloses at least one additional VM supported by the hypervisor, the at least one additional VM having at least one additional system clock synchronized with the first system clock via the first portion of the memory. ¶ 0030: PTP VM 105 and VMs 104a and 104b share clock memory 204 through hypervisor 132. Both recipient VMs run synchronization applications that obtain parameters from that memory and adjust their system clocks. ¶ 0033: Domain members generate their system clocks using “the same clock parameters 201,” resulting in precise synchronization among those members.
THAMPI discloses wherein the passthrough connection comprises access to the hardware clock by the first VM exclusive of the hypervisor, the second VM, and the at least one additional VM. ¶ 0029: PCI passthrough lets PTP VM 105 use NIC 121 as a native device and permits “exclusive assignment” of the NIC to that VM. ¶ 0023: PTP VM 105 can be exclusively assigned the PTP NIC, while other VMs receive virtual NICs that rely on other physical NICs.
Claims 8-9 and 12-14
Claims 8-9 and 12-14 are rejected utilizing the rationale for claims 1-2 and 5-7; the claims are directed to a method performed by the system.
Claims 15-16 and 19-20
Claims 15-16 and 19-20 are rejected utilizing the rationale for claims 1-2 and 5-7; the claims are directed to a medium storing instructions executed by the system.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-4, 10-11, and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Kasichainula et al., U.S. PG-Publication No. 2023/0262281 A1 (hereinafter KASICHAINULA).
Claim 3
KASICHAINULA discloses wherein the NIC is configured to synchronize the hardware clock with another hardware clock using messages exchanged with another NIC over a network using a protocol. ¶ 0027: The primary system includes NIC 326-1 containing “PTP timer circuitry 327-1.” ¶ 0028: The secondary system includes NIC 326-2 containing “PTP timer circuitry 327-2.” ¶ 0029: The systems communicate through PTP link 306, which may use an Ethernet cable or a wireless connection. ¶ 0031: The time in secondary NIC 326-2 “synchronizes its time to the PTP timer 327-1.” PTP messages are exchanged between the NICs to synchronize their timers in phase and frequency.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the NIC clock synchronization with another NIC’s hardware PTP timer through exchanged PTP messages taught by KASICHAINULA. One of ordinary skill in the art would be motivated to integrate that synchronization into THAMPI, with a reasonable expectation of success, in order to maintain consistent timing across machines despite differences in lock clock quality by synchronizing the NIC timers in phase and frequency, as taught by KASICHAINULA at ¶ 0033.
Claim 4
THAMPI discloses wherein the first guest software includes a driver configured to interface with the hardware clock via the passthrough connection, a first guest operating system (OS) having the first system clock, and first software configured to synchronize the system clock with the hardware clock using the driver. ¶ 0029: NIC 121 is directly assigned through PCI passthrough. Operating system 153 of PTP VM 105 uses “a NIC driver to control the NIC 121” and makes the NIC available to PTP Darmon 155 for deriving a system clock or its parameters. ¶ 0023: PTP daemon 155 runs within operating system 153 of PTP VM 105 and derives timing parameters from the clock signal or hardware timestamps supplied by its directly assigned NIC. Those parameters synchronize the PTP VM’s system clock. ¶ 0043: PTP daemon 155 generates clock parameters using NIC 121 and uses those parameters to “synchronize a system clock of the PTP VM 105.”
Claims 10-11
Claims 10-11 are rejected utilizing the rationale for claims 3-4; the claims are directed to a method performed by the system.
Claims 17-18
Claims 17-18 are rejected utilizing the rationale for claims 3-4; the claims are directed to a medium storing instructions executed by the system.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FRANK D MILLS whose telephone number is (571)270-3194. The examiner can normally be reached M-F 9-5:30 CT.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, KEVIN YOUNG can be reached at (571)270-3180. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/FRANK D MILLS/Primary Examiner, Art Unit 2194 September 27, 2026
