FINAL OFFICE ACTION
Status of the Claims
Claims 1-20 are rejected under 35 U.S.C 103
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7, 14-17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Solcia et al (U.S. Publication No. 2023/0230650 A1), hereinafter referred to as Solcia, in view of Zorian et al. (U.S. Patent No. 7,415,640 B1), hereinafter referred to as Zorian.
Regarding Claim 1, Solcia teaches:
A System on a Chip, comprising:
a function register, comprising multiple functional bits, ([0043]; regarding, “The shift register includes data bits 202A and addressing bits 202B. RAM R/W bits 202C, and a MUX enable bit 202D are also included.”);
wherein the System on a Chip performs a test operation based on data of at least one of the multiple functional bits; ([0045]; regarding, “Data is loaded into the shift register 202 one bit at a time when as directed by control signals received from a test controller. Once loaded, the data is transferred to the test register. A MUX intercepts the functional RAM control signals and toggles them to the signals received from the test register 204. The signals are then delivered to the System RAM 206 where they can be executed.”);
wherein when a bit value of a first setting bit among the multiple setting bits is a first value, the System on a Chip writes data coming from a first operating bit among the multiple operating bits into a first functional bit among the multiple functional bits, ([0066]; regarding, “The values of first selection bit 304E and second selection bit 304F may control the outputs of the first shift-register MUX 308, second shift-register MUX 310, and third shift-register MUX 312.”);
and wherein when the bit value of the first setting bit is a second value, the System on a Chip writes a first bit value of the test data into the first functional bit among the multiple functional bits. ([0056]; regarding, “The first shift-register MUX 308 may be coupled at a selection input with a bit of the test register 304. Thus, depending on the state of the selection input of the first shift-register MUX 308, the second section 302B will either receive the output of the first section 302A of the shift register 302 or the output of the first IO pin 314.”);
Solcia fails to explicitly disclose but Zorian teaches:
a one-time programmable memory, comprising multiple setting bits and multiple operating bits; (Col. 4, lines 24-31; regarding, “A fuse, such as the first fuse 212, is a non-volatile storage device, such as a Flash memory cell, an Electrically Programmable Read Only Memory cell, a one-time programmable memory cell, a few-time programmable memory cell, a laser fuse, or other similar component, that permanently stores fault information to perform the function of a fuse. All of the fuses may be contained a fuse box 214 located external to the memory block 216.”; Col. 5, lines 1-4; regarding, “A repair signature may be a compressed or not compressed form representing the logical 1 and 0 bits permanently stored in the fuse box 214.”);
and a processor, coupled to the function register and the one-time programmable memory and configured to receive test data during a test stage, (Col. 4, lines 22-25; regarding, “Each input output-circuit also couples a corresponding fuse via the processor 210.”; Col. 4, lines 32-34; regarding, “Each input output circuit contains a scan chain register to receive fault information permanently stored in the corresponding fuse, such as the first scan chain register 218.”);
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Solcia with the teachings of Zorian. Doing so can increase the yield of usable memories on a chip (Zorina, Col. 6, lines 51-55).
Regarding Claim 2, Solcia in view of Zorian teach the system of claim 1 as referenced above. Solcia in view of Zorian further teach:
a test data memory, coupled to the function register, wherein in the test stage, when the System on a Chip is reset and the bit value of the first setting bit is the second value, the System on a Chip writes the first bit value of the test data stored in the test data memory into the first functional bit among the multiple functional bits. (Solcia, [0041]; regarding, “The test data input 102, clock input 110, and test mode select 112 may all be coupled with an ATE 124, which can then control LRE tests. The ATE may also be coupled with the test data output 106 to receive the results of any tests performed. And, an ATE may assert a reset signal coupled with the reset input 114 during test operations. While an LRE test is being performed some or all of the additional pins on the SoC may be unused or otherwise available.”; [0056]; regarding, “The first shift-register MUX 308 may be coupled at a selection input with a bit of the test register 304. Thus, depending on the state of the selection input of the first shift-register MUX 308, the second section 302B will either receive the output of the first section 302A of the shift register 302 or the output of the first IO pin 314.”).
Regarding Claim 3, Solcia in view of Zorian teach the system of claim 2 as referenced above. Solcia in view of Zorian further teach:
wherein while the System on a Chip is running, the test data that has been written in the test data memory is prohibited from being modified. (Zorian, Col. 4, lines 24-26; regarding, “A fuse, such as the first fuse 212, is a non-volatile storage device, such as a… Read Only Memory cell”).
Regarding Claim 4, Solcia in view of Zorian teach the system of claim 2 as referenced above. Solcia in view of Zorian further teach:
while System on a Chip is running, the test data is one-time written into the test data memory, (Zorian, Col. 5, lines 27-31; regarding, “The repair data container may be a fuse box 314. The fuse box 314 stores actual repair signatures for each memory having one or more defective memory cells and dummy repair signatures for each memory with no defective memory cells.”);
and the test data memory is initialized based on a power-on procedure of the System on a Chip. (Zorian, Col. 10, lines 13-16; regarding, “A repair may be performed in the field with software on each power up and the repair signature generated in the field may augment the repair signature coming from the fuse box.”).
Regarding Claim 5, Solcia in view of Zorian teach the system of claim 1 as referenced above. Solcia in view of Zorian further teach:
wherein the System on a Chip receives the test data coming from an external test device. (Zorian, Col. 4, lines 53-57; regarding, “an external test device or the processor 210 may execute a repair algorithm to generate a repair signature to properly allocate the redundant components 234 associated with the memory 202 to repair the memory 202.”).
Regarding Claim 7, Solcia in view of Zorian teach the system of claim 1 as referenced above. Solcia in view of Zorian further teach:
wherein when the bit value of the first setting bit is the first value, the System on a Chip performs a logical operation on data coming from a first operating bit group among the multiple operating bits so as to generate the data of the first operating bit. (Solcia, [0054]; regarding, “the value of the MUX enable bit 304D used to toggle the output may vary. For example, a “1” may control the MUX to output data from the test register 304”).
Claims 14-16 are rejected under 35 U.S.C. under the same grounds of rejection as claims 1-3 respectively.
Regarding Claim 17, Solcia in view of Zorian teach the method of claim 14 as referenced above. Solcia in view of Zorian further teach:
while the System on a Chip is running, the test data is one-time written into the test data memory, and the test data memory is initialized based on a power-on procedure of the System on a Chip. (Zorian, Col. 5, lines 27-31; regarding, “The repair data container may be a fuse box 314. The fuse box 314 stores actual repair signatures for each memory having one or more defective memory cells and dummy repair signatures for each memory with no defective memory cells.”; Col. 10, lines 13-16; regarding, “A repair may be performed in the field with software on each power up and the repair signature generated in the field may augment the repair signature coming from the fuse box.”).
Regarding Claim 20, Solcia in view of Zorian teach the method of claim 14 as referenced above. Solcia in view of Zorian further teach:
(Solcia, [0054]; regarding, “the value of the MUX enable bit 304D used to toggle the output may vary. For example, a “1” may control the MUX to output data from the test register 304”).
Claim Rejections - 35 USC § 103
Claims 6, 9-13, and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Solcia et al (U.S. Publication No. 2023/0230650 A1), hereinafter referred to as Solcia, in view of Zorian et al. (U.S. Patent No. 7,415,640 B1), hereinafter referred to as Zorian, in further view of Ling et al (U.S. Publication No. 2012/0294100 A1), hereinafter referred to as Ling.
Regarding Claim 6, Solcia in view of Zorian teach the system of claim 5 as referenced above. Solcia in view of Zorian fail to explicitly disclose but Ling teaches:
wherein the System on a Chip receives the test data based on a transmission protocol. ([0030]; regarding, “The AFE 102 may be operable to transmit and/or receive information utilizing any suitable communication protocol(s).”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Solcia and Zorian with the teachings of Ling. Doing so can improve performance and or reduce power consumption (Ling, [0042]).
Regarding Claim 9, Solcia in view of Zorian in further view of Ling teaches:
A test device for testing System on a Chip,
wherein the System on a Chip comprises a one-time programmable memory, and wherein the one-time programmable memory comprises multiple setting bits and multiple operating bits, (Zorian, Col. 7, lines 6-12; regarding, “In a large memory, such as a four megabyte memory, five hundred and twelve columns of memory cells may exist. Therefore, the reconfiguration data consists of five hundred and twelve bits of logical 1s and 0s.”; Col. 4, lines 19-28; regarding, “The example memory 202 has columns and rows of memory cells coupling to each of the input-output circuits, such as a first group of columns of non-redundant memory cells 208. Each input output-circuit also couples a corresponding fuse via the processor 210. A fuse, such as the first fuse 212, is a non-volatile storage device, such as a Flash memory cell, an Electrically Programmable Read Only Memory cell, a one-time programmable memory cell”);
the test device comprising: an input unit; (Col. 4, lines 53-55; regarding, “then either an external test device or the processor 210 may execute a repair algorithm to generate a repair signature”);
a test data memory; (Col. 7, lines 57-60; regarding, “…reconfiguration data signal is generated and then sent into the corresponding memory.);
a processor, coupled to the test data memory, configured to receive multiple test data coming from outside, (Col. 4, lines 53-55; regarding, “an external test device or the processor 210 may execute a repair algorithm to generate a repair signature.”; Col. 5, lines 5-7; regarding, “The processor 210 loads the repair signature in…”);
write the multiple test data into the test data memory, (Col. 4, lines 57-61; regarding, “an external test device or the processor 210 may cause one or more fuses to signify this defect by changing the fuse's status, and thus, permanently store the location of where the defective non-redundant memory cell was detected.”);
select selected test data from the multiple test data in response to operation of the input unit, (Col. 4, lines 53-57; regarding, “an external test device or the processor 210 may execute a repair algorithm to generate a repair signature to properly allocate the redundant components 234 associated with the memory 202 to repair the memory 202.”);
and provide the selected test data to the System on a Chip by a transmission protocol, (Ling, [0030]; regarding, “The AFE 102 may be operable to transmit and/or receive information utilizing any suitable communication protocol(s).”).
wherein the System on a Chip receives the selected test data based on the transmission protocol, selects partial bit values of the test data based on bit values of the multiple setting bits, and performs a test operation based on the partial bit values, (Solcia, [0045]; regarding, “Data is loaded into the shift register 202 one bit at a time when as directed by control signals received from a test controller. Once loaded, the data is transferred to the test register. A MUX intercepts the functional RAM control signals and toggles them to the signals received from the test register 204. The signals are then delivered to the System RAM 206 where they can be executed.”);
wherein when a bit value of a first setting but among the multiple setting bits is a first value, the System on a Chip writes data coming from a first operating bit among the multiple operating bits into a first function but among the multiple functional bits. (Solcia, [0066]; regarding, “The values of first selection bit 304E and second selection bit 304F may control the outputs of the first shift-register MUX 308, second shift-register MUX 310, and third shift-register MUX 312.”; [0074]; regarding, “In a first RAM write operation, the addressing information may come directly from addressing bits 304B. The D_RAM may comprise the RAM data. It may directly come from data bits 304A.”).
Regarding Claim 10, Solcia in view of Zorian in further view of Ling teach the system of claim 9 as referenced above. Solcia in view of Zorian in further view of Ling teach:
a first transmission port, coupled to the processor; and a second transmission port, coupled to the processor, (Ling, [0095]; regarding, “Each of the configuration elements… may comprise… a CMOS transmission gate… or any other device for making and/or breaking a connection between signal traces… The configuration elements may be… dynamically configurable (e.g., by control signals from a processor such as the CPU 104) during operation of a device (e.g., receiver 150)”);
wherein the processor receives multiple test data coming from an external device through the first transmission port, and provides the transmission protocol and the selected test data to the System on a Chip through the second transmission port. (Ling, [0119]; regarding, “a test signal may be input to the receiver. The test signal may, for example, be generated by a test station, and/or may be generated by a transmitter collocated with the receiver and looped-back into the receiver. The test signal may, for example, represent a corner case or worst-case scenario such that successful recovery of the data contained in the test signal may be a reliable indicator that the receiver will be able to successfully receive signals that it is required to receiver”; [0120]; regarding, “the test signal may be digitized and otherwise processed by an analog front end (e.g., AFE 102). In step 1114, the data contained in the digitized signal may be recovered by, for example, demodulating and decoding the digitized signal. In step 1116, the recovered data may be written to the memory.”).
Regarding Claim 11, Solcia in view of Zorian in further view of Ling teach the system of claim 9 as referenced above. Solcia in view of Zorian in further view of Ling teach:
the processor generates the transmission protocol based on selected test data, and the transmission protocol comprises a command, a specification signal of the selected test data, and a check signal of the selected test data. (Ling, [0120]; regarding, “the data may be read out of the memory…”; [0119]; regarding, “successful recovery of the data contained in the test signal may be a reliable indicator that the receiver will be able to successfully receive signals that it is required to receive (e.g., signals that meet specifications set forth in one or more standards).”)
Regarding Claim 12, Solcia in view of Zorian in further view of Ling teach the system of claim 11 as referenced above. Solcia in view of Zorian in further view of Ling teach:
wherein the specification signal represents a quantity of the selected test data and number of bits of the selected test data. (Ling, [0121]; regarding, “a performance metric (e.g., bit-error rate) may be measured for the error-corrected data and compared to a threshold.”; [0124]; regarding, “The order in which bits of the test data are written to the array of memory cells may be determined by the contents of the fault register. The test data may then be read from the array of memory cells.”).
Regarding Claim 13, Solcia in view of Zorian in further view of Ling teach the system of claim 11 as referenced above. Solcia in view of Zorian in further view of Ling teach:
Wherein the check signal comprises check information of the selected test data. (Ling, [0119]; regarding, “successful recovery of the data contained in the test signal may be a reliable indicator that the receiver will be able to successfully receive signals that it is required to receive (e.g., signals that meet specifications set forth in one or more standards).”).
Regarding Claim 18, Solcia in view of Zorian in further view of Ling teach the system of claim 14 as referenced above. Solcia in view of Zorian in further view of Ling teach:
receiving the test data coming from an external test device by the System on a Chip based on a transmission protocol, wherein the transmission protocol comprises a specification signal of the test data and a check signal of the test data. (Ling, [0119]; regarding, “a test signal may be input to the receiver. The test signal may, for example, be generated by a test station, and/or may be generated by a transmitter collocated with the receiver and looped-back into the receiver. The test signal may, for example, represent a corner case or worst-case scenario such that successful recovery of the data contained in the test signal may be a reliable indicator that the receiver will be able to successfully receive signals that it is required to receiver”; [0120]; regarding, “the test signal may be digitized and otherwise processed by an analog front end (e.g., AFE 102). In step 1114, the data contained in the digitized signal may be recovered by, for example, demodulating and decoding the digitized signal. In step 1116, the recovered data may be written to the memory.”; [0120]; regarding, “the data may be read out of the memory. In step 1120, one or more error correction algorithms (e.g., Viterbi and Reed-Solomon) may be applied to the read-out data.”; [0119]; regarding, “successful recovery of the data contained in the test signal may be a reliable indicator that the receiver will be able to successfully receive signals that it is required to receive (e.g., signals that meet specifications set forth in one or more standards).”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Solcia and Zorian with the teachings of Ling. Doing so can improve performance and or reduce power consumption (Ling, [0042]).
Regarding Claim 19, Solcia in view of Zorian in further view of Ling teach the system of claim 18 as referenced above. Solcia in view of Zorian in further view of Ling teach:
generating the transmission protocol by the test device based on the test data. (Ling, [0119]; regarding, “successful recovery of the data contained in the test signal may be a reliable indicator that the receiver will be able to successfully receive signals that it is required to receive (e.g., signals that meet specifications set forth in one or more standards).”).
Claim Rejections - 35 USC § 103
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Solcia et al (U.S. Publication No. 2023/0230650 A1), hereinafter referred to as Solcia, in view of Zorian et al. (U.S. Patent No. 7,415,640 B1), hereinafter referred to as Zorian, in further view of Yuan et al. (U.S. Publication No. 2011/0156742 A1), hereinafter referred to as Yuan.
Regarding Claim 8, Solcia in view of Zorian teach the system of claim 7 as referenced above. Solcia in view of Zorian fail to explicitly disclose but Yuan teaches:
a logic circuit, configured to receive the data of the first operating bit group in the test stage and perform an Exclusive OR logical operation on the data of the first operating bit group so as to generate the data of the first operating bit. ([0024]; regarding, “The exclusive OR gate 208 receives any one of the feedback signals in the first group of feedback signals and any one of the feedback signals in the second group of feedback signals generated by the first read compressing circuit 202 and the second read compressing circuit 203 and performs a logic operation to generate the output signal JS1.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Solcia and Zorian with the teachings of Yuan. Doing so can improve testing efficiency (Yuan, [0033]).
Response to Arguments
Applicant’s arguments filed 02/11/2026 have been fully considered.
Applicant argues Solcia and Zorian, alone or in combination, fail to disclose wherein when a bit value of a first setting bit among the multiple setting bits is a first value, the System on a Chip writes data coming from a first operating bit among the multiple operating bits into a first functional bit among the multiple functional bits (Remarks, Pg. 8). However, for further clarification Solcia teaches: ([0048]; regarding, “The shift register 302 may also comprise locations for RAM addressing bits 302E. The number of addressing bits may vary among embodiments. The shift register 302 may comprise a RAM R/W bit 302F, which may be referred to as a RAM function bit.”; [0074]; regarding, “In a first RAM write operation, the addressing information may come directly from addressing bits 304B. In the subsequent RAM writes, automatically increased by 1. The D_RAM may comprise the RAM data. It may directly come from data bits 304A.”).
Further, applicant argues that the cited references fail to explicitly disclose using an internal data source to write data into the function register (Remarks, Pg. 9). However, Solcia teaches: ([0038]; regarding, “A SoC 100 may comprise a test data input 102. The test data input 102 may be coupled with register block 104. The register block 104 may also be coupled with a test data output 106.”; [0040]; regarding, “The register block 104 may store data serially loaded from the test data input… The register block may provide data to the test data output 106 depending on the signals received from the test controller.”). In addition, applicant’s own specification discloses at paragraph [0005], “The processor receives multiple test data coming from outside, writes the multiple test data into the test data memory…”. Applicant’s arguments are not persuasive.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/M.D.G./Examiner, Art Unit 2113 /BRYCE P BONZO/Supervisory Patent Examiner, Art Unit 2113
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