DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 8, 16, 17, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gibbons (US PGPUB 2004/0036513).
Regarding claim 1, Figure 6 of Gibbons discloses a system comprising:
a reference divider circuit to divide a reference clock, the reference divider circuit comprising a reference divider output [12]
a phase-frequency detector circuit to detect a detected phase difference and a detected frequency difference based on the reference divider output and a feedback clock, the phase-frequency detector circuit comprising a divided reference clock input coupled to the reference divider output, a feedback clock input coupled to the feedback clock, and a detector output based on the detected phase and the detected frequency difference [14]
a loop filter circuit to filter the detector output, the loop filter circuit comprising a loop filter output [16]
a voltage controlled oscillator (VCO) circuit to generate a VCO clock output, the voltage controlled oscillator circuit comprising a VCO input coupled to the loop filter output, the VCO input to adjust at least one of a frequency and a phase of the VCO clock output [18]
a divider circuit to divide the VCO clock output, the divider circuit comprising a divider clock input coupled to the VCO clock output, a divider control input, and a divider clock output [400]
a pulse-width modulation (PWM) circuit, the pulse-width modulation circuit comprising a PWM clock input coupled to the divider clock output [22 and 24]
a period register to store a period value [22]
a duty cycle register to store a duty cycle value [24]
a pulse-width modulated output based on the period value and the duty cycle value, the pulse-width modulated output coupled to the divider control input [output of 24]
a counter rollover output to generate the feedback clock [output of 22]
Regarding claim 8, Figure 6 of Gibbons discloses wherein the divider circuit comprises a dual modulus prescaler divider for dividing the VCO clock output by one of a first divisor and a second divisor; the divider circuit divides the VCO clock output by the first divisor when the divider control input is high; and the divider circuit divides the VCO clock output by the second divisor when the divider control input is low [400].
Regarding claim 16, Figure 6 of Gibbons discloses a method comprising:
dividing a reference clock [12]
detecting a phase and frequency relationship between the divided reference clock and a feedback clock in a detector circuit [14]
filtering a detector output of the detector circuit in a loop filter circuit [16]
adjusting the phase or frequency of a voltage controlled oscillator based on a loop filter output of the loop filter circuit [18]
dividing an output oscillation signal of the voltage controlled oscillator in a dual modulus prescaler circuit [400]
clocking a pulse-width modulation circuit with a divided signal output of the dual modulus prescaler circuit [22 and 24]
selecting a divisor used by the dual modulus prescaler circuit based on an output signal of the pulse-width modulation circuit [output of 24]
generating the feedback clock based on a counter in the pulse-width modulation circuit [output of 22]
Regarding claim 17, Figure 6 of Gibbons discloses wherein generating the feedback clock based on the counter in the pulse-width modulation circuit comprises generating the feedback clock based on the counter corresponding to a period setting in the pulse-width modulation circuit [22].
Regarding claim 20, Figure 6 of Gibbons discloses changing the frequency of the voltage controlled oscillator by changing one or more of a period setting in the pulse-width modulation circuit and a duty cycle setting in the pulse-width modulation circuit [22 and 24].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-5, 10-12, 15, 18, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gibbons (US PGPUB 2004/0036513).
Regarding claim 2, Gibbons does not explicitly disclose wherein the reference divider circuit, the phase-frequency detector circuit, the loop filter circuit, and the pulse-width modulation circuit are implemented in one or more peripherals of a microcontroller; and the voltage controlled oscillator circuit and divider circuit are external to the microcontroller.
However, it would have been obvious to of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Gibbons by using a microcontroller with external circuitry as a matter of simple design-choice, since it was well-known in the art to use microcontrollers to implement circuits and to use external circuitry with.
Regarding claim 3, Gibbons, as applied to claim 2, does not explicitly disclose wherein the loop filter circuit comprises an operational amplifier.
However, it would have been obvious to of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Gibbons, as applied to claim 2, by using an operational amplifier for the loop filter as a matter of simple design-choice, since it was well-known in the art to use operational amplifiers as loop filters.
Regarding claim 4, Gibbons, as applied to claim 2, does not explicitly disclose wherein the phase-frequency detector circuit is implemented in one or more configurable logic cell peripherals of the microcontroller.
However, it would have been obvious to of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Gibbons, as applied to claim 2, by using configurable logic cells as a matter of simple design-choice, since it was well-known in the art to use configurable logic cells in a microcontroller.
Regarding claim 5, Gibbons, as applied to claim 4, does not explicitly disclose wherein the phase-frequency detector circuit and the loop filter circuit comprise: a first D flip-flop comprising a first data input coupled to logic one, a first clock input coupled to the divided reference clock input, a first reset input, and a first output; a second D flip-flop comprising a second data input coupled to logic one, a second clock input coupled to the feedback clock input, a second reset input, and a second output; a NAND gate comprising a third input coupled to the first output, a fourth input coupled to the second output, and a third output coupled to the first reset input and the second reset input; and an operational amplifier comprising an inverting input coupled to the first output and a feedback capacitor, a non-inverting input coupled to the second output, and a fourth output coupled to the loop filter output and the feedback capacitor.
However, it would have been obvious to of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Gibbons, as applied to claim 4, by using the above circuit configuration for the phase-frequency detector and the loop filter as a matter of simple design-choice, since these are well-known implementations of those circuits and it would have been a matter of simple substitution of one known element for another to obtain predictable results.
Regarding claim 10, Figure 6 of Gibbons discloses an apparatus, comprising:
a reference divider circuit to divide a reference clock, the reference divider circuit comprising a reference divider output [12]
a phase-frequency detector circuit to detect a detected phase difference and a detected frequency difference based on the reference divider output and a feedback clock, the phase-frequency detector circuit comprising a divided reference clock input coupled to the reference divider output, a feedback clock input coupled to the feedback clock, and a detector output based on the detected phase difference and the detected frequency difference [14]
a loop filter circuit to filter the detector output, the loop filter circuit comprising a loop filter output [16]
a voltage controlled oscillator (VCO) control output pin coupled to the loop filter output, the VCO control output pin to adjust one of a frequency and a phase of a VCO clock output of a voltage controlled oscillator circuit [18]
a VCO clock divider control output pin to select a divisor of a clock divider circuit [400]
a divided VCO clock input pin for coupling to an output of the clock divider circuit [400]
a pulse-width modulation (PWM) circuit, the pulse-width modulation circuit comprising a PWM clock input coupled to the divided VCO clock input pin [22 and 24]
a period register to store a period value [22]
a duty cycle register to store a duty cycle value [24]
a pulse-width modulated output based on the period value and the duty cycle value, the pulse-width modulated output coupled to the VCO clock divider control output pin [output of 24]
a counter rollover output to generate the feedback clock [output of 22]
Gibbons does not explicitly disclose an external voltage controlled oscillator circuit and an external clock divider circuit.
However, it would have been obvious to of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Gibbons by using external circuitry as a matter of simple design-choice, since it was well-known in the art to use to use external circuitry with a circuit to implement the circuit.
Regarding claim 11, Gibbons, as applied to claim 10, does not explicitly disclose one or more configurable logic cell peripherals to implement the phase-frequency detector circuit.
However, it would have been obvious to of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Gibbons, as applied to claim 10, by using configurable logic cells as a matter of simple design-choice, since it was well-known in the art to use configurable logic cells.
Regarding claim 12, Gibbons, as applied to claim 11, does not explicitly disclose wherein the phase-frequency detector circuit and the loop filter circuit comprise: a first D flip-flop comprising a first data input coupled to logic one, a first clock input coupled to the divided reference clock input, a first reset input, and a first output; a second D flip-flop comprising a second data input coupled to logic one, a second clock input coupled to the feedback clock input, a second reset input, and a second output; a NAND gate comprising a third input coupled to the first output, a fourth input coupled to the second output, and a third output coupled to the first reset input and the second reset input; and an operational amplifier comprising an inverting input coupled to the first output and a feedback capacitor, a non-inverting input coupled to the second output, and a fourth output coupled to the loop filter output and the feedback capacitor.
However, it would have been obvious to of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Gibbons, as applied to claim 11, by using the above circuit configuration for the phase-frequency detector and the loop filter as a matter of simple design-choice, since these are well-known implementations of those circuits and it would have been a matter of simple substitution of one known element for another to obtain predictable results.
Regarding claim 15, Figure 6 of Gibbons, as applied to claim 10, discloses a system comprising: the apparatus; the external clock divider circuit implemented as a dual modulus prescaler circuit external to the device, the dual modulus prescaler circuit comprising: a prescaler output coupled to the divided VCO clock input pin of the device; a prescaler control input coupled to the VCO clock divider control output pin of the device; and a prescaler clock input; and the external voltage controlled oscillator circuit is external to the device, the external voltage controlled oscillator circuit comprising: an oscillator input coupled to the VCO control output pin of the device; and an oscillator output coupled to the prescaler clock input [Figure 6; 400].
Regarding claim 18, Gibbons does not explicitly disclose wherein detecting the phase and frequency relationship between the divided reference clock and the feedback clock in the detector circuit comprises a microcontroller configuring a configurable logic cell peripheral of the microcontroller to detect the phase and frequency relationship between the divided reference clock and the feedback clock in the detector circuit.
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Gibbons, as applied to claim 16, by using configurable logic cells as a matter of simple design-choice, since it was well-known in the art to use configurable logic cells in a microcontroller.
Regarding claim 19, Gibbons, as applied to claim 18, does not explicitly disclose wherein: the microcontroller comprises the loop filter circuit; the loop filter circuit comprises an operational amplifier; and filtering the detector output of the detector circuit in the loop filter circuit comprises using the operational amplifier to filter the detector output of the detector circuit.
However, it would have been obvious to of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Gibbons, as applied to claim 18, by using an operational amplifier for the loop filter as a matter of simple design-choice, since it was well-known in the art to use operational amplifiers as loop filters.
Allowable Subject Matter
Claims 6, 7, 9, 13, 14, 21, and 22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/TOMI SKIBINSKI/Primary Examiner, Art Unit 2842