DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1 – 20 are pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 – 3, 5 – 7, 13, 15, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 10,289,588 (hereinafter Chu) in view of US Patent No. 10,255,215 (hereinafter Breakstone).
As per claim 1, Chu teaches a system for transferring data comprising: a plurality of signal traces (Chu; Figure 4 – connections between devices); a first connector (Chu; Figures 1 – 6 Item 102) in electrical connection with the plurality of signal traces; a second connector (Chu; Figures 1 – 3 Item 104) in electrical connection with a first portion of the plurality of signal traces (Chu; Figures 4 – 6 “X2”); a third connector (Chu; Figures 1 – 3 Item 104) in electrical connection with a second portion of the plurality of signals traces (Chu; Figures 4 – 6 “X2”); a switch (Chu; Figures 3 – 6 Item 106) adapted to receive at least one control signal from the first connector (Chu; Figures 4 – 6 “SEL”), to receive an input data channel from the first connector (Chu; Figures 4 – 6 Item 108), and to provide a plurality of output data channels (Chu; Figures 4 – 6 “X2”).
Chu does not teach a reset control module adapted to receive a first one of the plurality of output data channels from the switch and provide a first reset signal to the second connector and a second reset signal to the third connector.
However, Breakstone teaches a multi-disk storage system which includes a reset control module (Breakstone; Figure 6 Items 620 and 621) adapted to receive a first one of the plurality of output data channels (Breakstone; Figure 6 Item 633) from the switch (Breakstone; Figure 6 Item 612) and provide a first reset signal to the second connector and a second reset signal to the third connector (Breakstone; Col 19 Lines 1 – 28).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Chu to include the reset control module because doing so allows for correcting or eliminating errors or problems (Breakstone; Col 1 Lines 1 – 3).
As per claim 2, Chu also teaches wherein the first portion of the plurality of signal traces implements at least a first lane of a PCIe interface and wherein the second portion of the plurality of signal traces implements at least a second lane of the PCIe interface (Chu; Figures 4 – 6 Item 116).
As per claim 3, Breakstone also teaches wherein the first portion of the plurality of signal traces comprises a first four lanes (Breakstone; Figure 6 Item 641) of a PCIe interface and the second portion of the plurality of signal traces comprises a second four lanes of the PCIe interface (Breakstone; Figure 6 Item 641).
As per claim 5, Chu teaches wherein the value of the at least one control signal selects which of the plurality of output data channels is in electrical communication with the input data channel (Chu; Figures 4 – 6 “SEL,” Col 5 Lines 12 – 14).
As per claims 6 and 15, Chu also teaches wherein the switch is adapted to provide a second output data channel (Chu; Figures 4 – 6 “X2”) to the second connector and to provide a third output data channel (Chu; Figures 4 – 6 “X2”) to the third connector.
As per claim 7, Chu also teaches an EEPROM (Chu; Col 3 Lines 32 – 37) and wherein the switch is adapted to provide a fourth output data channel to the EEPROM.
As per claims 8 and 16, Breakstone also teaches wherein the reset control module is further adapted to provide a first power disable signal to the second connector and a second power disable signal to the third connector (Breakstone; Col 19 Lines 16 – 28).
As per claim 13, Chu teaches a system for transferring data comprising: a plurality of signal traces (Chu; Figure 4 – connections between devices); a first connector (Chu; Figures 1 – 6 Item 102) in electrical connection with a first lane of a PCIe interface and a second lane of the PCIe interface; a second connector (Chu; Figures 1 – 3 Item 104) in electrical connection with the first lane of the PCIe interface (Chu; Figures 4 – 6 “X2”); a third connector (Chu; Figures 1 – 3 Item 104) in electrical connection with the second lane of the PCIe interface (Chu; Figures 4 – 6 “X2”); a switch (Chu; Figures 3 – 6 Item 106) adapted to receive at least one control signal from the first connector (Chu; Figures 4 – 6 “SEL”), to receive an input data channel (Chu; Figures 4 – 6 Item 108), and to provide a plurality of output data channels (Chu; Figures 4 – 6 “X2”).
Chu does not teach a reset control module adapted to receive a first one of the plurality of output data channels from the switch and provide a first reset signal to the second connector and a second reset signal to the third connector.
However, Breakstone teaches a multi-disk storage system which includes a reset control module (Breakstone; Figure 6 Items 620 and 621) adapted to receive a first one of the plurality of output data channels (Breakstone; Figure 6 Item 633) from the switch (Breakstone; Figure 6 Item 612) and provide a first reset signal to the second connector and a second reset signal to the third connector (Breakstone; Col 19 Lines 1 – 28).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Chu to include the reset control module because doing so allows for correcting or eliminating errors or problems (Breakstone; Col 1 Lines 1 – 3).
Claim(s) 4 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 10,289,588 (hereinafter Chu) in view of US Patent No. 10,255,215 (hereinafter Breakstone), and further in view of US Patent No. 10,055,379 (hereinafter Shin).
As per claims 4 and 14, Chu in combination with Breakstone teaches the invention as described per claims 1 and 13 (see rejections of claims 1 and 13 above).
Chu in combination with Breakstone does not teach a buffer adapted to receive a reference clock signal from the first connector, to provide a first clock signal to the second connector, and to provide a second clock signal to the third connector.
However, Shin teaches a multi-disk storage system which includes a buffer (Shin; Figure 7 Item 710) adapted to receive a reference clock signal (Shin; Figure 7 “100MHz PCIe RefClk”) from the first connector (Shin; Figure 7 Item 310), to provide a first clock signal (Shin; Figure 7 “PCIe RefClk”) to the second connector (Shin; Figure 7 Item 401), and to provide a second clock signal (Shin; Figure 7 “100MHz PCIe RefClk”) to the third connector (Shin; Figure 7 Item 404).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Chu in combination with Breakstone to include the clock buffer because doing so allows for splitting the clock signal delivered from the host device (Shin; Col 7 Line 55 – Col 8 Line 3).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 10,289,588 (hereinafter Chu) in view of US Patent No. 10,255,215 (hereinafter Breakstone), and further in view of US Patent No. 10,765,038 (hereinafter Leigh).
As per claim 12, Chu in combination with Breakstone teaches the invention as described per claim 1 (see rejection of claim 1 above).
Chu in combination with Breakstone does not teach wherein the system complies with VPX standards.
However, Leigh teaches a disk storage system which complies with VPX standards (Leigh; Col 5 Lines 39 – 51).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Chu in combination with Breakstone to include the VPX standards because doing so allows for taking advantage of a convenient form factor (Leigh; Col 5 Lines 39 – 51).
Allowable Subject Matter
Claims 9 – 11 and 17 – 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 20 is allowable.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 9 – 11 and 17 – 19 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record fails to teach or suggest alone or in combination wherein the reset control module is adapted to perform a first reset sequence comprising the steps of transitioning the first power disable signal from high to low prior to transitioning the first reset signal from low to high, as required by dependent claims 9 and 17, in combination with the other claimed limitations (emphasis added). The prior art of record teaches resetting a device by sending a reset signal to a connector of the device, but does not teach the specific sequence of signal transitions required by dependent claims 9 and 17.
Claims 10, 11, 18, and 19 would also be allowable because of their dependence, either directly or indirectly, upon one of allowable dependent claims 9 or 17.
Claim 20 is allowable because the prior art of record fails to teach or suggest alone or in combination a reset control module adapted to receive a third output data channel from the switch, provide a first reset signal to the second connector, provide a second reset signal to the third connector, provide a first power disable signal to the second connector, provide a second power disable signal to the third connector, perform a first reset sequence comprising the steps of transitioning the first power disable signal from high to low prior to transitioning the first reset signal from low to high, perform a second reset sequence comprising the steps of transitioning the second power disable signal from high to low prior to transitioning the second reset signal from low to high, and to not transition the first power disable signal from high to low simultaneously with transitioning the second power disable signal from high to low, as required by independent claim 20, in combination with the other claimed limitations (emphasis added). The prior art of record teaches resetting a device by sending a reset signal from a reset control module to a connector of the device, but does not teach the specific sequence of signal transitions required by independent claim 20.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD B FRANKLIN whose telephone number is (571)272-0669. The examiner can normally be reached M-F 8:30am-5pm.
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/RICHARD B FRANKLIN/ Examiner, Art Unit 2181
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