Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Linderman (US Pat. No. 10521390), hereinafter referred to as Linderman.
As to claim 1, Linderman discloses a system comprising: a processor (processor core, 110, Fig. 1), a first peripheral and at least a second peripheral (raw input/output interface; network interface, 180; 190, Fig. 1), wherein each peripheral comprises a first transmission line for data transmission from the processor and a second transmission line for data transmission to the processor (shared data busses and control signals coupling processor core and raw/network I/O, 131; 150; 182; 192, Fig. 1), a first FIFO buffer connected to one of the first transmission line and the second transmission line of the first peripheral via a first FIFO controller (controllable hardware FIFO; FIFO controller, 200; 250, Fig. 2), a second FIFO buffer connected to the same first transmission line and second transmission line of the first peripheral as the first FIFO buffer via a second FIFO controller (additional controllable hardware FIFO in FIFO bank sharing busses, 200; 330, Fig. 3), a third FIFO buffer connected to one of the first transmission line and the second transmission line of the at least second peripheral via a third FIFO controller (hardware FIFO handling network or raw I/O via controller, 100; 250, Fig. 1; Fig. 2), a fourth FIFO buffer connected to the same first transmission line and second transmission line of the second peripheral as the third FIFO buffer via a fourth FIFO controller (multiple hardware FIFOs sharing common busses and control logic, 100; 300, Fig. 3), wherein at least one of the first FIFO controller and the second FIFO controller is connectable to at least one of the third FIFO controller and the fourth FIFO controller (FIFO controllers moving data among FIFOs via local bus, 250; 330, Fig. 3).
As to claim 2, Linderman discloses the system according to claim 1, wherein the first FIFO controller is connected to the third FIFO controller (FIFO controllers interconnected via local bus enabling data movement between FIFOs, 250; 330, Fig. 3).
As to claim 3, Linderman discloses the system according to claim 1, wherein the second FIFO controller is connected to the first FIFO controller (multiple FIFO controllers sharing local FIFO bus, 250; 330, Fig. 3) and wherein the third FIFO controller is connected to the fourth FIFO controller (FIFO controllers within FIFO bank sharing common interconnect, 250, Fig. 2; 330, Fig. 3).
As to claim 4, Linderman discloses the system according to claim 3, wherein the second FIFO controller is connectable to the third FIFO controller via the first FIFO controller (indirect FIFO-to-FIFO connectivity through intermediary FIFO controller over shared bus, 250, Fig. 2; 330, Fig. 3).
As to claim 5, Linderman discloses the system according to claim 3, wherein the fourth FIFO controller is connectable to the first FIFO controller via the third FIFO controller (controller chaining through FIFO bank interconnect, 250; 330, Fig. 3).
As to claim 6, Linderman discloses the system according to claim 1, wherein the second FIFO controller is connectable to the fourth FIFO controller (FIFO controllers operably coupled through FIFO bank local bus, 250; 330, Fig. 3).
As to claim 7, Linderman discloses the system according to claim 1, further comprising a fifth FIFO buffer connected to the other one of the first transmission line and the second transmission line of the first peripheral via a fifth FIFO controller (additional hardware FIFO coupled to I/O path, 100; 250, Fig. 1; Fig. 2), a sixth FIFO buffer connected to the same first transmission line and second transmission line of the first peripheral as the fifth FIFO buffer via a sixth FIFO controller (multiple FIFOs sharing peripheral interfaces, 100; 300, Fig. 3), a seventh FIFO buffer connected to the other one of the first transmission line and the second transmission line of the at least second peripheral via a seventh FIFO controller (hardware FIFO handling alternate I/O direction, 100; 250, Fig. 1), an eighth FIFO buffer connected to the same first transmission line and second transmission line of the second peripheral as the seventh FIFO buffer via an eighth FIFO controller (FIFO bank with multiple FIFOs per peripheral, 100; 300, Fig. 3), wherein at least one of the fifth FIFO controller and the sixth FIFO controller is connectable to at least one of the seventh FIFO controller and the eighth FIFO controller (FIFO controller interconnection via FIFO bank local bus, 250; 330, Fig. 3).
As to claim 8, Linderman discloses the system according to claim 7, wherein the fifth FIFO controller is connected to the seventh FIFO controller (FIFO controllers linked through shared FIFO bank interconnect, 250; 330, Fig. 3).
As to claim 9, Linderman discloses the system according to claim 7, wherein the sixth FIFO controller is connected to the fifth FIFO controller (controller interconnection within FIFO bank, 250; 330, Fig. 3) and wherein the seventh FIFO controller is connected to the eighth FIFO controller (multiple FIFO controllers sharing common bus, 250; 330, Fig. 3).
As to claim 10, Linderman discloses the system according to claim 7, wherein the sixth FIFO controller is connectable to the eighth FIFO controller (FIFO controllers operably coupled through FIFO bank local bus, 250; 330, Fig. 3).
As to claim 11, Linderman discloses the system according to claim 7, wherein at least one of the first FIFO controller and the second FIFO controller is connectable to at least one of the fourth FIFO controller and the sixth FIFO controller (cross-FIFO controller connectivity via shared FIFO bank interconnect, 250; 300; 330, Fig. 3; Fig. 4).
As to claim 12, Linderman discloses the system according to claim 1, wherein the processor is connected to any of the first FIFO buffer and the second FIFO buffer (processor core coupled to FIFO heads and tails via address and data buses, 110; 120; 140; 131; 150, Fig. 1) and wherein the processor is operable to dynamically adjust a buffer size of the first FIFO buffer and the second FIFO buffer (processor-configured FIFO controller expanding or contracting FIFO buffer capacity using additional buffer memory, 110; 250; 510, Fig. 5).
As to claim 13, Linderman discloses the system according to claim 11, wherein the total buffer size of the first FIFO buffer and the second FIFO buffer is constant and wherein the processor is operable to increase the buffer size (dynamic FIFO depth increase, 130; 510, Fig. 5) of one of the first FIFO buffer and the second FIFO buffer at the expense of the other one of the first FIFO buffer and the second FIFO buffer (reallocation of FIFO buffer capacity within FIFO bank under processor and FIFO controller control, 250; 300; 510, Fig. 3; Fig. 5).
As to claim 14, Linderman discloses a mobile electronic device comprising the system according to claim 1 (microprocessor computer system with processor core and memory-mapped FIFO architecture suitable for embedded/mobile deployment, 110; 100; 200, Fig. 1; Fig. 2).
As to claim 15, Linderman et al. discloses a method of sharing buffer resources among multiple FIFO buffers in the system according to claim 1, comprising the steps of transmitting a data stream between the processor and a first peripheral (data transfer between processor core and raw/network I/O via shared buses, 110; 180; 190; 131; 150, Fig. 1), buffering a first portion of the data stream in a first FIFO buffer of a first transmission line of the first peripheral (data enqueued into hardware FIFO buffer from peripheral interface, 100; 130; 140, Fig. 1), and buffering a second portion of the data stream in one of a third FIFO buffer and a fourth FIFO buffer of a first transmission line of another peripheral of the system (data distributed among multiple FIFOs in FIFO bank via controller-managed buffering, 300; 250; 330, Fig. 3).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lin et al. (Pub. No. 20210157759) A data transmission system includes a host, a universal serial bus (USB) interface adaptor, a first-in first-out (FIFO) interface adaptor, a plurality of functional circuits, and a bus bridge circuit.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUANITO C BORROMEO whose telephone number is (571)270-1720. The examiner can normally be reached on Monday - Friday 9 - 5.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Henry Tsai can be reached on 5712724176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.C.B/ Assistant Examiner, Art Unit 2184
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