DETAILED ACTION
1. This Office Action is responsive to claims filed for No. 18/924,166 on December 3, 2025. Please note Claims 1-8 and 10-20 are pending.
Notice of Pre-AIA or AIA Status
2. The present application is being examined under the pre-AIA first to invent provisions.
Continued Examination Under 37 CFR 1.114
3. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on December 3, 2025 has been entered.
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
4. Claims 1-8 and 10-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Takasugi et al. ( US 2018/0337682 A1 ).
Takasugi teaches in Claim 1:
A shift-register unit circuit ( Figure 5, [0055] discloses stages of a shift register ) comprising:
a first input sub-circuit configured to have a display-input terminal to receive a display-input signal, and to provide a display output-control signal to a first node ( Figure 5, [0057], [0062] discloses details of an input block BK2 which applies a carry signal C(n-3) and charges node Q1 (read as a first node). Please note Figure 3 which shows a timing within one frame and notably, this is performed during an image data writing period of one frame, as detailed in [0039]-[0041]. Note driving gate pulse Pn-1 may be output from an n-th stage and supplied to a corresponding n-th pixel line );
a second input sub-circuit configured to have a blank-input terminal to receive a blank-input signal for charging a blank-control node, and to provide a blank output-control signal to the first node ( Figure 5, [0057]-[0058] disclose a first sensing control block BK1a which receives a carry signal C(n-2) from terminal Ta, etc, as shown. [0043], [0058], etc a node M which is output to/charged with blanking information ), wherein the second input sub-circuit comprises an isolation sub-circuit, wherein the isolation sub-circuit is set between the first node and the blank-control node ( Figure 5, [0059] disclose details of the transistors which are part of BK1a, such as transistors T1b, T1c, etc, which assist in the blanking/reset process (read these transistors as an isolation sub-circuit). Figure 5, [0062]-[0064] disclose the activation of transistors T1a-T1c and how they allow the connection and disconnection between nodes M and Q1 (read as preventing interference by disconnection). They are controlled to allow for sensing of the current and subsequent determination of deterioration );
an output sub-circuit configured to output signal under control of the first node ( Figure 5, [0066]-[0068] disclose output blocks BK4 and BK4’ which can output SCOUT(n) and SCOUT(n+1), as shown. Please note these aspects include aspects of data writing period WP and blanking interval period BP, as shown as one cycle/frame period, in Figure 2, [0110]. Furthermore, [0058]-[0063], [0066], etc, disclose when the voltage of the node Q1 is boosted from voltage level L2 to L3, the output block BK4 outputs a scan shift clock/sensing gate pulse ); and
an anti-leak sub-circuit configured to provide a working voltage level to an anti-leak connection point ( Please note Applicant’s Figure 8, [0135] for details of anti-leak sub-circuit 801, including an anti-leak connection point OFF. Please compare this to Figure 7, [0125] which discloses the second input sub-circuit 410 overlapping some of the elements of the anti-leak sub-circuit. In that same sense, please note Takasugi teaches in Figure 5, [0071]-[0073] of transistors of input block BK2’ as well as transistors of input block BK2 (read these elements combined as an anti-leak sub-circuit) which outputs a voltage output to node Qh (read as an anti-leak connection point) ); and
a display-reset transistor ( Figure 5 shows a transistor, such as T3n );
wherein the anti-leak sub-circuit comprises a second anti-leak transistor connected to the isolation sub-circuit ( Figure 5, [0072] discloses transistor T3nb )
wherein a control terminal of the display-reset transistor in an n-th stage is connected to an output terminal of an (n+3)-th stage; a first terminal of the display-reset transistor is directly connected to a first signal line; and a second terminal of the display-reset transistor is directly connected to the anti-leak sub-circuit. ( Figure 5 shows T3n with a control terminal connected to C(n+3), a first terminal directly connected to node Q1 which is a/along a signal line (and therefore directly connected to this horizontal line, as shown) and a second terminal directly to the interpreted anti-leak sub-circuit (see through Qh line). It is also directly connected to T3nb, as shown (another element of the interpreted anti-leak sub-circuit. To clarify, note the direct connection of T3n to T3nb and as well as T1’, etc )
Takasugi teaches in Claim 2:
The shift-register unit circuit of claim 1, wherein a control terminal of the second anti-leak transistor is connected to a first clock signal line, a first terminal of the second anti-leak transistor is directly connected to the first node, and a second terminal of the third anti-leak transistor is directly connected to an anti-leak connection point. ( Figure 5 shows T3nb is connected to global start signal VSP, a first terminal is connected to Q1 and a second terminal is connected to Qh. As for a third anti-leak transistor, please note T3nc with a second terminal directly connected to Qh )
Takasugi teaches in Claim 3:
The shift-register unit circuit of claim 1, wherein the anti-leak sub-circuit further comprises a first anti-leak transistor ( Figure 5, [0060] discloses T3q );
wherein the first anti-leak transistor is configured to provide a high-voltage signal from a high-voltage signal line to the anti-leak connection point under control of the first node. ( Figure 5, [0069] discloses the power voltage GVDD from BK2 is transferred through BK2’, and notably through Q1. Please note T3q which provides GVDD to Qh )
Takasugi teaches in Claim 4:
The shift-register unit circuit of claim 3, wherein a first terminal of the first anti-leak transistor is connected to the high-voltage signal line, a second terminal of the first anti-leak transistor is connected to a second electrode of the second anti-leak transistor, and a control terminal of the first anti-leak transistor is connected to the first node. ( Figure 5 shows T3q, for example, has a first terminal connected to GVDD, a second terminal connected to T3nb and a control terminal of T3q is connected to Q1, for example )
Takasugi teaches in Claim 5:
The shift-register unit circuit of claim 1, wherein the anti-leak sub-circuit further comprises a third anti-leak transistor and a fourth anti-leak transistor ( Figure 5 shows T31a (read as a third anti-leak transistor) and T31b (read as a fourth anti-leak transistor) );
wherein the third anti-leak transistor and the fourth anti-leak transistor are connected in parallel. ( Figure 5 shows these transistors to be arranged in parallel )
Takasugi teaches in Claim 6:
The shift-register unit circuit of claim 5, wherein a first terminal of the third anti-leak transistor is connected to a high-voltage signal line, a second terminal of the third anti-leak transistor is connected to a first electrode of the fourth anti-leak transistor, and a second electrode of the fourth anti-leak transistor is connected to a second electrode of a first anti-leak transistor. ( Figure 5 shows a first terminal of T31a is connected to GVDD, a second terminal of T31a is connected to a first electrode of T3na, and a second electrode of T31b is connected to T3q )
Takasugi teaches in Claim 7:
The shift-register unit circuit of claim 1, further comprising:
a first control sub-circuit, configured to control a voltage level of a second node under control of the first node; and a second control sub-circuit configured to pull down voltage levels of the first node and the output terminal to turn-off voltage levels under control of the second node. ( Figure 5, [0057], [0064], etc disclose inverter block BK3 and BK3’ (read as a first and second control sub-circuit, respectively) which can reduce/deactivate/pull-down voltage levels of the node leading into BK4 and this is done in light of input from node Q1, as shown )
Takasugi teaches in Claim 8:
The shift-register unit circuit of claim 1, further comprising a display-reset sub-circuit configured to reset the first node under control of a display-reset signal provided from a reset-signal line after outputting the display-output signal in the display period. ( Figure 5, [0101], [0060], etc, disclose transistors T3n and T3na which are turned on in response to C(n+3), which resets/reduces node Q1 to a low potential power voltage GVSS2 )
Takasugi teaches in Claim 10:
The shift-register unit circuit of claim 1, wherein the anti-leak sub-circuit comprises a fourth anti-leak transistor;
wherein a control terminal of the fourth anti-leak transistor and the control terminal of the display-reset transistor are connected to the output terminal of the (n+3)-th stage; a first terminal of the fourth anti-leak transistor is directly connected to the second terminal of the display-reset transistor; and a second terminal of the fourth anti-leak transistor is directly connected to the first node. ( Figure 5 shows details of T3na including a control terminal connected to a carry signal, a first terminal connected to T3n and a second terminal connected to Q1. Furthermore, please note other transistors in BK2’ could also satisfy these limitation as well. Please note the interpretation of the fourth anti-leak transistor can differ from other claims as they are separately dependent on Claim 1 )
Takasugi teaches in Claim 11:
The shift-register unit circuit of claim 1, wherein the second terminal of the display-reset transistor is directly connected to a second terminal of a first anti-leak transistor. ( Figure 5 shows the connection between T3q and T3n for the respective second terminals )
Takasugi teaches in Claim 12:
The shift-register unit circuit of claim 1, wherein the second control sub-circuit comprises a first pull-down transistor ( Figure 5, [0074] discloses BK3’ includes many transistors, including T5q’, etc );
wherein a control terminal of the first pull-down transistor is connected to the second node; a first terminal of the first pull-down transistor is connected to the first signal line; and a second terminal of the first pull-down transistor is directly connected to the anti-leak sub-circuit. ( Figure 5 shows a control terminal of T5q’ is connected to the interpreted second node, leading to BK4/BK4’, a first terminal is connected to GVSS2 and a second terminal is connected to BK2’ )
Takasugi teaches in Claim 13:
The shift-register unit circuit of claim 12, wherein the anti-leak sub-circuit comprises a fifth anti-leak transistor ( As noted earlier, BK2’ has many transistors. Please note T31a’ for example );
wherein a control terminal of the fifth anti-leak transistor and the control terminal of the first pull-down transistor are connected to the second node ( Figure 5 shows the control terminal of T31a’ and T5q’ connected to the interpreted second node );
a first terminal of the fifth anti-leak transistor is directly connected to the second terminal of the first pull-down transistor ( Figure 5 shows T31a’ and T5q’ sharing a common terminal connection ); and
a second terminal of the fifth anti-leak transistor is directly connected to the first node. ( Figure 5 shows a terminal of T31a’ being directly connected to the interpreted first node Q1 )
Takasugi teaches in Claim 14:
The shift-register unit circuit of claim 12, wherein the second terminal of the first pull-down transistor is directly connected to a second terminal of a first anti-leak transistor. ( Figure 5 shows T31a’ and T3q sharing a common terminal connection )
Takasugi teaches in Claim 15:
The shift-register unit circuit of claim 1, wherein the output sub-circuit comprises a first output transistor, a second output transistor ( Figure 5 shows for BK4, please note T6cr (read as a first output transistor) and T6 (read as a second output transistor) );
wherein a control terminal of the first output transistor is connected to the first node; a first terminal of the first output transistor is connected to a fourth clock-signal line; a second terminal of the first output transistor is connected to a first output terminal ( Figure 5 shows for T6cr, a control terminal is connected to Q1, a first terminal is connected to CRCLK(n), and a second terminal is connected to C(n). Figure 1 shows C(n) as the output to the next shift stage );
a control terminal of the second output transistor is connected to the first node; a first terminal of the second output transistor is connected to a fifth clock-signal line; a second terminal of the second output transistor is connected to a second output terminal ( Figure 5 shows for T6, a control terminal is connected to Q1, a first terminal connected to SCLK(n), and a second terminal is connected to SCOUT(n) );
a signal output from the first output terminal is used as a shift driving signal for a gate driving circuit comprising the shift-register unit circuit ( Figures 1 and 5, [0066] show a carry signal C(n) is for the next stage, i.e. a shift driving signal ); and
a signal output from the second output terminal is used as a driving signal for a pixel driving circuit. ( Figures 1 and 5, [0066] show a SCOUT(n) output which is a driving signal to the pixels )
Takasugi teaches in Claim 16:
The shift-register unit circuit of claim 1, wherein the first control sub-circuit comprises a first control transistor and a second control transistor ( Figure 5, [0064] discloses details on the BK3 circuit, such as T5q and T5 (read as the first control transistor and second control transistor, respectively ) ), the first control transistor having a first terminal and a control terminal commonly connected to a first pull-down control-signal line ( Figure 5 shows the common connection between terminals of these two transistors, to a common line, as shown ), and a second terminal connected to the second node ( Figure 5 shows the second terminal of T5q connected to the interpreted second node ); the second control transistor having a first terminal connected to the second node ( Likewise with T5, T5q shows a connection to the interpreted second node ), a control terminal connected to the first node ( Figure 5 shows the terminal connection to the Q1 node ), and a second terminal connected to the first signal line providing a turn-off voltage level. ( Figure 5 shows the connection to GVSS2 )
Takasugi teaches in Claim 17:
The shift-register unit circuit of claim 1, wherein the second control sub-circuit comprises a first pull-down transistor and a second pull-down transistor ( Figure 5, [0075] discloses details on BK3’ including T5q’ and T5’ (read as a first pull-down transistor and second pull-down transistor, respectively) ), the first pull-down transistor having a first terminal connected to the first node, a control terminal connected to the second node, and a second terminal connected to the first signal line providing the turn-off voltage level ( Figure 5 shows the first terminal of T5q’ connected to the interpreted first node, a first terminal connected to the interpreted second node and another terminal connected to GVSS2 ); the second pull-down transistor having a first terminal connected to the output terminal, a control terminal connected to the second node, and a second terminal connected to the first signal line providing the turn-off voltage level. ( Figure 5 shows the first terminal connected to SCOUT(n+1), a control terminal connected to the interpreted second node and a second terminal connected tot GVSS2 )
Takasugi teaches in Claim 18:
A gate-driving circuit, comprising N stages of shift-register unit circuits cascaded in series, the N stages of shift-register unit circuits comprising the shift-register unit circuit of claim 1;
wherein a display-input terminal of an i-th stage of shift-register unit circuit is connected to an output terminal of a j-th stage of shift-register unit circuit, wherein N is an integer greater than 2, 1 <i ≤ N, 1 ≤ j< N, and j<I ( Figure 5 shows one stage of a plurality of stages, notably with an output of one stage being the input of the next stage. That subsequent input is connected to the reset and blanking aspects described above and timings which are shown in Figures 2 and 3. Please note the RESET signals in particular );
a display-input terminal of a first stage of the N stages of shift-register unit circuits is connected to a display-signal line; and a blank-input terminal of the first stage of the N stages of shift-register unit circuits is connected to a blank-signal line. ( All of these aspects have been detailed in the reasoning for Claim 1 with the stage shown in Figure 5. To clarify, please note BK2, BK1a and the respective input terminals to control the transistors within these circuits )
Takasugi teaches in Claim 19:
A display apparatus comprising the gate-driving circuit of claim 18 and a display panel connected to the gate-driving circuit. ( Figure 6, [0077] disclose the timings of gate lines, notably in a staggered/sequential layout as this is a cascading stage layout. Respectfully, there are clearly a plurality of gate lines, greater than 2 and each gate line is associated with a stage, so the last stage would correspond to the last gate line, i.e. no greater than )
Takasugi teaches in Claim 20:
A method of driving the shift-register unit circuit of claim 1, the method comprising:
in a display period of one cycle of displaying one frame of image ( Figure 2-5, [0039] disclose a driving method during writing period WP and blanking period BP ),
providing a display output-control signal to a first node in the shift-register unit circuit via a first input sub-circuit thereof in a first control period ( Figures 2 and 5, during writing period WP, the first part of the period, [0057], [0062], etc, disclose details of block BK2 which charges node Q1 );
outputting a display-output signal via an output sub-circuit thereof under control of the display output-control signal at the first node in a first output period ( Figure 5, [0066]-[0068] discloses the process and functionality of output blocks BK4 and BK4’ which can output to scan lines SCOUT(n) and SCOUT(n+1), as shown. This is reflected in Figures 2 and 3. This is applied to the pixel during the image displaying period );
in a blank period of the one cycle of displaying one frame of image, providing a blank output-control signal via a second input sub-circuit to the first node via a second input sub-circuit of shift-register unit circuit in a second control period ( Figure 5, [0057]-[0058] disclose a first sensing control block BK1a which receives a carry signal C(n-2) from terminal Ta, etc, as shown. [0043], [0058], etc a node M which is output to/charged with blanking information ); and
outputting a blank-output signal via the output sub-circuit under control of the first node in a second output period. ( Figure 5, [0066]-[0068] disclose output blocks BK4 and BK4’ which can output SCOUT(n) and SCOUT(n+1), as shown. Please note these aspects include aspects of data writing period WP and blanking interval period BP, as shown as one cycle/frame period, in Figure 2, [0110]. The two aspects are considered together as part of the output (read as a hybrid output signal). Furthermore, [0058]-[0063], [0066], etc, disclose when the voltage of the node Q1 is boosted from voltage level L2 to L3, the output block BK4 outputs a scan shift clock/sensing gate pulse )
Response to Arguments
5. Applicant’s arguments considered, but are respectfully moot/not persuasive.
Please note the updated rejection in light of the claim amendments. While Examiner appreciates Applicant’s claim amendments, the interpretations have changed, notably for “a signal line” which needs to be better defined as it is, respectfully, broad.
Due to the change in interpretation, Applicant’s arguments are moot at this time.
Conclusion
6. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DENNIS P JOSEPH whose telephone number is (571)270-1459. The examiner can normally be reached Monday - Friday 5:30 - 3:30 EST.
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/DENNIS P JOSEPH/Primary Examiner, Art Unit 2621