DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I, claims 1-15, in the reply filed on 03/04/2026 is acknowledged. The traversal i
s on the ground(s) that 1) the claims do not have separate utility and 2) the claimed would not be an undue burden of search for the examiner. This is not found persuasive because 1) and encoder resides in a transmitter and is electrically connected to a transmitter resin decoder resides in a receiver and is electric in connected to a receiver. They are entirely different devices. Furthermore, an encoding is not a simple invertible operation. There are a multitude of different ways to decode an encoded data based on different algorithms. 2) in response to the Applicant’s assertion that it would be an undue burden for the examiner to do a search, the Examiner disagrees since as pointed out above error correction encoded data is not invertible and so recovering a transmitted codeword can be recovered using a multitude of different algorithms. A search burden for the different algorithms would double or maybe triple the amount of work for the examiner.
The requirement is still deemed proper and is therefore made FINAL.
Claims 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 03/04/2026.
Claim Objections
Applicant is advised that should claim 13 be found allowable, claim 14 will be objected to under 37 CFR 1.75 as being a substantial duplicate thereof. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
For the purposes of advancing prosecution, the Examiner suggests canceling claim 14.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 8 is/are rejected under 35 U.S.C. 102(1) as being press anticipated by Telado; Jose et al. (US 20070081475 A1, hereafter referred to as Telado).
Summary of the Patent PublicationThis patent application focuses on high-speed data transmission over twisted-pair copper network cables (specifically aiming at 10 Gigabit Ethernet or 10GBASE-T standards).The primary problem it solves is achieving near-capacity data rates over bandwidth-limited, noisy copper lines without incurring astronomical power consumption or latency at the receiver. To achieve this, the invention pairs Low-Density Parity-Check (LDPC) coding (a highly efficient Forward Error Correction scheme) with Pulse Amplitude Modulation (PAM). By structuring the transceiver to map these encoded bits into discrete multi-level voltage amplitudes (such as PAM8 or a down-selected subset like DSQ128/PAM12), the system reduces the required signaling bandwidth, lowers the digital processing overhead, and maximizes the coding gain needed to clear strict Bit Error Rate (BER) targets over traditional network cables.
Rejection of claims 1 and 8:
Analysis of the Limitations & Document LocationsBelow is the mapping of how the publication teaches each limitation, alongside the standard locations where these elements are established in Telado disclosure.Limitation A: "Encoding a to-be-sent signal to obtain a low density parity check (LDPC) encoded signal"* How it is taught: The patent details a transmitter architecture where incoming digital data streams (e.g., from an XGMII interface) are framed and passed into an LDPC Encoder*. The encoder applies a matrix-based parity check to generate a block of encoded bits, introducing redundant parity data that allows the receiver to mathematically fix transmission errors (illustrated in Figure 3 in Telado, which explicitly map out the transmitter block diagram showing raw bits flowing directly into an "LDPC Encoder" block; note: Figure 7 in Telado teaches the general purpose computer comprising a processor and storage for implementing the design).Limitation B: *"Modulating the LDPC encoded signal into an eight pulse amplitude modulation (PAM8) symbol"** How it is taught: The Telado publication teaches a modulation mapping stage immediately following the LDPC encoder. To map bits to wire voltages, it evaluates multi-level PAM variations. For a 1-dimensional (1-D) physical lane, it teaches mapping groups of bits (Figure 3 and paragraph [0057] in Telado).Limitation C: *"Sending the PAM8 symbol to a receiver through a network cable"** How it is taught: The patent covers the physical media dependent (PMD) layer transmission. Once the digital symbols are mapped to PAM8 amplitudes, they are sent to a Digital-to-Analog Converter (DAC), passed through line drivers/transmit filters, and pushed out across physical copper pairs. The disclosure specifies that this environment consists of structured twisted-pair cabling (such as Category 6, Cat 6A, or Class F cabling) running full-duplex to a link-partner receiver (paragraphs [0004]-[0005] in Telado).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2, and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Telado; Jose et al. (US 20070081475 A1, hereafter referred to as Telado).
Rejection of claims 2 and 9:
Paragraphs [0055]-0058] in Telado teaches an LDPC encoded signal of 2048 bits obtained by performing LDPC encoding on data of 1723 bits (see Paragraph [0055]-[0058], teaching (2048, 1723) matrix constraints and code frame structures). Telado further teaches that the data payload is constructed using standard Ethernet 65-bit blocks (Paragraph [0055] specifically teaching blocks of 65 bits).Telado does not explicitly disclose that the 1723 bits comprise exactly 1 synchronization bit, 25 blocks, and 97 zero-valued bits."However, it would have been obvious to a person of ordinary skill in the art (PHOSITA) at the time of the invention to configure the 1723-bit data payload to include 1 synchronization bit, 25 blocks of 65 bits, and 97 zero-padded bits.Reasoning: It is well-known in the art of digital communications that data streams must be framed with synchronization markers (such as a 1-bit sync header) to allow a receiver to align incoming blocks. Furthermore, because physical data transmission frames (like Telado's 65-bit blocks) do not always divide perfectly into an arbitrary mathematical LDPC code payload (1723 bits), it is a routine and ubiquitous practice to maximize the number of full data blocks (25 \times 65 = 1625 bits) and fill the remaining payload gaps with dummy bits or zero-padding (97 bits of 0s) to satisfy the strict length requirements of the encoder matrix (KSR v. Teleflex, Predictable Results from Routine Mathematical/Design Choices: choosing 25 blocks and 97 zero-bits is merely an algebraic necessity to make standard 65-bit blocks fit into a 1723-bit frame. Changing the specific number of blocks or zero-padding bits represents a routine optimization of design parameters yielding entirely predictable results; furthermore, Given that an engineer must fill a 1723-bit space using 65-bit components, there are a strictly limited number of mathematical permutations available. Choosing 25 blocks and zero-padding the rest is one of a finite number of predictable options that an engineer would logically try).
Claim(s) 7 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Telado; Jose et al. (US 20070081475 A1, hereafter referred to as Telado) and Mezer; Amir et al. (US 20080069052 A1, hereafter referred to as Mezer).
Rejection of claims 7 and 15:
Paragraph [0024] in Mezer, in an analogous art, teaches the use of category 5 cable.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Telado with the teachings of Mezer by including use of category 5 cable. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, because one of ordinary skill in the art would have recognized that use of category 5 cable would have provided an interconnection means between transmitter and receiver (Paragraphs [0024] in Mezer).
Allowable Subject Matter
Claims 3-6 and 10-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: dependent claims 3-7 and 10-15 are also allowable since dependent claims inherit all the limitations of the claims from which they depend and any intervening claims. Therefore, the rejection of independent claims 1 and 8 identify the difference between that which is considered new and/or/novel independent claims 3-7 and 10-15.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
* US 2007/0081475 A1 (Telado et al. / Teranetics): primary document establishing that 10GBASE-T data payloads map across a (2048, 1723) LDPC code matrix. It introduces the precise hardware path of Figure 3, verifying that 65-bit encapsulation blocks form the underlying data structure, which are then projected via 128-DSQ down to 1-D PAM8 wire signals.* US 2008/0069052 A1 & US 2008/0320362 A1 (Tellado et al. / Teranetics): expand directly upon the control logic and structural framing mentioned in the '475 text. They provide the detailed hardware mechanisms for low-latency parity calculations and show how fractional bit-allocations map to the PAM levels. They are directed to manipulating the block layouts to achieve perfect (2048, 1723) alignment is an obvious, foundational design choice within the Teranetics architecture.
* US 2011/0249687 A1 (Aquantia Corp.): Focuses on standard 64B/65B and 64B/66B line coding structures over copper lines. It provides explicit teaching on how to manage the exact boundaries of the 65-bit blocks to prevent latency bottlenecks during the LDPC matrix construction—the exact real-world problem solved by adding custom synchronization bits and routine zero-padding.* US 9,001,872 B1 & US 9,363,039 B1 (Aquantia / Marvell Semiconductor): focus on digital signal processing (DSP) power management and clock alignment during the framing stage. They explicitly detail how the transceiver manipulates the bits *before* they hit the LDPC encoder to handle asymmetric line speeds and alien crosstalk, showing that adjusting payload layouts (such as changing block sizes or adding filler zero bits) is standard industry methodology.
* US 9,853,769 B1 & US 11,165,533 B1 (Marvell / Aquantia Solutions): These protect the modern hardware control engines (the types of computing structures hinted at in Telado’s Figure 7). They specialize in the exact mathematical optimization of error-correcting codes, detailing how a processor handles remaining payload space when data blocks do not divide evenly into an architectural standard.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH D TORRES whose telephone number is (571)272-3829. The examiner can normally be reached Monday-Friday 10-7 PT.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Albert Decady can be reached at 571-272-3819. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOSEPH D TORRES/Primary Examiner, Art Unit 2112
Prosecution Insights