Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/04/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings were received on 10/23/2024. These drawings are accepted.
Claim Objections
Claims 7, 13, and 20 are objected to because of the following informalities: In claim 7, last two lines recites a type “sew rate parameter”, should recite “slew rate parameter”. Similar typos and informalities recited in claim 13, last two lines and claim 20, last two lines. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Mekad et al. (USPGPUB No. 2020/0073840 A1, hereinafter referred to as Mekad) in view of Suarez et al. (US Pat No. 10649949 B1, hereinafter referred to as Suarez) and further in view of Binder et al. (USPGPUB No. 2012/0166582 A1, hereinafter referred to as Binder).
Referring to claim 1, Mekad discloses a system comprising {see Fig. 1, “example system 8” [0019]}:
a memory device {“data center includes a set of storage nodes 12”, see Fig. 1 [0021]};
and a memory sub-system controller {subsystem controller “[data processing units] DPUs 17, in accordance with… support emerging use cases … can dynamically unplug storage and/or compute connectivity… [via] controller-based systems”, see Fig. 1, [0027]} operatively coupled to the memory device {see Fig. 1, “have an external PCIe connectivity option”, [0027]} via an active input/output expander (AIOE) {see Fig. 2, “[serial] PCIe interfaces 146 are also coupled to respective I/O expanders 147” [0048]};
the AIOE to perform operations comprising:
receiving, from the memory sub-system controller {“dynamically unplug storage and/or compute connectivity operating in one mode (for example, EP) and change it to a mode that would need the controller to dynamically change over to RC mode … PCIe controller-based systems”, see Fig. 1, [0027]} via the first interface of the AIOE, a reference clock signal {see Fig. 1, “reset line paths” including PERST where “these techniques to meet interface link up [reference clock] timing requirements”, both cited in [0029], see Fig. 1};
Mekad does not appear to explicitly disclose receiving, from the memory device via the second interface of the AIOE, a signal corresponding to data associated with an input/output (I/O) command;
converting, based on the reference clock signal, the signal corresponding to the data to a first interface-compliant signal;
and sending, to the memory sub-system controller, via the first interface, the first interface-compliant signal;
However, Suarez discloses receiving, from the memory device via the second interface of the AIOE {second interface “parallel port 1”, right side “130” of “expander 100”, see Fig. 1b, “8-bit digital I/O ports 130” (Col 4, lines 14-18)}, a signal corresponding to data associated with an input/output (I/O) command {two types I/O compliant commands I2C (Col 6, lines 33-36, Table 2) and SPI (Col 7, lines 55-58, see Table 3)};
converting, based on the reference clock signal {reference clock signals “Switching speed SPI 10 30 MHz Switching speed I.sup.2C 100 500 kHz” depending on the direct of the given command from left side to right side and vice-versa (see Fig. 1B, Column 4, Table I, last two rows)}, the signal corresponding to the data {“reads the output serial data (miso)”, see Figs. 5 and 7, Col 5, line 38} to a first interface-compliant signal {see Fig. 1, “serial I/O signals may be from an I2C or SPI bus”, see Figs. 1a and 1b, Col 4, lines 10-12};
and sending, to the memory sub-system controller, via the first interface {“table2 summarizes the I2c read and write transactions” in register bank 750 as claimed (Col 6, lines 33-36 and table 2 into Column 7}, the first interface-compliant signal {see Fig. 1, “provide full mesh (any-to-any) interconnectivity” [0035]};
Mekad and Suarez are analogous because they are from the same field of endeavor, interfacing with I/O expanders.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Mekad/Binder and Suarez before him or her, to modify Mekad’s active input/output expander “expanders 147” incorporating Suarez’ “IO expander 100” and appropriate parallel circuitry “mux 680” (see Fig. 7).
The suggestion/motivation for doing so would have been to implement means of expanding I/O signals without moving to a larger microcontroller (Suarez Col 1 lines 64-67) for designing circuitry for a given application using microcontrollers (Suarez Col 1 lines 56-62).
Therefore, it would have been obvious to combine Suarez with Mekad to obtain the invention as specified in the instant claim(s).
Neither Mekad or Suarez appears to explicitly disclose wherein the AIOE is coupled to the memory sub-system controller via a first interface, and wherein the AIOE is coupled to the memory device via a second interface, the AIOE to perform operations.
However, Binder discloses wherein the AIOE is coupled to the memory sub-system controller via a first interface {“controller that incorporates the electronics that bridge the NAND memory components”, [0043]}, and wherein the AIOE is coupled to the memory device via a second interface, the AIOE to perform operations {AIOE “connect to 255 device port expanders” ([0049])via parallel interface “via the second bus, which may be a parallel bus” [0087]}.
Mekad/Suarez and Binder are analogous because they are from the same field of endeavor, interfacing with I/O expanders.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Mekad/Suarez and Binder before him or her, to modify Mekad/Suarez’s system (see Fig. 35) incorporating Binder’s “node 0 1008” (see Fig. 10, [0108]).
The suggestion/motivation for doing so would have been to implement an improved networking or storage security method and system that is simple, secured, cost-effective, faithful, reliable, easy to use or sanitize, has a minimum part count, minimum hardware, and/or uses existing and available components, protocols, programs and applications for providing better security and additional functionalities, and provides a better user experience (Binder [0058]).
Therefore, it would have been obvious to combine Binder with Mekad/Suarez to obtain the invention as specified in the instant claim(s).
As per claim 2, the rejection of claim 1 is incorporated and Binder discloses wherein the first interface is a serial interface {see Figs. 33-34, “Serial Attached SCSI” [0049], [0313]} and wherein the second interface is a parallel interface {see Figs. 1 and 2, “reorder the packets for delivery to the destinations” including the appropriate memory device as claimed [0036] last 3 lines}.
As per claim 3, the rejection of claim 1 is incorporated and Mekad discloses further comprising:
receiving, from the memory sub-system controller via the first interface of the AIOE {see Fig. 2, “PCIe interfaces 146 are also coupled to respective I/O expanders 147” [0048]}, the I/O command referencing a logical address {see Fig. 1, “logically establish one or more virtual fabrics” [0023]};
translating the logical address to a physical address referencing the memory device {see Fig. 1, “any of a number of parallel data paths within the data center 10” [0035]};
generating a second interface-compliant signal {see Fig. 1, “provide full mesh (any-to-any) interconnectivity” [0035]}; and sending, to the memory device, via the second interface, the second interface-compliant signal {see Figs. 1 and 2, “spray individual packets for packet flows” [0036]}.
As per claim 4, the rejection of claim 3 is incorporated and Binder discloses wherein the I/O command is received via a differential signal {“the PCIe peripheral is bidirectional [I/O command]. A [PCIe] lane is commonly composed of a transmit pair and a receive pair, each of differential lines”, see Figs. 13 and 24, [0048]}.
As per claim 5, the rejection of claim 1 is incorporated and Mekad discloses further comprising:
responsive to receiving {“coupled to respective I/O expanders 147” receiving I/O commands as appropriate [0048]}, from the memory sub-system controller, the I/O command, sending, to the memory sub-system controller, an indication that the I/O command has been successfully received {see Fig. 1, “use the communication control channels to notify each of DPUs” [0023]}.
As per claim 6, the rejection of claim 1 is incorporated and Mekad discloses further comprising:
responsive to receiving a notification {see Fig. 1, “use the communication control channels to notify each of DPUs” [0023]} from a controller of the memory device indicating that the I/O command has been successfully performed {see Fig. 1, “facilitate communication of data across switch fabric 14” [0037]}, sending an indication to the memory sub-system controller that the I/O command has been successful performed {see Fig. 6, “send data from configuration register 156 to programmable I/O expander 170 via interface 164 to cause programmable I/O expander 170 to issue a reset signal” [0086]}.
As per claim 7, the rejection of claim 1 is incorporated and Suarez discloses further comprising:
improving a quality parameter {“provides operating specifications for a … expander 100”, see Figs. 1a and 1b, Col 4, lines 28-30} of the first interface-compliant signal, wherein the quality parameter comprises at least one of {Examiner’s interpretation: recitation “at least one of” in conjunction with “or” treats this dependent as a Markush claim, thus the reference needs only disclose one member of the group in order to address the claim.} a jitter parameter or sew rate parameter {“Output Slew rate… V/us”, Table 1, Col 4, lines 43-45} of the first interface-compliant signal {“serial I/O signals… converted to general purpose digital I/O signals”, see Figs. 1a and 1b, Col 4, lines 8-11}.
Referring to claims 8-13 are method claim of claims reciting claim functionality corresponding to the system claim of claims 1-7, respectively, thereby rejected under the same rationale as claims 1-7 recited above.
Referring to claims 14-20 are non-transitory computer-readable storage medium claims reciting claim functionality corresponding to the system claim of claims 1-7, respectively, thereby rejected under the same rationale as claims 1-7 recited above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following references are applicable as 103 art teaching at least one limitation recited in claim 1’s “memory device”, “data associated with an I/O command”, or “memory subsystem controller”: US 20220365889 A1, US 11194750 B2, US 20200073840 A1, US 10019402 B2, and US 7793031.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A. BARTELS whose telephone number is (571)270-3182. The examiner can normally be reached on Monday-Friday 9:00a-5:30pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dr. Henry Tsai can be reached on 571-272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C. B./
Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184