DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claim 6 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Specie, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 01/08/2026.
Applicant’s election without traverse of Specie V (Figure 6A) in the reply filed on 01/08/2026 is acknowledged.
Applicant indicated that claims 2-5 and 7-21 are readable on the elected Specie V (Figure 6A).
Specification
The disclosure is objected to because of the following informalities: in paragraph [0001] of the specification, the issued patent information for Application 16/946,090 should be provided. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 12-14 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
For claim 12, the recitation “the amplifier of claim 1” causes the claim to be indefinite because claim 1 has been canceled, so claim 12 cannot be depended on a canceled claim 1. Clarification and/or Appropriate correction is required.
For claim 13, the recitation “the voltage clamp” on line 1 is indefinite because it lacks clear antecedent basis since “a voltage clamp” is first recited in claim 12 and not recited in claim 11. Clarification and/or Appropriate correction is required.
Claim 14 is indefinite because it depends on claim 13.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 2-5, 7-11 and 15-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Brantley et al. (US 2015/0028949).
For claims 2 and 15, Figure 3A of Brantley et al. teaches an amplifier comprising: a pair of input terminals (Vin+, Vin-) configured to receive a differential input signal (Vin+, Vin-), wherein the pair of input terminals (Vin+, Vin-) includes a first input terminal (Vin+) and a second input terminal (Vin-); a differential pair of input transistors (310, 312) configured to amplify the differential input signal (Vin+, Vin-), wherein the differential pair of input transistors (310, 312) includes a first input transistor (310) and a second input transistor (312) connected at a tail node (junction connections of transistors 310 and 312 with voltage source 301 and current source 300); a first protection transistor (306) in series between the first input terminal (Vin+) and a control input (gate of 310) of the first input transistor (310); and a bias circuit (302, 301, 304) configured to control a bias voltage (voltage to gate of 306 and gate of 308) of a control input (gate of 306) of the first protection transistor (306), wherein the bias voltage (voltage to gate of 306 and gate of 308) is configured to change based on at least one of a voltage of the control input (gate of 310) of the first input transistor (310) or a voltage of a control input (gate of 312) of the second input transistor (312).
For claims 3 and 16, Figure 3A of Brantley et al. teaches wherein the first input transistor (310) and the second input transistor (312) are p-type metal-oxide-semiconductor (PMOS) transistors (PMOS 310 and PMOS 312), the bias circuit (302, 301, 304) configured to control the bias voltage (voltage to gate of 306 and gate of 308) based on the lesser of the voltage of the control input of the first input transistor (310) or the voltage of the control input of the second input transistor (312).
For claims 4 and 17, Figure 3A of Brantley et al. teaches wherein the bias circuit (302, 301, 304) includes an input selector (302, 304) having a first input (anode of 302) that receives the voltage of the control input (gate of 310) of the first input transistor (310) and a second input (anode of 304) that receives the voltage of the control input (gate of 312) of the second input transistor (312), the bias circuit (302, 301, 304) further including a voltage source (301) connected between an output (cathodes of 302 and 304) of the input selector (302, 304) and the control input (gate) of the first protection transistor (306).
For claims 5 and 18, Figure 3A of Brantley et al. teaches wherein the bias circuit (302, 301, 304) includes a common-bias driver (302, 304) having a first input (anode of 302) that receives the voltage of the control input (gate of 310) of the first input transistor (310), a second input (anode of 304) that receives the voltage of the control input (gate of 312) of the second input transistor (312), and an output (cathodes of 304 and 304) that controls the bias voltage (voltage to gate of 306 and gate of 308).
For claims 7 and 19, it is seen in the operation of the amplifier in Figure 3A of Brantley et al. that wherein an impedance of the first protection transistor (306) is configured to increase in response to an excursion of the first input terminal (Vin+) or the second input terminal (Vin-) (note that this is because the connection structures of the first protection transistor 306 connected to the input transistor 310 in the amplifier is substantially the same as the amplifier of the invention, so their claim properties/functions are presumed to be the same, see MPEP 2112.01).
For claim 8, Figure 3A of Brantley et al. teaches a second protection transistor (308) in series between the second input terminal (Vin-) and the control input (gate of 312) of the second input transistor (312).
For claim 9, Figure 3A of Brantley et al. teaches wherein the control input (gate of 306) of the first protection transistor (306) and a control input (gate of 308) of the second protection transistor (308) are both biased by the bias voltage (voltage to gate of 306 and gate of 308) from the bias circuit (302, 301, 304).
For claim 10, Figure 3A of Brantley et al. teaches wherein the first input transistor (310) and the second input transistor (312) are p-type metal-oxide-semiconductor (PMOS) transistors (PMOS transistors 310 and 312), and the first protection transistor (306) and the second protection transistor (308) are n-type metal-oxide- semiconductor (NMOS) transistors (NMOS transistors 306 and 308).
For claim 11, Figure 3A of Brantley et al. teaches comprising a current source (300) connected to the tail node (junction connections of transistors 310 and 312 with voltage source 301 and current source 300) and configured to generate a bias current (300).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 12-14 and 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over Brantley et al. (US 2015/0028949) in view of Ying et al. (CN-108880488-A).
For claims 12 and 20, Figure 3A of Brantley et al. teaches an amplifier which includes all the limitations of these claims as discussed in the 102 rejection. Figure 3A of Brantley et al. does not teach the amplifier including a voltage clamp configured to provide clamping between the control input of the first input transistor and a control input of the second input transistor. However, Figure 2 of Ying et al. teaches an amplifier including a voltage clamp (the 2 diodes connected PMOS transistors) configured to provide clamping between the control input (V1) of the first input transistor (the PMOS input transistor that has its gate connected to receive V1) and a control input (V2) of the second input transistor (the PMOS input transistor that has its gate connected to receive V2). Therefore, it would have been obvious to one having ordinary skilled in the art at the time before the invention was effectively filed to modify the amplifier in Figure 3A of Brantley et al. by including the voltage clamp (the 2 diodes connected PMOS transistors), as taught in Figure 2 of Ying et al., configured to provide clamping between the control input (gate of 310) of the first input transistor (310) and a control input (gate of 312) of the second input transistor (312) for the purpose of counteract the input transistors process change which makes the input transistors of the leakage is not sensitive with the technology (see abstract, and the description of Figure 2 in the 2nd paragraph of page 17). Thus, this combination/modification meets all the limitations of claim 12. For claims 13-14 and 20-21, the combination/modification as discussed teaches wherein the voltage clamp (the 2 diodes connected PMOS transistors in Figure 2 of Ying et al. that is incorporated into Figure 3A of Brantley et al.) comprises a first diode (the bottom one of the 2 diodes connected PMOS transistors in Figure 2 of Ying et al.) having an anode connected to the control input of the first input transistor (gate of transistor 310 in Figure 3A of Brantley et al. in the modification/combination) and a cathode connected to the control input of the second input transistor (gate of transistor 312 in Figure 3A of Brantley et al. in the modification/combination), wherein the first diode (the bottom one of the 2 diodes connected PMOS transistors in Figure 2 of Ying et al.) comprises one of a p-n junction diode, a Zener diode, or a Schottky diode (the 2 diodes connected PMOS transistors in Figure 2 of Ying et al. are p-n junction diodes).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directly to Examiner Long Nguyen whose telephone number is (571) 272-1753. The Examiner can normally be reached on Monday to Friday from 8:30am to 5:00pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lincoln Donovan, can be reached at (571) 272-1988. The fax number for this group is (571) 273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
/Long Nguyen/
Primary Examiner
Art Unit 2842