DETAILED ACTION
This is in response to the request for continued examination filed on 9/28/2026.
Status of Claims
Claims 1 – 10 are pending, of which claim 1 is in independent form.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 9/28/2026 has been entered.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 6, and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Kannan et al., ‘Decoupling Dynamic Information Flow Tracking with a Dedicated Coprocessor’ (hereinafter referred to as Kannan) (from Applicant’s IDS) in view of Wahab et al., ‘ARMHEx: A hardware extension for DIFT on ARM-based SOCs’ (hereinafter referred to as Wahab).
Referring to claim 1, Kannan discloses “A method of processing instructions” (Figure 1 and section 2.1 instruction execution and DIFT checks), “comprising: (a) in an application processing domain, by an application processor” (Introduction, specifically top of page 106 teaches main processor running an 'application'): “implementing a first instruction set architecture” (section 2.1 ISA instructions and page 110 left column, paragraph beginning with ‘To address these challenges’ describes the ISA); “receiving instructions comprising operand information indicative of one or more operands, and operation information indicative of an operation to be performed on the one or more operands, the instructions being formatted in accordance with the first instruction set architecture” (section 2.1 instructions with operands, an 'add' instruction. Also section 2.1 operations such as move, arithmetic, and logical operations); “and providing, to a metadata processing domain, the instructions in an instruction stream” (Figure 2 main core sending instruction tuples to coprocessor); “and (b) in the metadata processing domain: by a tag processing unit” (Figure 2 coprocessor dealing with tags including a tag check logic) “comprising at least one decode” module (Figure 2 “security decode”):
“extracting” “the operation information from an instruction of the instructions” (Figure 2 and section 3.2 ‘given an executed instruction by the main core, the first stage (of the coprocessor architecture) decodes it into primitive operations); “obtaining, using the extracted operand information, an input metadata tag associated with one or more of the operands of the instruction” (section 3.2 tags for the architectural registers, tags for the instruction word); “and determining, in accordance with one or more policies being enforced and based on the operation information and the input metadata tag, whether the instruction is allowed” (section 3.2 check rules, security policies for the tags for the architectural registers and tags for the instruction word).
Kannan does not appear to explicitly disclose “a tag processing unit comprising at least one decode table” and “extracting, using the at least one decode table, the operand information and the operation information.” However, Wahab discloses another DIFT coprocessor method (Fig. 1) including “a tag processing unit comprising at least one decode table” and “extracting, using the at least one decode table, the operand information and the operation information” (Fig.4 and its description teach a memory section with "information on how to decode the instructions" (considered equivalent to 'decode table'). Also, Table VI shows PFT Decoder with 105 Slice LUTs. Introduction and discussion of Table IV teaches “tag propagation” for operands. Also section V. B. teaches ARMHEx operations including looking for tags of source operands and computing tag of destination operand).
Kannan and Wahab are analogous art because they are from the same field of endeavor, which is dynamic tracking of instruction execution with a coprocessor.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Kannan and Wahab before him or her, to modify the teachings of Kannan to include the teachings of Wahab so that the tag processing unit comprises a decode table for extracting operand information and operation information.
The motivation for doing so would have been to provide for a fast decoding means, since LUTs are known to have high throughput.
Therefore, it would have been obvious to combine Wahab with Kannan to obtain the invention as specified in the instant claim.
As per claim 3, Kannan teaches “determining, by the tag processing unit” “that the instructions are formatted in accordance with the first instruction set architecture” (Figure 2 coprocessor dealing with tags including a tag check logic. Also, section 2.1 ISA instructions and page 110 left column, paragraph beginning with ‘To address these challenges’ describes the ISA). It is inherent in Kannan that only instructions that are “formatted in accordance with the first instruction set architecture” would be properly decoded and executed. This is a function of an ISA.
Kannan does not appear to explicitly disclose “determining, by the tag processing unit based on the at least one decode table, that the instructions are formatted in accordance with the first instruction set architecture.”
However, as above, Wahab discloses another DIFT coprocessor method (Fig. 1) including a tag processing unit comprising at least one decode table and extracting, using the at least one decode table, the operand information and the operation information (Fig.4 and its description teach a memory section with "information on how to decode the instructions" (considered equivalent to 'decode table'). Also, Table VI shows PFT Decoder with 105 Slice LUTs. Introduction and discussion of Table IV teaches “tag propagation” for operands. Also section V. B. teaches ARMHEx operations including looking for tags of source operands and computing tag of destination operand).
It would have been obvious to one of ordinary skill in the art at the time of Applicant’s filing to combine Wahab with Kannan so that a method includes “determining, by the tag processing unit (as in Kannan) based on the at least one decode table (as in Wahab), that the instructions are formatted in accordance with the first instruction set architecture (as in Kannan).”
Kannan and Wahab are analogous art because they are from the same field of endeavor, which is dynamic tracking of instruction execution with a coprocessor.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Kannan and Wahab before him or her, to modify the teachings of Kannan to include the teachings of Wahab so that the tag processing unit comprises a decode table for extracting operand information and operation information.
The motivation for doing so would have been to provide for a fast decoding means, since LUTs are known to have high throughput.
Therefore, it would have been obvious to combine Wahab with Kannan to obtain the invention as specified in the instant claim.
As per claims 6 – 7, Kannan discloses “a buffered interface configured to store the instructions from the application processor when the tag processing unit is stalled, and to provide stored instructions for use by the tag processing unit when the instruction stream is stalled” and “the buffered interface comprises a first-in-first-out (FIFO) component” (page 110 ‘Decoupling’ section teaches stalling and an extra queue for mismatches in processing rate of the processor and coprocessor. Kannan’s queue does not change the order, thus it follows FIFO).
Kannan shows the extra queue in Figure 2 as being external to both the main core and the DIFT coprocessor. However, as learned from In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950) shifting the position of an element is unpatentable if the shifting would not have modified the operation of the device. In this case, including the queue as part of the DIFT coprocessor does not modify the operation of the system. Thus it would have been obvious to one of ordinary skill in the art to modify Kannan so that “the tag processing unit further comprises a buffered interface.”
Claims 2 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Kannan in view of Wahab, as applied to claims above, further in view of Chiricescu et al., U.S. Patent Application 2016/0140363 (hereinafter referred to as Chiricescu).
As per claim 2, Kannan and Wahab teach “the tag processing unit comprises at least one look-up table” (Kannan Figure 2 coprocessor dealing with tags including a tag check logic. Wahab Fig.4 and its description teach a memory section with "information on how to decode the instructions" (considered equivalent to 'decode table'). Also, Wahab Table VI shows PFT Decoder with 105 Slice LUTs).
Neither Kannan nor Wahab appears to explicitly disclose the tag processing unit “configured to determine, based on the instructions, instruction care bit information indicative of one or more care bits, and operation group information indicative of an operation group.”
However, Chiricescu discloses another metadata processing method including a unit “configured to determine, based on the instructions, instruction care bit information indicative of one or more care bits, and operation group information indicative of an operation group” ([0092] opgroups and don’t care).
Kannan, Wahab, and Chiricescu are analogous art because they are from the same field of endeavor, which is metadata processing with a tag unit.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Kannan, Wahab, and Chiricescu before him or her, to modify the teachings of Kannan and Wahab to include the teachings of Chiricescu so that the tag processing unit comprises at least one look-up table configured to determine, based on the instructions, instruction care bit information indicative of one or more care bits, and operation group information indicative of an operation group.
The motivation for doing so would have been to provide a means for defining similar rules for similar opcodes, and reducing the number of rules needed (as stated by Chiricescu at [0092]).
Therefore, it would have been obvious to combine Chiricescu with Kannan and Wahab to obtain the invention as specified in the instant claim.
As per claim 4, Kannan discloses “the instructions are formatted in accordance with the first instruction set architecture” (section 2.1 ISA instructions and page 110 left column, paragraph beginning with ‘To address these challenges’ describes the ISA).
Neither Kannan nor Wahab appears to explicitly disclose “a determination that the instructions are formatted in accordance with the first instruction set architecture is further based on the instruction care bit information indicative of the one or more care bits and the operation group information indicative of an operation group.”
However, Chiricescu discloses “the instruction care bit information indicative of the one or more care bits and the operation group information indicative of an operation group” ([0092] opgroups and don’t care).
It would have been obvious to one of ordinary skill in the art at the time of Applicant’s filing to combine the opgroups and don’t cares of Chiricescu with Kannan/Wahab so that a determination that the instructions are formatted in accordance with the first instruction set architecture is further based on the instruction care bit information indicative of the one or more care bits and the operation group information indicative of an operation group.
Kannan, Wahab, and Chiricescu are analogous art because they are from the same field of endeavor, which is metadata processing with a tag unit.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Kannan, Wahab, and Chiricescu before him or her, to modify the teachings of Kannan and Wahab to include the teachings of Chiricescu so that the tag processing unit comprises at least one look-up table configured to determine, based on the instructions, instruction care bit information indicative of one or more care bits, and operation group information indicative of an operation group.
The motivation for doing so would have been to provide a means for defining similar rules for similar opcodes, and reducing the number of rules needed (as stated by Chiricescu at [0092]).
Therefore, it would have been obvious to combine Chiricescu with Kannan and Wahab to obtain the invention as specified in the instant claim.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Kannan in view of Wahab, as applied to claims above, further in view of Lee et al., U.S. Patent Application 2015/0058997 (hereinafter referred to as Lee ‘997).
As per claim 8, neither Kannan nor Wahab appears to explicitly disclose “the tag processing unit further comprises a tag map table (TMT) configured to convert one or both of a physical instruction address and a data memory page address, into one or both of (i) a corresponding associated tag addresses and (ii) directly into a tag.”
However, Lee ‘997 discloses “the tag processing unit further comprises a tag map table (TMT) configured to convert one or both of a physical instruction address and a data memory page address, into one or both of (i) a corresponding associated tag addresses and (ii) directly into a tag” ([0081] if access is validated, then it initiates the generation of appropriate hardware tags for the data file, [0082] if the access is validated, the file management module 314 requests the hypervisor 316 to create an SDC 318 for the data file with the corresponding hardware tags, and [0103] tags and table lookups).
Kannan, Wahab, and Lee '997 are analogous art because they are from the same field of endeavor, which is improvements to securely processing instructions.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Kannan, Wahab, and Lee '997 before him or her, to modify the teachings of Kannan and Wahab to include the teachings of Lee '997 so that a tag map table (TMT) is configured to convert one or both of a physical instruction address and a data memory page address, into one or both of (i) a corresponding associated tag addresses and (ii) directly into a tag.
The motivation for doing so would have been to provide a means for storing and checking tags before performing operations that may lead to security breaches (as described by Lee '997 at [0018]).
Therefore, it would have been obvious to combine Lee '997 with Kannan and Wahab to obtain the invention as specified in the instant claim.
Allowable Subject Matter
Claims 5, 9, and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claims 1 – 10 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Taylor et al., ‘Extended Abstract: A Hardware-Assisted Data Hiding Based Approach in Building High Performance Secure Execution Systems’ teaches secure execution systems, data for security and trust purposes, using a decoder to extract information and decode the instruction "(for example, by checking a look-up table)."
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN G SNYDER whose telephone number is (571)270-1971. The examiner can normally be reached on M-F 8:00am-4:30pm (flexible).
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/STEVEN G SNYDER/Primary Examiner, Art Unit 2184
