DETAILED ACTION
This is in response to communication filed on 3/16/2026.
Status of Claims
Claims 1 – 10 are pending, of which claim 1 is in independent form.
Claim Rejections - 35 USC § 112
In light of applicant’s amendments to the claims, the examiner withdraws the previous rejection to the claims.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 4 are rejected under 35 U.S.C. 103 as being unpatentable over Chiricescu et al., U.S. Patent Application 2016/0140363 (hereinafter referred to as Chiricescu) (from Applicant’s IDS) in view of Lee et al., U.S. Patent Application 2011/0276785 (hereinafter referred to as Lee).
Referring to claim 1, Chiricescu discloses “A method of processing instructions, comprising: (a) in an application processing domain, by an application processor: implementing a first instruction set architecture” ([0015] a conventional processor (e.g. RISC-CPU, GPU, Vector processor, etc.). [0062] Reduced Instruction Set Computer (RISC) processor with a pipeline including fetch, decode, execute, memory, and writeback according to instructions); “receiving instructions comprising operand information indicative of one or more operands, and operation information indicative of an operation to be performed on the one or more operands, the instructions being formatted in accordance with the first instruction set architecture” ([0062] Reduced Instruction Set Computer (RISC) processor with a pipeline including fetch, [0067] current instruction, current opcode, input operands, [0076] opcode, [0092] opcode groups); and “(b) in the metadata processing domain: by a tag processing unit” ([0015] adding a metadata processing unit (the PUMP) to the conventional processor) “extract the operand information and the operation information from the instructions” ([0067] "if the current opcode is opcode, ..., the tags on its input operands (if any) are OP1 and OP2").
Chiricescu does not appear to explicitly disclose “providing, to a metadata processing domain, the instructions in an instruction stream” and “a tag processing unit comprising at least one decode table” for “extract[ing] the operand information and the operation information from the instructions.”
However, Lee discloses “providing” “the instructions in an instruction stream” (Figs. 1 and 3 along with [0009] receiving bytecodes in a bytecode buffer 11) and a “processing unit comprising at least one decode table” for “extract[ing] the operand information and the operation information from the instructions” (Figs. 1 and 3 along with [0009] bytecode conversion acceleration device 10 includes decoding table 13/131 and buffer 11/110. [0020] and [0047] The decoding table 131 stores a bytecode length (BL) including an operation code and the number of operands).
Chiricescu and Lee are analogous art because they are from the same field of endeavor, which is improvements to processing instructions. Chiricescu teaches security policies for executing code (Abstract) and describes performance and speed based on memory traffic ([0113]). Lee teaches an accelerator for executing instructions that will improve execution speed ([0006], [0015]).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Chiricescu and Lee before him or her, to modify the teachings of Chiricescu to include the teachings of Lee so that the tag processing unit of Chiricescu receives instructions and includes a decode table to extract opcodes and operands (as taught by Lee).
The motivation for doing so would have been to enhance the performance of the system (as taught by Lee at [0015], [0058] – [0059]).
Therefore, it would have been obvious to combine Lee with Chiricescu to obtain the invention as specified in the instant claim.
As per claim 2, Chiricescu discloses “determine, based on the instructions, instruction care bit information indicative of one or more care bits, and operation group information indicative of an operation group” ([0092] don't care and opgroups).
Also, Lee discloses “the tag processing unit comprises at least one look-up table configured to determine, based on the instructions” instruction information (Fig. 1 and [0009] look-up table 15).
It would have been obvious to one of ordinary skill in the art at the time of Applicant’s filing to combine the look-up table of Lee with the don’t care and opgroups data of Chiricescu so that the look-up table includes the don’t care and opgroups data.
As per claim 3, Chiricescu discloses “the instructions are formatted in accordance with the first instruction set architecture” ([0062] Reduced Instruction Set Computer (RISC) processor, [0076] opcode, and [0092] opcode groups).
Also, Lee discloses “determining, by the tag processing unit based on the at least one decode table, that the instructions are formatted in accordance with the first instruction set architecture” (Figs. 1 and 3 along with [0009] bytecode conversion acceleration device 10 includes decoding table 13/131 and buffer 11/110. [0020] and [0047] The decoding table 131 stores a bytecode length (BL) including an operation code and the number of operands).
As per claim 4, Chiricescu discloses “the instructions are formatted in accordance with the first instruction set architecture” ([0062] Reduced Instruction Set Computer (RISC) processor, [0076] opcode, and [0092] opcode groups) and “the instruction care bit information indicative of the one or more care bits and the operation group information indicative of an operation group” ([0092] don't care and opgroups).
Also, as above, Lee discloses “a determination that the instructions are formatted in accordance with the first instruction set architecture” (Figs. 1 and 3 along with [0009] bytecode conversion acceleration device 10 includes decoding table 13/131 and buffer 11/110. [0020] and [0047] The decoding table 131 stores a bytecode length (BL) including an operation code and the number of operands).
It would have been obvious to one of ordinary skill in the art at the time of Applicant’s filing to combine the look-up table of Lee with the don’t care and opgroups data of Chiricescu so that the look-up table includes the don’t care and opgroups data, which are used to confirm that the instructions are formatted in accordance with the first instruction set architecture.
Claims 6 – 7 are rejected under 35 U.S.C. 103 as being unpatentable over Chiricescu in view of Lee, as applied to claims above, further in view of Roser, “Theory and Practice on FiFo Lanes – How Does FiFo Work in Lean Manufacturing?” (hereinafter referred to as Roser).
As per claims 6 and 7, Chiricescu discloses “the tag processing unit” ([0015] adding a metadata processing unit (the PUMP) to the conventional processor) and “the application processor” ([0015] a conventional processor (e.g. RISC-CPU, GPU, Vector processor, etc.). [0062] Reduced Instruction Set Computer (RISC) processor).
Further, Lee discloses “processing unit further comprises a buffered interface configured to store the instructions” received “and to provide stored instructions for use by the tag processing unit” (Figs. 1 and 3 bytecode buffer 11/110).
Neither Chiricescu nor Lee appears to explicitly disclose a buffered interface to store instructions “from the application processor when the tag processing unit is stalled, and to provide stored instructions for use by the tag processing unit when the instruction stream is stalled” and “the buffered interface comprises a first-in-first-out (FIFO) component.”
However, buffers are known in the art to be beneficial for allowing a sender and receiver of different speeds or intermittent processing to reliably send instructions and/or data that will be properly received.
For example, Roser teaches a FIFO buffer interface to store inventory “from” a first process “when the” second process “is stalled, and to provide stored” inventory “for use by the” second process “when the” first process “is stalled” and “the buffered interface comprises a first-in-first-out (FIFO) component” (Figures FiFo lanes and last paragraph beginning on page 2 “This waiting can be avoided by having inventory, with the long-term slowest process working with material from a buffer inventory (if the temporary slower process is before), or filling into a buffer (if the temporary slower process is afterward)”).
It would have been obvious to one of ordinary skill in the art to utilize such a buffered interface in the system of Chiricescu/Lee so that “the tag processing unit
further comprises a buffered interface configured to store the instructions from the application processor when the tag processing unit is stalled, and to provide stored instructions for use by the tag processing unit when the instruction stream is stalled.”
As stated by Roser, “in the real world, processes are not static but dynamic. Sometimes a process will take longer or shorter time than average. In this case, a FiFo lane can improve utilization and throughput of the system” (page 2, paragraph following the figure).
Chiricescu and Lee are analogous art because they are from the same field of endeavor, which is improvements to processing instructions. Chiricescu teaches security policies for executing code (Abstract) and describes performance and speed based on memory traffic ([0113]). Lee teaches an accelerator for executing instructions that will improve execution speed ([0006], [0015]). Roser is also analogous because it expands on the buffering idea of Lee.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Chiricescu, Lee, and Roser before him or her, to modify the teachings of Chiricescu and Lee to include the teachings of Roser so that the tag processing unit further comprises FIFO buffered interface configured to store the instructions from the application processor when the tag processing unit is stalled, and to provide stored instructions for use by the tag processing unit when the instruction stream is stalled.
The motivation for doing so would have been to handle real world processes where processing times change (as taught by Roser at page 2, paragraph beneath the Figure) and processes have to wait (as taught by Roser at the last paragraph beginning on page 2).
Therefore, it would have been obvious to combine Roser with Chiricescu and Lee to obtain the invention as specified in the instant claim.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Chiricescu in view of Lee, as applied to claims above, further in view of Lee, U.S. Patent Application 2015/0058997 (hereinafter referred to as Lee ‘997).
As per claim 8, Chiricescu discloses “the tag processing unit” ([0015] adding a metadata processing unit (the PUMP) to the conventional processor).
Neither Chiricescu nor Lee appears to explicitly disclose the tag processing unit “further comprises a tag map table (TMT) configured to convert one or both of a physical instruction address and a data memory page address, into one or both of (i) a corresponding associated tag addresses and (ii) directly into a tag.”
However, Lee ‘997 discloses “a tag map table (TMT) configured to convert one or both of a physical instruction address and a data memory page address, into one or both of (i) a corresponding associated tag addresses and (ii) directly into a tag” ([0081] if access is validated, then it initiates the generation of appropriate hardware tags for the data file, [0082] if the access is validated, the file management module 314 requests the hypervisor 316 to create an SDC 318 for the data file with the corresponding hardware tags, and [0103] tags and table lookups).
Chiricescu, Lee, and Lee ‘997 are analogous art because they are from the same field of endeavor, which is improvements to processing instructions. Chiricescu teaches security policies for executing code (Abstract) and describes performance and speed based on memory traffic ([0113]). Lee ‘997 similarly teaches data protected by policies ([0063]). Lee teaches an accelerator for executing instructions that will improve execution speed ([0006], [0015]).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Chiricescu, Lee, and Lee ‘997 before him or her, to modify the teachings of Chiricescu and Lee to include the teachings of Lee ‘997 so that a tag map table (TMT) is configured to convert one or both of a physical instruction address and a data memory page address, into one or both of (i) a corresponding associated tag addresses and (ii) directly into a tag.
The motivation for doing so would have been to provide a means for storing and checking tags before performing operations that may lead to security breaches (as described by Lee ‘997 at [0018]).
Therefore, it would have been obvious to combine Lee ‘997 with Chiricescu and Lee to obtain the invention as specified in the instant claim.
Allowable Subject Matter
Claims 5, 9, and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed March 16, 2026 have been fully considered but they are not persuasive.
Applicant argues, on page 6, that
Significantly, Lee does not disclose or suggest to "extract the operand information and the operation information from the instructions," let alone that this is done in "a metadata processing domain" by "a tag processing unit."
First, to convert bytecode into native code bears no relation to "a metadata processing domain."
The examiner disagrees. Lee at [0047] states that a "decoding table 131 stores a bytecode length (BL) including an operation code and the number of operands, the total number (TNC) of native codes (NC) that are converted by each bytecode, a stack variation (SV) representing change of a stack by the bytecode to be executed, and the first native code (FNC) that is converted according to each bytecode, and a link address (LA)." This data is considered to be equivalent to metadata that is processed.
Applicant continues, on page 6, that
Second, the (BL) in Lee is mentioned as being a combined numeric length of an opcode plus some number of operands. The (BL) itself is not the opcode or operand information nor is an extraction performed. Instead, Lee uses the (BL) value to index into a native code table to retrieve pre-stored conversion outputs. By including the length, the native code table in Lee can be a "native code table that stores only non-overlapping native codes among native codes to be converted from all bytecodes," as compared to approaches where "native codes are stored in duplication many times in the conventional look-up table."
The examiner disagrees. As in Lee at [0009] and [004] – [0048] bytecodes are received and a decoding table is used to generate native code according to each bytecode that will be executed. It is understood in the art that decoding includes interpreting and extracting information from encoded data. The examiner maintains that an extraction is performed in Lee. Further, as in Lee’s Figs. 1 and 3 along with [0020] and [0047], the decoding table is used for extracting operand code and the number of operands.
Also, note that Chiricescu is cited for teaching “extract the operand information and the operation information from the instructions” ([0067] "if the current opcode is opcode, ..., the tags on its input operands (if any) are OP1 and OP2").
Applicant argues, on pages 6 – 7, that Chiricescu and Lee are unrelated to one another. Applicant argues that the references cannot be combined.
The examiner disagrees. As in the previous office action,
Chiricescu and Lee are analogous art because they are from the same field of endeavor, which is improvements to processing instructions. Chiricescu teaches security policies for executing code (Abstract) and describes performance and speed based on memory traffic ([0113]). Lee teaches an accelerator for executing instructions that will improve execution speed ([0006], [0015]).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Chiricescu and Lee before him or her, to modify the teachings of Chiricescu to include the teachings of Lee so that the tag processing unit of Chiricescu receives instructions and includes a decode table to extract opcodes and operands (as taught by Lee).
The motivation for doing so would have been to enhance the performance of the system (as taught by Lee at [0015], [0058] – [0059]).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN G SNYDER whose telephone number is (571)270-1971. The examiner can normally be reached on M-F 8:00am-4:30pm (flexible).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Henry Tsai can be reached on 571-272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STEVEN G SNYDER/Primary Examiner, Art Unit 2184
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