DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-18 are pending, of which all pending claims are rejected.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-6, 8-9, 11-13, 15-16 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Rajeev Balasubramonian (WO 2016/195704 A1), (Hereinafter Balasubramonian).
Regarding claim 1, Balasubramonian teaches, a memory system comprising: an N (where N is an integer satisfying N≥2) number of memory devices (Balasubramonian: ‘plurality of memory devices’; “FIG. 1 depicts an example of a device that may use the data writing to a subset of memory devices techniques described herein. System 100 may include a memory controller 110 coupled to a plurality of memory devices 150-1 ...9. Although 9 memory devices are depicted, it should be understood that this is to aid in the description. The techniques described herein are not limited to any particular number of memory devices.” [0025] & [Fig.1]), each memory device including a first bank and a second bank that is paired with the first bank (Balasubramonian: “An actual memory device may be divided into any number of banks. For example, a memory device may be divided into 2, 4, 8, 16, or any other number of banks.” [0102]); and a controller (Balasubramonian: “System 100 may include a memory controller 110 coupled to a plurality of memory devices 150-1 ...9.” [0025]) configured to read (Balasubramonian: ‘data read/write using the memory device read/write circuit 225’ [0041,0047]) M (where M is an integer satisfying M≥2) bits of first data from the first bank of each of the N number of memory devices (Balasubramonian: ‘in Fig.1, 8 bytes or 64 bits of data are written to (or read from) the first bank of each of the eight memory devices’ [Fig.1]), …..
Balasubramonian does not explicitly disclose, … to read M bits of second data from the second bank of each of the N number of memory devices, and to process a codeword of 2∙N∙M bits, which is configured using the first data and the second data obtained from each of the N number of memory devices.
However, Balasubramonion teaches a single line or 64 bytes of data write (or read) [0017,0031-0033, 0041]. With the single line data write (or read) teaching of Balasubramonion a person ordinary skill in the art before the effective filing date of the claimed invention to write (or read) two consecutive lines or blocks of data where the first (or the first line) data are to be written into (or read from) each of the first memory banks of each of the memory devices, and the second block (or second line) data are to be written into (or read from) each of the second memory banks of each of the memory devices. Also, the first and the second memory banks of the memory device 150-9 are to be used for writing (or reading) error correction codes. By doing so, reducing the amount of write energy needed, the techniques described herein also provide for a mechanism to reduce the amount of read energy needed when reading a line of data [0037].
Regarding claim 2, Balasubramonian teaches, the memory system according to claim 1, wherein the codeword of 2∙N∙M bits includes a parity of K (where K an integer satisfying K≥2) bits, and M is equal to or smaller than 1/2 of K (Balasubramonian: ‘using right amount of error correction/detection code bits are design choice for a person ordinary skill in the art’ “[0029] The ECC generation circuit 120 may be circuitry used to calculate an ECC for the block of data. The ECC may be used to determine if there has been an error in the data. Many ECCs can be used to correct for single bit errors and detect multiple bit errors.”).
Regarding claim 3, Balasubramonian teaches, the memory system according to claim 2, wherein K is smaller than 4 times M (Balasubramonian: ‘using right amount of error correction/detection code bits are design choice for a person ordinary skill in the art’ “[0029] The ECC generation circuit 120 may be circuitry used to calculate an ECC for the block of data. The ECC may be used to determine if there has been an error in the data. Many ECCs can be used to correct for single bit errors and detect multiple bit errors.”).
Regarding claim 4, Balasubramonian teaches, the memory system according to claim 2, wherein the controller corrects an error, using the parity of K bits, in the first data obtained from a first bank included in one of the N number of memory devices or the second data obtained from a second bank included in one of the N number of memory devices (Balasubramonian: ‘detect and correct errors using error correction code’; “The ECC generation circuit may generate an ECC over the 64 bytes and the ECC is appended to the line. The memory device write may then receive the uncompressed data block as well as the appended ECC and write the line to memory devices 150-1 ...9.” [0029,0034]).
Regarding claim 5, Balasubramonian teaches, the memory system according to claim 1, wherein the codeword of 2∙N∙M bits includes L (where L is an integer satisfying L≥2) bits of metadata (Balasubramonian: ‘metadata’ [0066, 0047-0048]).
Regarding claim 6, Balasubramonian teaches, the memory system according to claim 1, wherein the controller separately transmits a first read command for reading the first data and a second read command for reading the second data to each of the N number of memory devices (Balasubramonian: “[0089] In block 560, a line in a rank of memory may be read. Reading the line may include reading all memory devices that comprise the rank. In other words, all memory devices, even those which may not be storing valid data for the line are read, in block 565, metadata indicating the result of the compression may be retrieved from a block header”).
Regarding claim 8, Balasubramonian teaches, the memory system according to claim 1, wherein the controller separately transmits a first active command for an operation of the first bank and a second active command for an operation of the second bank to each of the N number of memory devices (Balasubramonian: “[0022] Because the writes to memory devices are spread based on the mapping, it may be possible to increase memory write bandwidth by performing multiple writes in parallel. For example, if a first line is to be stored on the first three memory devices and a second line is to be stored on the last three memory devices, the lines may be written in parallel. Because there is no overlap in the memory devices used, each device can be commanded to write a different line”).
Regarding claim 9, Balasubramonian teaches, the memory system according to claim 1, wherein the controller obtains the first data and the second data in correspondence to a single command transmitted to each of the N number of memory devices (Balasubramonian: “[0022] Because the writes to memory devices are spread based on the mapping, it may be possible to increase memory write bandwidth by performing multiple writes in parallel. For example, if a first line is to be stored on the first three memory devices and a second line is to be stored on the last three memory devices, the lines may be written in parallel. Because there is no overlap in the memory devices used, each device can be commanded to write a different line”).
Regarding claim 11, Balasubramonian teaches, a controller comprising: a control circuit configured to output a first read command for a first bank included in each of an N (where N is an integer satisfying N≥2) number of memory devices and a second read command for a second bank included in each of the N number of memory devices (Balasubramonian: ‘plurality of memory devices’; “FIG. 1 depicts an example of a device that may use the data writing to a subset of memory devices techniques described herein. System 100 may include a memory controller 110 coupled to a plurality of memory devices 150-1 ...9. Although 9 memory devices are depicted, it should be understood that this is to aid in the description. The techniques described herein are not limited to any particular number of memory devices.” [0025] & [Fig.1]), to pair the second bank and the first bank in each of the N number of memory devices (Balasubramonian: “An actual memory device may be divided into any number of banks. For example, a memory device may be divided into 2, 4, 8, 16, or any other number of banks.” [0102]), and …. an error correction circuit configured to correct an error in the first data obtained from the first bank included in one of the N number of memory devices or the second data obtained from the second bank included in one of the N number of memory devices, using a parity of K (where K is an integer satisfying K≥2) bits included (Balasubramonian: ‘error correction circuit’; “System 200 may also include ECC generation / validation circuit 220. As above with respect to element 120, circuit 220 may generate an ECC to ensure that a line does not contain errors. Circuit 220 may also include functionality to validate the ECC. Circuit 220 may examine a line of data and validate that the ECG indicates that there are no errors in the line..” [0040, 0029,0034]),….
Balasubramonian does not explicitly disclose, to obtain M (where M is an integer satisfying M≥2) bits of first data corresponding to the first read command and M bits of second data corresponding to the second read command; and …. in a codeword of 2∙N∙M bits, which is configured using the first data and the second data obtained from each of the N number of memory devices.
However, Balasubramonion teaches a single line or 64 bytes of data write (or read) [0017,0031-0033, 0041]. With the single line data write (or read) teaching of Balasubramonion a person ordinary skill in the art before the effective filing date of the claimed invention to write (or read) two consecutive lines or blocks of data where the first (or the first line) data are to be written into (or read from) each of the first memory banks of each of the memory devices, and the second block (or second line) data are to be written into (or read from) each of the second memory banks of each of the memory devices. Also, the first and the second memory banks of the memory device 150-9 are to be used for writing (or reading) error correction codes. By doing so, reducing the amount of write energy needed, the techniques described herein also provide for a mechanism to reduce the amount of read energy needed when reading a line of data [0037].
Regarding claim 12, Balasubramonian teaches, the controller according to claim 11, wherein K is at least two times M and is smaller than four times M (Balasubramonian: ‘using right amount of error correction/detection code bits are design choice for a person ordinary skill in the art’ “[0029] The ECC generation circuit 120 may be circuitry used to calculate an ECC for the block of data. The ECC may be used to determine if there has been an error in the data. Many ECCs can be used to correct for single bit errors and detect multiple bit errors.”).
Regarding claim 13, Balasubramonian teaches, the controller according to claim 11, wherein the codeword of 2∙N∙M bits includes L (where L is an integer satisfying L≥2) bits of metadata (Balasubramonian: ‘metadata’ [0066, 0047-0048]).
Regarding claim 15, Balasubramonian teaches, the controller according to claim 11, wherein the control circuit separately transmits a first active command for an operation of the first bank and a second active command for an operation of the second bank to each of the N number of memory devices (Balasubramonian: “[0022] Because the writes to memory devices are spread based on the mapping, it may be possible to increase memory write bandwidth by performing multiple writes in parallel. For example, if a first line is to be stored on the first three memory devices and a second line is to be stored on the last three memory devices, the lines may be written in parallel. Because there is no overlap in the memory devices used, each device can be commanded to write a different line”).
Regarding claim 16, Balasubramonian teaches, a memory device (Balasubramonian: ‘memory devices 150-1 through 150-9 in Fig.1’ [Fig.1]) comprising: a first bank including a plurality of first word lines, a plurality of first bit lines and a plurality of first memory cells (Balasubramonian: ‘each line from LINE 0 to LINE n in Fig. 1 represents a memory bank of a memory device’ [Fig.1]; ‘each memory bank of a memory device include one or more bit line, word line and memory cells are well known for a person ordinary skill in the art before the effective filling date of the claimed invention’ ); and a second bank paired with the first bank, and including a plurality of second word lines, a plurality of second bit lines and a plurality of second memory cells (Balasubramonian: “An actual memory device may be divided into any number of banks. For example, a memory device may be divided into 2, 4, 8, 16, or any other number of banks.” [0102]), ….
Balasubramonian does not explicitly disclose, wherein M (where M is an integer satisfying M≥2) bits of first data read from the first bank and M bits of second data read from the second bank are provided in response to a single command.
However, Balasubramonion teaches a single line or 64 bytes of data write (or read) [0017,0031-0033, 0041]. With the single line data write (or read) teaching of Balasubramonion a person ordinary skill in the art before the effective filing date of the claimed invention to write (or read) two consecutive lines or blocks of data where the first (or the first line) data are to be written into (or read from) each of the first memory banks of each of the memory devices, and the second block (or second line) data are to be written into (or read from) each of the second memory banks of each of the memory devices. Also, the first and the second memory banks of the memory device 150-9 are to be used for writing (or reading) error correction codes. By doing so, reducing the amount of write energy needed, the techniques described herein also provide for a mechanism to reduce the amount of read energy needed when reading a line of data [0037].
Regarding claim 18, Balasubramonian teaches, the memory device according to claim 16, wherein read operations on an M number of first bit lines and an M number of second bit lines are performed in response to the single command (Balasubramonion teaches a single line or 64 bytes of data write (or read) [0017,0031-0033, 0041]. With the single line data write (or read) teaching of Balasubramonion a person ordinary skill in the art before the effective filing date of the claimed invention to write (or read) two consecutive lines or blocks of data where the first (or the first line) data are to be written into (or read from) each of the first memory banks of each of the memory devices, and the second block (or second line) data are to be written into (or read from) each of the second memory banks of each of the memory devices. Also, the first and the second memory banks of the memory device 150-9 are to be used for writing (or reading) error correction codes. By doing so, reducing the amount of write energy needed, the techniques described herein also provide for a mechanism to reduce the amount of read energy needed when reading a line of data [0037].)
Claims 10, 17, 7 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Balasubramonian (WO 2016/195704 A1) in view of Kang et al. (US 2013/0039135 A1), (Hereinafter Balasubramonian-Kang).
Regarding claim 10, Balasubramonian does not explicitly teach, the memory system according to claim 9, wherein each of the N number of memory devices performs precharge operations on the respective first banks and second banks in response to the single command.
However, Kang et al. teaches in an analogous art, each of the N number of memory devices performs precharge operations on the respective first banks and second banks in response to the single command (Kang: [0052-0057]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the ‘data block write mapped to memory bank’ taught by Balasubramonian with the ‘performing precharge operation on memory bank’ as taught by Kang since doing so would accurately write data to word lines.
Regarding claim 17, Balasubramonian-Kang teaches, the memory device according to claim 16, wherein in response to the single command, the first bank and the second bank are precharged and read operations on the first bank and the second bank are performed (Kang: ‘performing precharge operation on memory bank’ [0052-0057]).
Regarding claim 7, Balasubramonian-Kang teaches, the memory system according to claim 6, wherein the controller transmits the first read command and the second read command in an interleaving scheme (Kang: ‘data write/read operation using bank/sub-bank interleaving method’ [0058-0063]).
Regarding claim 14, Balasubramonian-Kang teaches, the controller according to claim 11, wherein the controller transmits the first read command and the second read command in an interleaving scheme (Kang: ‘data write/read operation using bank/sub-bank interleaving method’ [0058-0063]).
Citation of Pertinent Prior Art
It is noted that any citations to specific, pages, columns, lines, or figures in the prior art references and any interpretation of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP 2123.
Conclusion
The following prior arts made of record, listed on form PTO-892, and not relied upon, if any, are considered pertinent to applicant's disclosure:
Chung et al. (US 2022/0121518 A1) teaches a semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.
When amending the claims, Applicants are respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ENAMUL MD KABIR whose telephone number is (571)270-7256. The examiner can normally be reached on 10:00-6:30 pm.
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/ENAMUL M KABIR/
Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112