Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAIL ACTION
Claims 1-21 are presented for examination.
Processor and memory “configured to” perform a function recited throughout claims 1-18 directly or via dependency are not treated under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph because it failed the third prong of the three-prong test modifying by reciting sufficient structure.
Claim Objections
Claim 19 is objected to because of the following informalities: “setting up a value in the hypervisor status register du to indicate…” should read -- setting up a value in the hypervisor status register to indicate…--.
Appropriate correction is required.
Double Patenting
A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957).
A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101.
Claims 2-3 is/are rejected under 35 U.S.C. 101 as claiming the same invention as that of claims 1-2 of prior U.S. Patent No. 12,131,178 (Note: dependent claim(s) include every limitation of the claim from which it depends and that it specify a further limitation(s) of the subject matter claimed). This is a statutory double patenting rejection.
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1 and 4-21 are rejected on the ground of nonstatutory double patenting as being anticipated by claims 1 and 3-20 of US Patent 12,131,178 (hereafter ‘178) such that claims 1 and 3-20 of Patent ‘178 include all the limitations of claims 1 and 4-21 despite a slight difference in wording (Note: status register that stores a value indicative of whether or not an operating hypervisor is present and hypervisor status register that performs the same function are both registers and are directed to identical subject matter).
US Patent 12,131,178
Instant Application
1. An apparatus, comprising:
a memory configured to store at least instructions of routines of a predefined set of domains; and
a processor coupled with the memory, the processor comprising a status register, and the processor configured to:
determine a value stored in the status register, the value indicative of whether or not an operating hypervisor is present; and
customize an operation of a computer system based on the value stored in the status register;
wherein the value stored in the status register is not adjustable outside of a power up process of the apparatus.
1. An apparatus, comprising:
a memory configured to store at least instructions of routines of a predefined set of domains; and
a processor coupled with the memory, the processor comprising a hypervisor status register, and the processor configured to: determine a value stored in the hypervisor status register, the value indicative of whether or not an operating hypervisor is present; and customize an operation of a computer system comprising the processor and the memory based on the value stored in the hypervisor status register.
3. The apparatus of claim 1, wherein the processor is further configured to store the value in the status register during a power up process of the apparatus.
4. The apparatus of claim 1, wherein the predefined set of domains comprises at least one of a domain for hypervisor, a domain for operating system, or a domain for application, or any combination thereof.
5. The apparatus of claim 4, wherein the predefined set of domains have no predefined levels of trust.
6. The apparatus of claim 1, wherein the customization of the operation comprises the processor configured to customize address translation operations in the processor according to the value stored in the status register.
7. The apparatus of claim 6, wherein the customization of the operation comprises the processor configured to use a virtual machine identifier in address translation in response to the status register indicating that an operating hypervisor is present in the apparatus.
8. The apparatus of claim 6, wherein the customization of the operation comprises the processor configured to perform address translation without using a virtual machine identifier in response to the status register indicating that no operating hypervisor is present in the apparatus.
9. The apparatus of claim 6, wherein the customization of the operation comprises the processor configured to trap an operation performed in execution of an operating system running in a virtual machine in generating a page table entry mapping a virtual address page to a pseudo-physical address page, in response to the status register indicating that an operating hypervisor is present in the apparatus.
10. The apparatus of claim 9, wherein the processor is configured to execute a routine of the hypervisor to identify a physical address page corresponding to the pseudo-physical address page in the virtual machine, in response to the operation of the operating system running in the virtual machine is trapped.
11. The apparatus of claim 10, wherein the processor is configured to modify the page table entry mapping the virtual address page to the pseudo-physical address page into a page table entry mapping the virtual address page to the physical address page.
12. A processor, comprising:
a status register, and the processor configured to:
determine a value stored in the status register, the value indicative of whether or not an operating hypervisor is present in the system; and customize an operation of a computer system comprising the processor on the value stored in the status register;
wherein the value stored in the status register is not adjustable outside of a power up process of the apparatus.
13. The processor of claim 12, wherein the customization of the operation comprises the processor configured to customize translation of virtual memory addresses to physical memory addresses according to the value stored in the status register.
14. The processor of claim 12, wherein the customization of the operation comprises the processor configured to apply a security control to a resource of the computer system based on the value stored in the status register.
15. The processor of claim 14, wherein the resource comprises at least one of a privileged register, a called routine, or a memory region of a memory device of the computer system.
16. The processor of claim 14, wherein processor is coupled to a memory, and the memory is configured to store at least instructions of routines of a predefined set of domains, and further wherein the processor is further configured to, during execution of one of the routines, select a setting for the security control that is preassociated with a domain for which one of the routines is being executed.
17. The processor of claim 16, wherein the setting is indicative of whether access to the memory is permissible while the one of the routines is being executed.
18. A method, comprising:
storing in a memory at least instructions of routines of a predefined set of domains;
providing, in a processor coupled with the memory, a status register;
setting up a value in the status register to indicate whether or not an operating hypervisor is present; and
customizing operations in the processor based on the value stored in the status register; wherein the value stored in the status register is not adjustable outside of a power up process of the apparatus.
19. The method of claim 18, wherein the customizing of the operations comprising: customizing translation of virtual memory addresses to physical memory addresses according to the value stored in the status register.
20. The method of claim 18, wherein the customizing of the operations comprising: applying a security control to a resource of the computer system based on the value stored in the status register.
4. The apparatus of claim 1, wherein the processor is further configured to store the value in the hypervisor status register during a power up process of the apparatus.
5. The apparatus of claim 1, wherein the predefined set of domains comprises at least one of a domain for hypervisor, a domain for operating system, or a domain for application, or any combination thereof.
6. The apparatus of claim 5, wherein the predefined set of domains have no predefined levels of trust.
7. The apparatus of claim 1, wherein the customization of the operation comprises the processor configured to customize address translation operations in the processor according to the value stored in the hypervisor status register.
8. The apparatus of claim 7, wherein the customization of the operation comprises the processor configured to use a virtual machine identifier in address translation in response to the hypervisor status register indicating that an operating hypervisor is present in the apparatus.
9. The apparatus of claim 7, wherein the customization of the operation comprises the processor configured to perform address translation without using a virtual machine identifier in response to the hypervisor status register indicating that no operating hypervisor is present in the apparatus.
10. The apparatus of claim 7, wherein the customization of the operation comprises the processor configured to trap an operation performed in execution of an operating system running in a virtual machine in generating a page table entry mapping a virtual address page to a pseudo-physical address page, in response to the hypervisor status register indicating that an operating hypervisor is present in the apparatus.
11. The apparatus of claim 10, wherein the processor is configured to execute a routine of the hypervisor to identify a physical address page corresponding to the pseudo-physical address page in the virtual machine, in response to the operation of the operating system running in the virtual machine is trapped.
12. The apparatus of claim 11, wherein the processor is configured to modify the page table entry mapping the virtual address page to the pseudo-physical address page into a page table entry mapping the virtual address page to the physical address page.
13. A processor, comprising:
a hypervisor status register, and the processor configured to:
determine a value stored in the hypervisor status register, the value indicative of whether or not an operating hypervisor is present in the system; and customize an operation of a computer system comprising the processor on the value stored in the hypervisor status register.
14. The processor of claim 13, wherein the customization of the operation comprises the processor configured to customize translation of virtual memory addresses to physical memory addresses according to the value stored in the hypervisor status register.
15. The processor of claim 13, wherein the customization of the operation comprises the processor configured to apply a security control to a resource of the computer system based on the value stored in the hypervisor status register.
16. The processor of claim 15, wherein the resource comprises at least one of a privileged register, a called routine, or a memory region of a memory device of the computer system.
17. The processor of claim 15, wherein processor is coupled to a memory, and the memory is configured to store at least instructions of routines of a predefined set of domains, and further wherein the processor is further configured to, during execution of one of the routines, select a setting for the security control that is preassociated with a domain for which one of the routines is being executed.
18. The processor of claim 17, wherein the setting is indicative of whether access to the memory is permissible while the one of the routines is being executed.
19. A method, comprising:
storing in a memory at least instructions of routines of a predefined set of domains; providing, in a processor coupled with the memory, a hypervisor status register;
setting up a value in the hypervisor status register du to indicate whether or not an operating hypervisor is present; and customizing operations in the processor based on the value stored in the hypervisor status register.
20. The method of claim 19, wherein the customizing of the operations comprising: customizing translation of virtual memory addresses to physical memory addresses according to the value stored in the hypervisor status register.
21. The method of claim 19, wherein the customizing of the operations comprising: applying a security control to a resource of the computer system based on the value stored in the hypervisor status register.
Claim 1 is rejected on the ground of nonstatutory double patenting as being anticipated by claim 3 (i.e. limitations of claims 1-3) of US Patent 11,500,665 (hereafter ‘665) such that claim 3 of Patent ‘665 includes all the limitations of claim 1 despite a slight difference in wording [note: a processor configured to identify and customized operation in the processor/computer system determined the valued stored in the hypervisor status register].
As to claims 2 and 7-12, these claims are rejected on the ground of nonstatutory double patenting as being anticipated by claims 4-10 of Patent ‘665 for the same reason as applied to claim 1 above.
Claims 3-6 are rejected on the ground of nonstatutory double patenting as being anticipated by claims 1-2 of Patent ‘665 such that claims 1-2 of Patent ‘665 includes all the limitations of claims 3-6 with the difference in claim hierarchy. However, claiming limitations in different claim hierarchies are well known in the art and would have been a matter of design choice.
Claims 19-20 are rejected on the ground of nonstatutory double patenting as being anticipated by claims 12 and 14 of Patent ‘665 such that claims 12 and 14 of Patent ‘665 includes all the limitations of claims 19-20.
US Patent 11,500,665
Instant Application
1. A computer system, comprising:
a memory configured to store at least instructions of routines of a predefined set of domains; and
a processor coupled with the memory, the processor comprising a hypervisor status register, the processor configured to store a value in the hypervisor status register during a power up process of the computer system, the value configured to identify whether or not an operating hypervisor is present in the computer system, wherein the power up process comprises an initial powering on of the processor of the computer system.
2. The computer system of claim 1, wherein the predefined set of domains comprises at least one of a domain for hypervisor, a domain for operating system, or a domain for application, or any combination thereof; and wherein the domains have no predefined levels of trust.
3. The computer system of claim 2, wherein the processor is further configured to customize operations in the processor according to the value stored in the hypervisor status register.
1. An apparatus, comprising:
a memory configured to store at least instructions of routines of a predefined set of domains; and
a processor coupled with the memory, the processor comprising a hypervisor status register, and the processor configured to:
determine a value stored in the hypervisor status register, the value indicative of whether or not an operating hypervisor is present; and
customize an operation of a computer system comprising the processor and the memory based on the value stored in the hypervisor status register.
4. The computer system of claim 3, wherein the value stored in the hypervisor status register is not adjustable outside of the power up process.
2. The apparatus of claim 1, wherein the value stored in the hypervisor status register is not adjustable outside of a power up process of the apparatus.
1. A computer system, comprising:
a memory configured to store at least instructions of routines of a predefined set of domains; and
a processor coupled with the memory, the processor comprising a hypervisor status register, the processor configured to store a value in the hypervisor status register during a power up process of the computer system, the value configured to identify whether or not an operating hypervisor is present in the computer system, wherein the power up process comprises an initial powering on of the processor of the computer system.
2. The computer system of claim 1, wherein the predefined set of domains comprises at least one of a domain for hypervisor, a domain for operating system, or a domain for application, or any combination thereof; and
wherein the domains have no predefined levels of trust.
4. The apparatus of claim 1, wherein the processor is further configured to store the value in the hypervisor status register during a power up process of the apparatus.
3. The apparatus of claim 2, wherein the power up process comprises an initial powering on of the processor of the apparatus.
5. The apparatus of claim 1, wherein the predefined set of domains comprises at least one of a domain for hypervisor, a domain for operating system, or a domain for application, or any combination thereof.
6. The apparatus of claim 5, wherein the predefined set of domains have no predefined levels of trust.
5. The computer system of claim 3, wherein the processor is further configured to customize address translation operations in the processor according to the value stored in the hypervisor status register.
6. The computer system of claim 5, wherein the processor is configured to use a virtual machine identifier in address translation when the hypervisor status register indicates that an operating hypervisor is present in the computer system.
7. The computer system of claim 6, wherein the processor is configured to perform address translation without using a virtual machine identifier when the hypervisor status register indicates that no operating hypervisor is present in the computer system.
8. The computer system of claim 6, wherein the processor is configured to trap an operation performed in execution of an operating system running in a virtual machine in generating a page table entry mapping a virtual address page to a pseudo-physical address page, when the hypervisor status register indicates that an operating hypervisor is present in the computer system.
9. The computer system of claim 8, wherein the processor is configured to execute a routine of the hypervisor to identify a physical address page corresponding to the pseudo-physical address page in the virtual machine, in response to the operation of the operating system running in the virtual machine is trapped.
10. The computer system of claim 9, wherein the processor is configured to modify the page table entry mapping the virtual address page to the pseudo-physical address page into a page table entry mapping the virtual address page to the physical address page.
7. The apparatus of claim 1, wherein the customization of the operation comprises the processor configured to customize address translation operations in the processor according to the value stored in the hypervisor status register.
8. The apparatus of claim 7, wherein the customization of the operation comprises the processor configured to use a virtual machine identifier in address translation in response to the hypervisor status register indicating that an operating hypervisor is present in the apparatus.
9. The apparatus of claim 7, wherein the customization of the operation comprises the processor configured to perform address translation without using a virtual machine identifier in response to the hypervisor status register indicating that no operating hypervisor is present in the apparatus.
10. The apparatus of claim 7, wherein the customization of the operation comprises the processor configured to trap an operation performed in execution of an operating system running in a virtual machine in generating a page table entry mapping a virtual address page to a pseudo-physical address page, in response to the hypervisor status register indicating that an operating hypervisor is present in the apparatus.
11. The apparatus of claim 10, wherein the processor is configured to execute a routine of the hypervisor to identify a physical address page corresponding to the pseudo-physical address page in the virtual machine, in response to the operation of the operating system running in the virtual machine is trapped.
12. The apparatus of claim 11, wherein the processor is configured to modify the page table entry mapping the virtual address page to the pseudo-physical address page into a page table entry mapping the virtual address page to the physical address page.
12. A method, comprising:
storing in a memory at least instructions of routines of a predefined set of domains;
providing, in a processor coupled with the memory, a hypervisor status register;
setting up a value in the hypervisor status register during a power up process of the processor to indicate whether or not an operating hypervisor is present, wherein the power up process comprises an initial powering on of the processor; and customizing operations in the processor based on the value stored in the hypervisor status register.
19. A method, comprising:
storing in a memory at least instructions of routines of a predefined set of domains;
providing, in a processor coupled with the memory, a hypervisor status register;
setting up a value in the hypervisor status register du to indicate whether or not an operating hypervisor is present; and
customizing operations in the processor based on the value stored in the hypervisor status register.
14. The method of claim 13, wherein the customizing of the operations comprising: customizing translation of virtual memory addresses to physical memory addresses according to the value stored in the hypervisor status register.
20. The method of claim 19, wherein the customizing of the operations comprising: customizing translation of virtual memory addresses to physical memory addresses according to the value stored in the hypervisor status register.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 5-8 and 13-21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Patent 8,713,563 to Kondoh et al. (hereafter Kondoh).
Kondoh was cited in applicant’s IDS filed on 10/30/24.
As to claim 1, Kondoh teaches the invention as claimed including an apparatus, comprising:
a memory configured to store at least instructions of routines of a predefined set of domains [execution modes and associated instructions inherently stored in a memory, col. 7, lines 35-40; Fig. 1, memory 120]; and
a processor coupled with the memory, the processor comprising a hypervisor status register, the processor configured to:
determine a value stored in the hypervisor status register, the value indicative of whether or not an operating hypervisor is present [CPU coupled to the memory, an XVSCR.MD register in the CPU, wherein the XVSCR.MD register holds a value of one bit; the value of which determines whether an operating mode is a virtual machine manager mode (XVS Mode) hence an indication of the presence of a VMM, col. 7, line 45-col. 8, line 5; and Fig. 1, CPU 100, Memory 120, XVSCR.MD 150]; and
customize an operation of a computer system comprising the processor and the memory based on the value stored in the hypervisor status register [XVSCR.MD register value determines mode of operation having specific access/restrictions to resources of a computer system, col. 7, lines 25-65].
As to claim 5, Kondoh teaches the invention as claimed including wherein the predefined set of domains comprises at least one of a domain for hypervisor, a domain for operating system, or a domain for application, or any combination thereof [operating modes such as user mode, Priv Mode and XVS Mode having various levels of resource access/restrictions, col. 7, line 25-col. 8, line 5].
As to claim 6, Kondoh teaches the invention as claimed including wherein the domains have no predefined levels of trust [operating modes such as user mode, Priv Mode and XVS Mode having various levels of resource access/restrictions, col. 7, line 25-col. 8, line 5].
As to claims 7-8, Kondoh teaches the invention as claimed including wherein the customization of the operation comprises the processor configured to customize address translation operations in the processor according to the value stored in the hypervisor status register; wherein the customization of the operation comprises the processor configured to use a virtual machine identifier in address translation in response to the hypervisor status register indicating that an operating hypervisor is present in the apparatus [in address translation by an MMU (105), hit judgments with respect to a virtual address generated by an executed instruction, a value of the XVSVMID.VMID register, and a value of an address space identifier (ASID) set by the MMU (105) are performed for each entry using the VMID field, the VPN field, ASID field, and V field of an address array and the SZ field of a data array of a translation look-aside buffer (TLB), Col. 9, lines 17-25; and Fig. 1].
As to claim 13, this claim is rejected for the same reason as claim 1 above.
As to claim 14, Kondoh teaches the invention as claimed including wherein the customization of the operation comprises the processor configured to customize translation of virtual memory addresses to physical memory addresses according to the value stored in the hypervisor status register [a translation look aside buffer (TLB) constituting the MMU holds address translation settings for translating a virtual address, which is an address for access issued by the execution section (EXEC), into a physical address, Col. 8, line 59-Col. 9, line 13; and Figs. 1 and 3; transfer of control to/from guest O/Ses to VMM, Col. 18, lines 16-37; interrupt processing and transfer of control from guest O/Ses to VMM, Fig. 21 and corresponding text].
As to claim 15, Kondoh teaches the invention as claimed including wherein the customization of the operation comprises the processor configured to apply a security control to a resource of the computer system based on the value stored in the hypervisor status register [XVSCR.MD register value determines mode of operation having specific access/restrictions to resources of a computer system, see column 7, lines 25-65; specific access to an address region, col. 10, lines 1-44].
As to claim 16, Kondoh teaches the invention as claimed including wherein the resource comprises at least one of a privileged register, a called routine, or a memory region of a memory device of the computer system [restricted access to particular CPU register, col. 7, lines 35-37].
As to claims 17-18, this claim is rejected for the same reason as claims 5 and 15-16 above.
As to claims 19-21, this claim is rejected for the same reason as claim 1 and 14-15 above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kondoh as applied to claims 1 and 7 above.
As to claim 9, Kondoh as modified does not specifically teach the limitations as claimed. However, Kondoh teaches a user mode are taken according to a value of an XVSVMID.VMID register, wherein the user mode is a mode that a typical application program (i.e. a user program) runs [Col. 7, lines 34-35; Col. 8, lines 2-5 and Fig. 1]. Furthermore, it is well known in the art in a system that address translation or resolution in a system without a hypervisor or virtualization do not necessitate the use of identifier of a virtual machine. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a well-known feature as a matter of design choice.
Claim(s) 2 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Patent 8,713,563 to Kondoh et al. (hereafter Kondoh) as applied to claim 1 above in view of “Implementation of Intel Virtual Machine Extension Root Operation on the NPS Least Privilege Separation Kernel” to Martinsen.
Martinsen was cited in applicant’s IDS filed on 10/30/24.
As to claim 2, Kondoh does not specifically teach wherein the value stored in the hypervisor status register is not adjustable outside of a power up process of the apparatus. However, Martinsen teaches requirements for booting and transitioning LPSK….to operate as a VMM [p. 2] and at least the value of bit 31 of ECX, setting of bit 5 of ECX and/or setting of bit 5 of EDX in startup/boot/BIOS [p. 26, line 24 -p.34, line 7] (Note: power up process broadly interpret as the process of initiating or preparing or transitioning into a hypervisor mode of operation (i.e. not as a booting sequence or bootstrap process)). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teaching of Kondoh and Martinsen to achieve the predictable result of having a computer system having knowledge of whether is operating with or without the presence of a hypervisor or virtualization capability.
As to claim 4, this claim is rejected for the same reason as claim 2 above.
Claim(s) 10-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kondoh as applied to claims 1 and 7, in view of US PG Pub. 2021/0240619 to Earnshaw.
Earnshaw was cited in applicant’s IDS filed on 10/30/24.
As to claims 10-12, Kondoh teaches the invention substantially as claimed including wherein the customization of the operation comprises the processor configured to trap an operation performed in execution of an operating system running in a virtual machine in generating a page table entry mapping a virtual address page to a physical address page, in response to the hypervisor status register indicating that an operating hypervisor is present in the apparatus; to execute a routine of the hypervisor to identify a physical address page corresponding to the virtual address page in the virtual machine, in response to the operation of the operating system running in the virtual machine is trapped [a translation look aside buffer (TLB) constituting the MMU holds address translation settings for translating a virtual address, which is an address for access issued by the execution section (EXEC), into a physical address, Col. 8, line 59-Col. 9, line 13; and Figs. 1 and 3; transfer of control to/from guest O/Ses to VMM, Col. 18, lines 16-37; interrupt processing and transfer of control from guest O/Ses to VMM, Fig. 21 and corresponding text]. Kondoh as modified does not specifically pseudo-physical address page and modify the page table entry mapping the virtual address page to the pseudo-physical address page into a page table entry mapping the virtual address page to the physical address page. However, Earnshaw teaches a two-stage address translation, a first stage from the virtual address to an intermediate physical address under control of a first set of page tables set by the operating system, and a second stage from the intermediate physical address to physical address under control of a second set of page tables controlled by a hypervisor [paragraph 61, lines 4-10]. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combine the teaching of Kondoh, Martinsen and Earnshaw because they are in the same field of endeavor pertaining to virtualization and that Earnshaw’s two stage address translation is useful for supporting virtualization where multiple guest operating systems coexist on the same platform and are mapped by the hypervisor onto different regions of the physical address space even though the operating systems may from their point of view perceive that they are using physical addresses as being considered by Earnshaw.
Allowable Subject Matter
Claim 3 would be allowable by overcoming the nonstatutory double patenting rejection and if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to QING YUAN WU whose telephone number is (571)272-3776. The examiner can normally be reached M-F 9AM-6PM EST.
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/QING YUAN WU/Primary Examiner, Art Unit 2199
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