DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The Terminal disclaimer filed(04-14-26) has been approved.
The examiner would like to request an interview by telephone before the next response, if possible, to discuss ways to advance prosecution.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3, 4, 6, 7 and 8 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim et al US 7,005,930 new cite.
Re claims 1:
The reference to Kim et al discloses a clocking circuit(oscillator). The IC circuit comprises a 1st VCO oscillator(456) w/ 1st core and 2nd VCO oscillator(458) w/ 2nd core. See figure 5 below. A 1st Inductor (466)is shown in the 1st VCO between T1(1st )and T2(2nd )terminals. The switching network forms a ‘butterfly’ switch due to the balanced couplings of the differential core. A 2nd Inductor(468) is shown coupled in the 2nd VCO between the T3(3rd ) and T4 (4th )terminals .
A 3rd core(oscillator) is operably coupled to the 1st core (oscillator)by way of the inductive coupling via the third inductor (462) shown coupling the other inductor elements for each core.
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Re claim 3:
a first voltage controlled oscillator ( 1st core VCO/456) that includes the first core(cross-coupled transistors and LC circuit) and the first inductor(466).
Re claim 4:
a second VCO (2nd core oscillator/458) includes the second core(cross-coupled transistors and LC circuit) and the second inductor(468).
Re claim 6. The switching circuitry comprises a ‘butterfly’ switch as described above.
Re claim 7:
Please note the T1,T2,T3,T4 terminal indicators on the oscillator terminals. The first core has first (T1)and second terminals(T2), the first inductor(466) is coupled between the first and second terminals, the second core has third (T3)and fourth terminals(T4), the second inductor(468) is coupled between the third and fourth terminals, and the switching circuitry couples the first and second terminals to the third and fourth terminals.
Re claim 8:
A 1st SW(475) is shown coupling the 1st terminal (T1)and the 3rd terminal(T3). A 2nd SW(476) is shown coupling the 2nd (T2)and 4th (T4)terminals. A 3rd SW(478) is shown between the 1st and 4th terminals, and a 4th SW(477) is shown between the 2nd (T2)and 3rd terminals(T3).
The 1st VCO is shown with 1st (T1)and 2nd terminals(T2); the 2nd VCO is shown with 3rd (T3) and 4th terminals(T4).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 13-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Farazian et al US 20160373057 of record.
Re claims 13:
The reference to Farazian et al discloses a clocking circuit. The IC circuit comprises a 1st VCO oscillator/core and 2nd VCO oscillator/core. See figure 2B below. A 1st Inductor (L1)is shown in the 1st VCO between 1st and 2nd terminals. The switching network forms a ‘butterfly’ switch due to the balanced couplings due to differential structure. A 2nd Inductor(L2) is shown coupled in the 2nd VCO between the 3rd and 4th terminals
A 4th SW(switching circuitry) is shown coupling the neg(-) of 1st VCO and the neg(-) of the 2nd VCO. The tuning caps (C1,C2)allow in band tuning.
A 1st SW is shown coupling the 1st terminal and the 3rd terminal. A 2nd SW is shown coupling the 2nd and 4th terminals.
The 1st VCO is shown with 1st and 2nd terminals; the 2nd VCO is shown with 3rd and 4th terminals.
The switching action allows for current direction in the cores to allow for the out of phase signal outputs, that is, constantly switching current direction to maintain energy balance and the 90° phase separation between the two oscillator cores.
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The reference to Farazian et al does not explicitly disclose use of varactors for the tuning capacitors in each oscillator , however, these are functionally equivalent means and allow for band tuning as desired.
In light of the above it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have recognized that the apparatus as described by Farazian et al for generic capacitors can make use of varactors, as a functionally equivalent means, for achieving the same frequency adjustment as desired.
Re claim 14. The switching circuitry comprises a ‘butterfly’ switch as described above.
Re claim 15: The ability to use the switching circuit to switch cores depending on the frequency band desired, that is, when the switching in a particular state allows for the 1st core oscillator to operate and then in the other state to allow the 2nd core to oscillate at a particular clock output signal, in band, is inherent to the configuration as described. The tuning caps (C1,C2)allow in band tuning.
Allowable Subject Matter
Claims 2, 5, 9, 10, 11, 12 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 17-20 are allowed.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARNOLD M KINKEAD whose telephone number is (571)272-1763. The examiner can normally be reached M-F 7am-5:30pm(Fri-Flex).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at 571-270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ARNOLD M KINKEAD/Primary Examiner, Art Unit 2836
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