DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 13, 17 and 18 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 15, 17 and 18 of U.S. Patent No. 12,184,222. Although the claims at issue are not identical, they are not patentably distinct from each other because
the current application claims for an IC circuit with first and second oscillators(cores), for example see claims 13, 17 and 18, are merely broader than claims 1, 15, 17 and 18 patented in 12,184,222,
Claims in the current application, provide for a circuit with a first oscillator/core having first and second terminals; a second oscillator having third and fourth terminals; and a butterfly switch that couples the first and second terminals to the third and fourth terminals. Claims 17 and 18 extend the number of oscillators, that is a third oscillator and 4th oscillator with respective third and fourth switching circuitry. The patent mirrors this but claims VCO and butterfly switch.
The integration of such circuit elements in transceivers, for example, is a simple matter of design consideration.
18/924,876
US PAT 12,184,232
1. Circuitry comprising: a first core; a first inductor operably coupled to the first core; a second core; a second inductor operably coupled to the second core; and switching circuitry coupled between the first core and the second core, wherein the switching circuitry is configured to reverse a current direction in the first core.
2. The circuitry of claim 1, wherein the circuitry is configured to output an oscillator signal and the switching circuitry is configured to adjust a frequency range of the oscillator signal.
3. The circuitry of claim 1, further comprising: a first voltage controlled oscillator (VCO) that includes the first core and the first inductor.
4. The circuitry of claim 3, further comprising: a second VCO that includes the second core and the second inductor.
5. The circuitry of claim 1, wherein the switching circuitry has first and second states, the circuitry is configured to generate an oscillator signal at a first frequency while the switching circuitry is in the first state, and the circuitry is configured to generate the oscillator signal at a second frequency different than the first frequency while the switching circuitry is in the second state.
6. The circuitry of claim 1, wherein the switching circuitry comprises a butterfly switch.
7. The circuitry of claim 1, wherein: the first core has first and second terminals, the first inductor is coupled between the first and second terminals, the second core has third and fourth terminals, the second inductor is coupled between the third and fourth terminals, and the switching circuitry couples the first and second terminals to the third and fourth terminals.
8. The circuitry of claim 7, wherein the switching circuitry comprises: a first switch that couples the first terminal to the third terminal; a second switch that couples the second terminal to the fourth terminal; a third switch that couples the first terminal to the fourth terminal; and a fourth switch that couples the second terminal to the third terminal.
9. The circuitry of claim 8, further comprising: a first capacitor coupled between the first terminal and the third terminal in parallel with the first switch; and a second capacitor coupled between the second terminal and the fourth terminal in parallel with the second switch.
10. The circuitry of claim 1, further comprising: first and second capacitors coupled between the first core and the second core in parallel with the switching circuitry.
11. The circuitry of claim 1, wherein the switching circuitry is configured to reverse a current direction in the second core.
12. The circuitry of claim 1, further comprising: a third core; a third inductor operably coupled to the third core; and additional switching circuitry coupled between the first core and the third core.
13. Circuitry comprising: a first oscillator having first and second terminals; a second oscillator having third and fourth terminals; and a butterfly switch that couples the first and second terminals to the third and fourth terminals.
14. The circuitry of claim 13, wherein the circuitry is configured to output a clocking signal and the butterfly switch is configured to adjust a frequency range of the clocking signal.
15. The circuitry of claim 14, wherein the first oscillator is configured to receive a voltage that adjusts a frequency of the clocking signal within the frequency range.
16. The circuitry of claim 13, wherein the butterfly switch is configured to reverse a current direction in the first and second oscillators.
17. An integrated circuit chip comprising: a first oscillator; a second oscillator; a third oscillator; first switching circuitry that operably couples the first oscillator to the second oscillator; and second switching circuitry that operably couples the first oscillator to the third oscillator.
18. The integrated circuit chip of claim 17, further comprising: a fourth oscillator; third switching circuitry that operably couples the third oscillator to the fourth oscillator; and fourth switching circuitry that operably couples the second oscillator to the fourth oscillator.
19. The integrated circuit chip of claim 17, wherein: the first oscillator comprises a first conductive loop, the second oscillator comprises a second conductive loop, the first switching circuitry has first and second states, a first current flows through the first conductive loop in a first direction and a second current flows through the second conductive loop in a second direction opposite the first direction while the switching circuitry is in the first state, and the first current flows through the first conductive loop in the first direction and the second current flows through the second conductive loop in the second direction while the switching circuitry is in the second state.
20. The integrated circuit chip of claim 17, wherein the first oscillator comprises a first voltage controlled oscillator (VCO), the second oscillator comprises a second VCO, the third oscillator comprises a third VCO, the first, second, and third VCOs are configured to output an oscillator signal, and the first switching circuitry and the second switching circuitry are configured to adjust a frequency range of the oscillator signal.
1. Clocking circuitry comprising: a first oscillator having a first terminal and a second terminal; a second oscillator having a third terminal and a fourth terminal; a third oscillator; a first switch that couples the first terminal to the fourth terminal; a second switch that couples the second terminal to the third terminal; and a third switch that couples the second terminal to the third oscillator.
2. The clocking circuitry of claim 1, further comprising: a fourth switch that couples the first terminal to the third terminal.
3. The clocking circuitry of claim 2, further comprising: a fifth switch that couples the second terminal to the fourth terminal.
4. The clocking circuitry of claim 1, wherein the first oscillator comprises a first inductor coupled between the first terminal and the second terminal.
5. The clocking circuitry of claim 4, wherein the second oscillator comprises a second inductor coupled between the third terminal and the fourth terminal.
6. The clocking circuitry of claim 5, further comprising: a fourth switch that couples the first terminal to the third terminal; and a fifth switch that couples the second terminal to the fourth terminal.
7. The clocking circuitry of claim 1, wherein the first terminal comprises a positive terminal of the first oscillator, the second terminal comprises a negative terminal of the first oscillator, the third terminal comprises a positive terminal of the second oscillator, and the fourth terminal comprises a negative terminal of the second oscillator.
8. The clocking circuitry of claim 7, further comprising: a fourth switch that couples the positive terminal of the first oscillator to the positive terminal of the second oscillator; and a fifth switch that couples the negative terminal of the first oscillator to the negative terminal of the second oscillator.
9. The clocking circuitry of claim 1, further comprising: a first capacitor that couples the first terminal to the third terminal.
10. The clocking circuitry of claim 9, further comprising: a second capacitor that couples the second terminal to the fourth terminal.
11. The clocking circuitry of claim 10, further comprising: a fourth switch that couples the first terminal to the third terminal; and a fifth switch that couples the second terminal to the fourth terminal.
12. The clocking circuitry of claim 1, the first oscillator including a first voltage controlled oscillator (VCO) core having the first terminal and the second terminal and the second oscillator including a second VCO core having the third terminal and the fourth terminal.
13. The clocking circuitry of claim 12, the first oscillator including a first inductor coupled between the first terminal and the second terminal, and the second oscillator including a second inductor coupled between the third terminal and the fourth terminal.
14. The clocking circuitry of claim 1, wherein the third oscillator has a fifth terminal and a sixth terminal, the third switch couples the fifth terminal to the second terminal, and the clocking circuitry further comprises: a fourth switch that couples the sixth terminal to the first terminal; a fourth oscillator having a seventh terminal and an eighth terminal; a fifth switch that couples the seventh terminal to the fourth terminal; a sixth switch that couples the eighth terminal to the third terminal; a seventh switch that couples the seventh terminal to the sixth terminal; and an eighth switch that couples the eighth terminal to the fifth terminal.
15. Wireless circuitry comprising: a first voltage controlled oscillator (VCO) having first terminals; a second VCO having second terminals; a first butterfly switch that couples the first terminals to the second terminals; a third VCO having third terminals; and a second butterfly switch that couples the third terminals to the first terminals.
16. The wireless circuitry of claim 15, further comprising: a first conductive loop coupled between the first terminals; and a second conductive loop coupled between the second terminals.
17. The wireless circuitry of claim 15, further comprising: a fourth VCO having fourth terminals; a third butterfly switch that couples the fourth terminals to the second terminals; and a fourth butterfly switch that couples the fourth terminals to the third terminals.
18. An electronic device comprising: one or more antennas configured to convey a radio-frequency signal; a mixer configured to operate on the radio-frequency signal based on an oscillator signal; and clocking circuitry configured to generate the oscillator signal, the clocking circuitry including a first voltage controlled oscillator (VCO) core having a first positive terminal and a first negative terminal, a first inductor coupled between the first positive terminal and the first negative terminal, a second VCO core having a second positive terminal and a second negative terminal, a second inductor coupled between the second positive terminal and the second negative terminal, a first switch that couples the first positive terminal to the second positive terminal, a second switch that couples the first positive terminal to the second negative terminal, and a third VCO core coupled to the first VCO core by at least one switch.
19. The electronic device of claim 18, wherein the clocking circuitry further comprises: a third switch that couples the first negative terminal to the second negative terminal; and a fourth switch that couples the second positive terminal to the first negative terminal.
20. The electronic device of claim 18, wherein the third VCO core has a third positive terminal and a third negative terminal, the electronic device further comprising: a third switch that couples the third positive terminal to the first negative terminal.
In light of the above it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have recognized that the oscillator circuit as claimed, presently, with switching to couple respective oscillators, is simply a broader presentation of the VCO(oscillators) and butterfly switches to couple the respective oscillator terminals as previously patented. The integration of such elements being a simple matter of design consideration for a compact arrangement.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13-16 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Farazian et al US 20160373057.
Re claims 1 and 13:
The reference to Farazian et al discloses a clocking circuit. The IC circuit comprises a 1st VCO oscillator/core and 2nd VCO oscillator/core. See figure 2B below. A 1st Inductor (L1)is shown in the 1st VCO between 1st and 2nd terminals. The switching network forms a ‘butterfly’ switch due to the balanced couplings to be highlighted. A 2nd Inductor(L2) is shown coupled in the 2nd VCO between the 3rd and 4th terminals
A 4th SW(switching circuitry) is shown coupling the neg(-) of 1st VCO and the neg(-) of the 2nd VCO.
A 1st SW is shown coupling the 1st terminal and the 3rd terminal. A 2nd SW is shown coupling the 2nd and 4th terminals.
The 1st VCO is shown with 1st and 2nd terminals; the 2nd VCO is shown with 3rd and 4th terminals.
The switching action allows for current direction in the cores to allow for the out of phase signal outputs, that is, constantly switching current direction to maintain energy balance and the 90° phase separation between the two oscillator cores.
Re claim 2: The 2nd VCO will output and oscillator signal(s) see sine wave output representation on either side of 2nd core oscillator. AS noted in para [0003] “Dual-band VCOs may employ two oscillator cores and operate in two frequency bands, for example in a range of about 2.4-4.0 GHz (low band) and a range of about 3.3-5.6 GHz (high band) and may operate in even mode (i.e., with the output signals of the two cores in-phase) or odd mode (i.e., with the output signals of the two cores out-of-phase). Conventional dual-band VCOs may have two VCO cores with re-channel metal-oxide semiconductor (NMOS) cross-coupled transistors. However, cross-coupled NMOS VCO architectures may require high operating currents. Further, conventional dual-band VCOs may become unstable, i.e., the VCO may oscillate at more than one frequency during high-band and/or low-band operation.”
Re claim 3:
a first voltage controlled oscillator ( 1st coreVCO) that includes the first core(transistors(222a,b) and LC circuit) and the first inductor(L1).
Re claim 4:
a second VCO (2nd core oscillator)that includes the second core(transistors(272a,b) and LC circuit) and the second inductor.
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Re claim 5, 14 and 15: The ability to use the switching circuit to switch cores depending on the frequency band desired, that is, when the switching in a particular state allows for the 1st core oscillator to operate and then in the other state to allow the 2nd core to oscillate at a particular clock output signal, in band, is inherent to the configuration as described. The tuning caps (C1,C2)allow in band tuning.
Re claim 6. The circuitry of claim 1, wherein the switching circuitry comprises a ‘butterfly’ switch as described above.
Re claim 7:
Please note the +/- terminal indicators on the oscillator terminals(consistent with the inductor coupling dots). The first core has first and second terminals, the first inductor(L1) is coupled between the first and second terminals, the second core has third and fourth terminals, the second inductor(L2) is coupled between the third and fourth terminals, and the switching circuitry couples the first and second terminals to the third and fourth terminals. A 1st SW is shown coupling the 1st terminal (T1)and the 3rd terminal(T3). A 2nd SW is shown coupling the 2nd terminal(T2) and 4th terminal(T4).
Re claim 8:
A 1st SW is shown coupling the 1st terminal (T1)and the 3rd terminal(T3). A 2nd SW is shown coupling the 2nd (T2)and 4th (T4)terminals. A 3rd SW is shown between the 1st and 4th terminals, and a 4th SW is shown between the 2nd (T2)and 3rd terminals(T3).
The 1st VCO is shown with 1st and 2nd terminals; the 2nd VCO is shown with 3rd and 4th terminals.
Re claim 9:
A first capacitor (225)coupled between the first terminal ( T1 ) and the third terminal (T3)in parallel with the first switch; and a second capacitor(230) coupled between the second terminal (T2)and the fourth terminal(T4) in parallel with the second switch.
Re claim 10: first(225) and second capacitor(230) coupled between the first core and the second core in parallel with the switching circuitry, SW1 and SW2, respectively.
Re claims 11 and 16: the switching circuitry(and oscillator configuration) provides for reverse current direction in the first and second core(oscillators)(as noted for claim 1).
Allowable Subject Matter
Claims 12, 19 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARNOLD M KINKEAD whose telephone number is (571)272-1763. The examiner can normally be reached M-F 7am-5:30pm(Fri-Flex).
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ARNOLD M. KINKEAD
Primary Examiner
Art Unit 2849
/ARNOLD M KINKEAD/Primary Examiner, Art Unit 2849