Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the application filed on 10/23/2024.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/23/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Appropriate correction is required.
Claim Objections
Claims 7, 10, 13, 16, and 18 are objected to because of the following informalities:
Regarding claim 7, in line 2, “the regulator control hardware logic” appears that it should read as “the regulator controlling circuit”.
Regarding claim 10, in line 2-3, “the first control signal” appears that it should read as “the control signal”.
Regarding claim 13, in line 2, “the memory subsystem” appears that it should read as “the memory”.
Regarding claim 16, in line 4, “a first supply and a second supply” appears that it should read as “a first supply terminal and a second supply terminal”.
Regarding claim 18, in line 3, “first pass transistor” appears that it should read as “the first transistor”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 16, 19, 20, 21, 22, 24, and 27 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Boecker et al. (US Patent Application Publication US 2024/0004449 A1, hereinafter “Boecker”).
Regarding claim 16, Boecker discloses (see Fig. 1 and Fig. 2) a circuit (domain control circuit 200) comprising: a clock gate controlling circuit (sequencing circuit 204); a clock gate (the clock gate of the clock distribution tree CLKTREE that gates the system clock SYSCLK to domain 106(1), see Fig. 1) coupled to the clock gate controlling circuit; a regulator (power regulator 202) coupled to a first supply (supply voltage node 220) and a second supply (power rail 208), the regulator including a first transistor (first transistor 228) configured to carry current on a path between the first supply terminal and the second supply terminal (the first transistor 228 couples the supply voltage node 220 to the intermediate node 230 on the current path to the power rail 208); and a regulator controlling circuit (regulator control circuit 224) coupled to the regulator and to the clock gate controlling circuit, wherein: the clock gate controlling circuit is configured to transmit a control signal (clock gate signal 218) to the clock gate; and the clock gate controlling circuit is coupled to a first input of the regulator (the input of the regulator control circuit 224 that receives the power control signal 216), wherein the clock gate controlling circuit is configured to apply a voltage (power control signal 216) to the first input of the regulator to change the current based on the control signal (see [0021] “the sequencing circuit 204 first generates a power control signal 216 to control the regulator circuits 210(1)-210(N) to supply power on the power rail 208”, the power control signal 216 and the clock gate signal 218 both being generated from the domain control signal DM-CTL).
Regarding claim 19, Boecker discloses (see Fig. 2) a clock requesting circuit (the always-on domain that provides the domain control signal DM-CTL) coupled to the clock gate controlling circuit, wherein the clock requesting circuit is configured to generate a clock request signal (domain control signal DM-CTL on input 212) to the clock gate controlling circuit (see [0021] “The domain control signal DM-CTL may be provided to the domain control circuit 200 from an always-on domain”).
Regarding claim 20, Boecker discloses (see Fig. 2) wherein the clock gate controlling circuit is configured to generate the control signal (clock gate signal 218) in response to the clock request signal (the sequencing circuit 204 generates the clock gate signal 218 in response to activation of the domain control signal DM-CTL).
Regarding claim 21, Boecker discloses (see Fig. 2 and Fig. 4) a controller circuit (processor 402) coupled to the clock gate controlling circuit; and a memory (main memory 408 comprising memory array 416) coupled to the controller circuit and to the clock gate, wherein the controller circuit is configured to transmit a clock request signal (domain control signal DM-CTL) to the clock gate controlling circuit, and wherein the clock gate controlling circuit is configured to generate the control signal (clock gate signal 218) in response to the clock request signal to cause a clock (domain clock signal) to be provided to the memory via the clock gate (see [0034] “Any of the circuits in the processor-based system 400 may include a domain control circuit 200”).
Regarding claim 22, Boecker discloses (see Fig. 2 and Fig. 4) wherein the clock gate and the memory are configured to be powered by the regulator (powered on the power rail 208 by the regulator circuits 210(1)-210(N)), and wherein the controller circuit is configured to be powered by a power supply separate from the regulator (the processor 402 is powered in an always-on domain that remains active while the first domain DM1 is deactivated, see [0020]).
Regarding claim 24, Boecker discloses (see Fig. 2 and Fig. 4) a controller circuit (processor 402) coupled to the clock gate controlling circuit, wherein the controller circuit is configured to transmit a clock request signal (domain control signal DM-CTL) to the clock gate controlling circuit, and wherein the clock gate controlling circuit is configured to generate the control signal (clock gate signal 218) in response to the clock request signal.
Regarding claim 27, Boecker discloses (see Fig. 1 and Fig. 2) wherein the clock gate comprises a first clock gate (the clock gate gating SYSCLK to domain 106(1) per clock gate signal CKGT1(1)) and the control signal comprises a first control signal (clock gate signal CKGT1(1)), and wherein the circuit further comprises a second clock gate (the clock gate gating SYSCLK to domain 106(2) per clock gate signal CKGT1(2)), wherein the second clock gate is coupled to the clock gate controlling circuit, further wherein the clock gate controlling circuit is configured to transmit a second control signal (clock gate signal CKGT1(2)) to the second clock gate and is further configured to change the current based on the second control signal (the second sequencing circuit 254 generates the second power control signal 256 to control the regulator circuits 250(1)-250(Y), see [0028]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2, 3, 4, 6, 7, 8, 9, 10, 11, 15, and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Boecker in view of Xi (US Patent Application Publication US 2003/0178976 A1).
Regarding claim 1, Boecker discloses (see Fig. 1 and Fig. 2) a circuit (domain control circuit 200) comprising: a clock gate controlling circuit (sequencing circuit 204); a first clock gate (the clock gate of the clock distribution tree CLKTREE that gates the system clock SYSCLK to domain 106(1), see Fig. 1) coupled to the clock gate controlling circuit; a regulator (power regulator 202); and a regulator controlling circuit (regulator control circuit 224) coupled to the regulator and to the clock gate controlling circuit, wherein the clock gate controlling circuit is configured to transmit a control signal (clock gate signal 218) to the first clock gate and to cause the regulator controlling circuit to change a setting of the regulator in response to the control signal (the sequencing circuit 204 generates the power control signal 216 to cause the regulator control circuit 224 to control the number of regulator circuits 210(1)-210(N) that are activated to supply power on the power rail 208, in coordination with the clock gate signal 218 generated from the same domain control signal DM-CTL).
Boecker does not disclose wherein the clock gate controlling circuit is configured to cause the regulator controlling circuit to change a bandwidth of the regulator in response to the control signal.
However, Xi teaches (see Fig. 2) causing a regulator controlling circuit (threshold detection and bias current adjustment circuit 266) to change a bandwidth of the regulator (see [0019] the circuit 266 “provides a slow adjustment to the bias level of the three amplifiers 204, 216 and 228 so that they will have a higher bandwidth and a faster slew rate”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Boecker to cause the regulator controlling circuit to change a bandwidth of the regulator in response to the control signal, as taught by Xi, because it can help the regulator respond quickly to the surge in power consumption that occurs when the clock signal is activated in the domain, thereby reducing the voltage droop on the power rail without destabilizing the control loop.
Regarding claim 2, Boecker does not disclose wherein the regulator comprises a low dropout (LDO) voltage regulator having a pass transistor, wherein the regulator controlling circuit is configured to increase the bandwidth by increasing a current through the pass transistor.
However, Xi teaches (see Fig. 2) wherein the regulator comprises a low dropout (LDO) voltage regulator (LDO regulator 200) having a pass transistor (PMOS power transistor 256), wherein the regulator controlling circuit (threshold detection and bias current adjustment circuit 266) is configured to increase the bandwidth by increasing a current through the pass transistor (see [0023] “increasing the bias current to the drive amplifiers for both the SLEEP mode pass transistor and ON mode pass transistor”, thereby increasing the bandwidth and the current through the pass transistor 256).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the regulator of Boecker to comprise a low dropout (LDO) voltage regulator having a pass transistor and to increase the bandwidth by increasing a current through the pass transistor, as taught by Xi, because it can help provide a regulated output voltage with a low input-to-output differential while quickly responding to load transients.
Regarding claim 3, Boecker discloses (see Fig. 1) an oscillator (the source that generates the system clock signal SYSCLK) coupled to the first clock gate, wherein the first clock gate is configured to pass a first clock signal (system clock SYSCLK) from the oscillator in response to the control signal (see [0015] “the clock distribution tree CLKTREE distributes a domain clock CLK-D1(1) to each of a plurality of digital circuits 114(1)-114(4) in domain 106(1)” when the clock gate signal is deactivated).
Regarding claim 4, Boecker discloses (see Fig. 1 and Fig. 2) wherein the first clock gate is configured to be powered by a first power domain (the first domain DM1 powered on the power rail 208), and wherein the oscillator is configured to be powered by a second power domain (the always-on domain that remains active during a low-power mode, see [0020]).
Regarding claim 6, Boecker discloses (see Fig. 2) a capacitor (capacitor 222) coupled to the regulator (the capacitor 222 is coupled between the power rail 208 and ground GND).
Boecker does not disclose wherein the regulator is configured to drain charge from the capacitor in response to the bandwidth of the regulator being increased.
However, Xi teaches (see Fig. 2) a regulator configured to drain charge from a capacitor (filter capacitor 294) in response to the bandwidth of the regulator being increased (see [0019] when the bias current adjustment provides “a higher bandwidth and a faster slew rate” to respond to the larger load, the output capacitor supplies and is drained of charge to support the load transient).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Boecker so that the regulator drains charge from the capacitor in response to the bandwidth of the regulator being increased, as taught by Xi, because it can help supply transient load current and maintain the regulated output voltage during the high-current mode.
Regarding claim 7, Boecker does not disclose wherein the regulator comprises a low dropout (LDO) voltage regulator having a bias transistor, wherein the regulator control hardware logic is configured to increase the bandwidth by increasing a current through the bias transistor.
However, Xi teaches (see Fig. 2 and Fig. 4) wherein the regulator comprises a low dropout (LDO) voltage regulator (LDO regulator 200) having a bias transistor (bias transistor M13 that supplies bias current to the large current drive amplifier 428), wherein the regulator control hardware logic (threshold detection and bias current adjustment circuit 266) is configured to increase the bandwidth by increasing a current through the bias transistor (see [0022] the signal EN HPM FAST “connects transistor M15 in parallel with transistor M13 to increase the current to the large current drive amplifier 428”, increasing the bandwidth).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the regulator of Boecker to comprise a low dropout (LDO) voltage regulator having a bias transistor and to increase the bandwidth by increasing a current through the bias transistor, as taught by Xi, because it can help the regulator increase its bandwidth and slew rate to respond quickly to the increased load when the clock is activated.
Regarding claim 8, Boecker does not disclose wherein the regulator controlling circuit is configured to increase the current through the bias transistor by adjusting a voltage applied to a control terminal of the bias transistor.
However, Xi teaches (see Fig. 4) wherein the regulator controlling circuit (threshold detection and bias current adjustment circuit 266) is configured to increase the current through the bias transistor by adjusting a voltage applied to a control terminal of the bias transistor (the signal EN HPM FAST is applied to the gate of switching transistor SW2 to connect transistor M15, increasing the bias current; see [0022] of Xi).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Boecker to increase the current through the bias transistor by adjusting a voltage applied to a control terminal of the bias transistor, as taught by Xi, because it can help controllably increase the bias current and the bandwidth of the regulator.
Regarding claim 9, Boecker does not disclose wherein the regulator controlling circuit is configured to increase the current through the bias transistor by turning on a switch in series with the bias transistor.
However, Xi teaches (see Fig. 4) wherein the regulator controlling circuit is configured to increase the current through the bias transistor by turning on a switch in series with the bias transistor (the switching transistor SW2, when turned on, connects bias transistor M15 in series therewith and in parallel with M13 to increase the current to the drive amplifier 428; see [0022] of Xi).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Boecker to increase the current through the bias transistor by turning on a switch in series with the bias transistor, as taught by Xi, because it can help selectively boost the bias current to increase the regulator bandwidth on demand.
Regarding claim 10, Boecker does not disclose wherein the regulator controlling circuit is further configured to revert the bandwidth of the regulator to a prior setting in response to a state of the first control signal.
However, Xi teaches (see Fig. 2 and Fig. 6C-6D) wherein the regulator controlling circuit is further configured to revert the bandwidth of the regulator to a prior setting (the regulator switches from the ON mode back to the SLEEP mode, reverting the bias level and the bandwidth, when the output current decreases) in response to a state of the control signal.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Boecker to revert the bandwidth of the regulator to a prior setting in response to a state of the first control signal, as taught by Xi, because it can help reduce quiescent current and power consumption when the higher bandwidth is no longer needed, such as when the clock is gated off.
Regarding claim 11, Boecker discloses (see Fig. 2) wherein the regulator is configured to power the clock gate controlling circuit and the first clock gate (the power regulator 202, including the always-on regulator circuit 206, provides power on the power rail 208 to the always-on domain that includes the sequencing circuit 204 and the clock gate, see [0019]-[0020]).
Regarding claim 15, Boecker discloses (see Fig. 1 and Fig. 2) a second clock gate (the clock gate gating SYSCLK to domain 106(2) per clock gate signal CKGT1(2)) coupled to the clock gate controlling circuit, wherein the clock gate controlling circuit is configured to transmit a second control signal (clock gate signal CKGT1(2)) to the second clock gate and to cause the regulator controlling circuit to change a setting of the regulator in response to the second control signal (via the second sequencing circuit 254 and regulator circuits 250(1)-250(Y), see [0028]).
Boecker does not disclose to cause the regulator controlling circuit to change the bandwidth of the regulator in response to the second control signal.
However, Xi teaches (see Fig. 2) changing the bandwidth of the regulator (the threshold detection and bias current adjustment circuit 266 provides “a higher bandwidth and a faster slew rate”, see [0019] of Xi).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Boecker to cause the regulator controlling circuit to change the bandwidth of the regulator in response to the second control signal, as taught by Xi, because it can help the regulator respond to the additional load of the second domain when its clock is activated, reducing voltage droop.
Regarding claim 26, Boecker does not disclose wherein the regulator comprises a low dropout (LDO) voltage regulator.
However, Xi teaches (see Fig. 2) wherein the regulator comprises a low dropout (LDO) voltage regulator (LDO regulator 200; see [0003] “A low drop-out (LDO) regulator is a linear regulator which utilizes a transistor or FET to generate a regulated output voltage with very low differential between the input voltage and the output voltage”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the regulator of Boecker to comprise a low dropout (LDO) voltage regulator, as taught by Xi, because it can help generate a regulated output voltage with a very low input-to-output voltage differential, conserving power.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Boecker in view of Xi, and further in view of Al-Shyoukh et al. (US Patent Application Publication US 2009/0160410 A1, hereinafter “Al-Shyoukh”).
Regarding claim 5, Boecker discloses (see Fig. 2) wherein the first power domain is configured to be powered via the regulator (the first domain DM1 is powered on the power rail 208 by the power regulator 202), and wherein the second power domain comprises a supply powered power domain (the always-on domain powered by the supply voltage VDD, see [0019]-[0020]).
Boecker does not disclose wherein the first power domain comprises a battery-powered power domain.
However, Al-Shyoukh teaches (see Fig. 1) wherein the first power domain comprises a battery-powered power domain configured to be powered via the regulator (see [0018] “The RTC voltage regulator 110 uses the operating voltage from the battery 180 to provide an RTC voltage rail” for the RTC circuitry 170).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Boecker so that the first power domain comprises a battery-powered power domain powered via the regulator, as taught by Al-Shyoukh, because it can help maintain operation of the first power domain from a battery during a power outage or a low-power mode, extending battery life.
Claims 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Boecker in view of Xi, and further in view of Voisine (US Patent Application Publication US 2010/0283452 A1).
Regarding claim 12, Boecker does not disclose wherein the circuit comprises a meter having a real-time clock (RTC) subsystem, wherein the first clock gate is implemented within the RTC subsystem.
However, Voisine teaches (see Fig. 1) wherein the circuit comprises a meter (electricity meter within meter housing 16) having a real-time clock (RTC) subsystem (see [0003] “Meters employing time-of-use” metering employ a real time clock that develops and maintains real-time clock information and provides the clock output 12).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to implement the first clock gate of Boecker within the RTC subsystem of the electricity meter of Voisine, because it can help selectively gate the clock to the RTC subsystem of the meter to conserve power while reducing voltage droop when the clock is reactivated.
Regarding claim 13, Boecker does not disclose wherein the circuit comprises a meter having a memory, wherein the first clock gate is implemented within the memory subsystem.
However, Voisine teaches (see Fig. 1 and Fig. 5) wherein the circuit comprises a meter (electricity meter within meter housing 16) having a memory (the processing circuit 15 that stores and communicates metering data, see [0023]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to implement the first clock gate of Boecker within the memory subsystem of the meter of Voisine, because it can help selectively gate the clock to the memory of the meter to conserve power while reducing voltage droop when the clock is reactivated.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Boecker in view of Xi, and further in view of Maxim (Maxim Integrated Application Note 3816, “Selecting a Backup Source for Real-Time Clocks”, 2013, hereinafter “Maxim”).
Regarding claim 14, Boecker discloses (see Fig. 2) wherein the regulator is configured to output power to the first clock gate (the power regulator 202 provides power on the power rail 208 to the domain that includes the clock gate).
Boecker does not disclose wherein the regulator is coupled to a coin cell battery.
However, Maxim teaches a regulated backup arrangement coupled to a coin cell battery for powering a real-time clock (see p. 2 section “Lithium Primary (BR and CR) Cells”: “Primary lithium coin cells are commonly used for RTC and memory backup”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to couple the regulator of Boecker to a coin cell battery to output power to the first clock gate, as taught by Maxim, because it can help maintain timekeeping and clocked operation from a compact, long-life backup source when primary power is unavailable.
Claims 23 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Boecker in view of Al-Shyoukh.
Regarding claim 23, Boecker does not disclose wherein the regulator is configured to be powered in a battery-powered domain.
However, Al-Shyoukh teaches (see Fig. 1) wherein the regulator is configured to be powered in a battery-powered domain (the RTC voltage regulator 110 receives the operating voltage from the battery 180 at the input node 120; see [0015]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Boecker so that the regulator is powered in a battery-powered domain while the controller circuit is powered in another power domain, as taught by Al-Shyoukh, because it can help operate the regulated domain from a battery during a power-down of the remainder of the circuit, conserving power.
Regarding claim 25, Boecker does not disclose wherein the clock gate is disposed within a real-time clock (RTC) system, wherein the regulator comprises a power output coupled to a power input of the RTC system.
However, Al-Shyoukh teaches (see Fig. 1) a real-time clock (RTC) system (RTC circuitry 170 of the RTC module 160, comprising a crystal oscillator and associated logic), wherein the regulator comprises a power output (output node 130 providing the RTC voltage VRTC) coupled to a power input of the RTC system (see [0016] “The RTC voltage regulator 110 is coupled to RTC circuitry 170 via the output node 130 of the PMIC 100”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to dispose the clock gate of Boecker within the RTC system of Al-Shyoukh and couple the power output of the regulator to the power input of the RTC system, because it can help provide a regulated, reliable voltage to the RTC system so the clock can be selectively gated while maintaining timekeeping.
Allowable Subject Matter
Claims 17, 18, and 28 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 17, none of the cited prior art alone or in combination discloses or teaches the claimed invention in which “the first supply terminal is coupled to a battery power source; and wherein the regulator further comprises: a second transistor coupled to the first transistor and to the second supply terminal, wherein the first input is coupled to a third transistor in series with the second transistor”.
Regarding claim 18, none of the cited prior art alone or in combination discloses or teaches the claimed invention in which “the first supply terminal is coupled to a battery power source; and wherein the regulator further comprises: a second transistor coupled to first pass transistor and the second supply terminal, wherein the first input is coupled to a control terminal of the second transistor”.
Regarding claim 28, none of the cited prior art alone or in combination discloses or teaches the claimed invention in which “the clock gate controlling circuit comprises an OR gate having a first input configured to receive the first control signal and a second input configured to receive the second control signal, and an output coupled to the regulator controlling circuit”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 2010/0085817 A1 discloses a semiconductor memory device that controls an internal voltage generating unit in accordance with the logical combination of a first enable signal and a second enable signal.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JYE-JUNE LEE whose telephone number is (571)270-7726. The examiner can normally be reached on M-F 9 AM - 5 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached on 5712721838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MONICA LEWIS/ Supervisory Patent Examiner, Art Unit 2838
/JYE-JUNE LEE/Examiner, Art Unit 2838
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