DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. Claims 1-20 are pending.
Priority
3. Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Receipt is acknowledged of certified copies or papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
4. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
6. Claims 1, 2, 10, 11, 16 and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gim et al. (US Pub. No. 2023/0401120 A1 hereinafter “Gim”).
Referring to claim 1, Gim discloses a computing device (Gim – Fig. 2, host device 102) comprising:
a processor (Gim – Fig. 2, processor 206);
a memory (Gim – Fig. 2, memory 208); and
a root complex configured to be connected with the processor, the memory, and a memory expander (Gim – Par. [0061] & Fig. 2, The root complex 202 may connect (e.g., via a local bus or the like) the processing circuit 204 (comprises of the processor 206 and the memory 208) to the expandable memory device 118 via the second memory interface 116.),
wherein the processor (Gim – Fig. 2, processor 206) is configured to:
recognize whether the memory expander is connected to the root complex, and update a physical address space of the computing device based on a recognition that the memory expander is connected to the root complex (Gim – Par. [0044] discloses the host physical address may be changed when the expandable memory is plugged into a different slot of the host device, or the expandable memory expander card is plugged into a slot of a different host device. Par. [0059] discloses the expandable memory device 118 may be connected to a port (e.g., a PCIe port) of a root complex 202 (e.g., via the second memory interface 116) of the host device 102.).
Referring to claim 2, Gim discloses the computing device of claim 1, wherein the root complex is configured to connect the processor, the memory, and the memory expander through a compute express link (CXL) protocol-based interconnect (Gim – Par. [0061] & Fig. 2, The root complex 202 may connect (e.g., via a local bus or the like) the processing circuit 204 (comprises of the processor 206 and the memory 208) to the expandable memory device 118 via the second memory interface 116 (e.g., the connector and the protocol thereof) may include (e.g., may conform to) a CXL interconnect built on periphery component interconnect express (PCIe), such that the expandable memory device 118 may be a PCIe device connected to a PCIe port of the root complex 202.).
Referring to claim 10, note the rejections of claim 1 above. The Instant Claim recites substantially same limitations as the above-rejected with the addition of a plurality of memory expanders (Gim – Fig. 5, Expandable Memory Pool 114) and is therefore rejected under same prior-art teachings.
Referring to claim 11, note the rejections of claim 2 above. The Instant Claim recites substantially same limitations as the above-rejected and is therefore rejected under same prior-art teachings.
Referring to claim 16, note the rejections of claim 1 above. The Instant Claim recites substantially same limitations as the above-rejected and is therefore rejected under same prior-art teachings.
Referring to claim 17, note the rejections of claim 2 above. The Instant Claim recites substantially same limitations as the above-rejected and is therefore rejected under same prior-art teachings.
Claim Rejections - 35 USC § 103
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
8. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
9. Claims 3-9, 12-15 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Bains in view of Jung et al. (US Pub. No. 2024/0264957 A1 hereinafter “Jung”).
Referring to claim 3, Gim discloses the computing device of claim 1, wherein the root complex (Gim – Par. [0061] & Fig. 2, The root complex 202) comprises:
a root port configured to be connected with the memory expander (Gim – Par. [0061] & Fig. 2, The root complex 202 may connect (e.g., via a local bus or the like) the processing circuit 204 (comprises of the processor 206 and the memory 208) to the expandable memory device 118 via the second memory interface 116 (e.g., the connector and the protocol thereof) may include (e.g., may conform to) a CXL interconnect built on periphery component interconnect express (PCIe), such that the expandable memory device 118 may be a PCIe device connected to a PCIe port of the root complex 202.).
Gim fails to explicitly disclose a CXL controller configured to transmit/receive data to/from the memory expander connected with the root port, and the root port and the CXL controller correspond to each other and are paired.
Jung discloses a CXL controller configured to transmit/receive data to/from the memory expander connected with the root port (Jung– Par. [0089-0097] & Fig. 8, a CXL controller 311A configured to transmit/receive data to/from the memory expander (storage 13A) connected with the CXL root port 210A.), and the root port and the CXL controller correspond to each other and are paired (Jung – Fig. 8, CXL root port 210A coupled directly with the CXL controller 311A via CXL EP 313A.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Jung’s teachings with Gim’s techniques for the benefit of the storage such as SSD can be used as the cacheable memory expander, improving the performance of a wide range of applications requiring a large-capacity memory, such as large-scale scientific analysis, healthcare, recommendation systems, and machine learning-based autonomous vehicle (Jung – Par. [0026]).
Referring to claim 4, Gim and Jung disclose the computing device of claim 3, wherein the processor (Gim – Fig. 2, processor 206) is configured to: identify a root port to which the memory expander is connected based on the recognition that the memory expander is connected to the root complex, and update the physical address space of the computing device based on the root port to which the memory expander is connected (Gim – Par. [0044] discloses the host physical address may be changed when the expandable memory is plugged into a different slot of the host device, or the expandable memory expander card is plugged into a slot of a different host device. Par. [0059] discloses the expandable memory device 118 may be connected to a port (e.g., a PCIe port) of a root complex 202 (e.g., via the second memory interface 116) of the host device 102.).
Referring to claim 5, Gim and Jung disclose the computing device of claim 4, wherein the processor (Gim – Fig. 2, processor 206) is configured to map the root port to which the memory expander is connected to a physical address included in the physical address space of the computing device (Gim – Par. [0044] discloses the host physical address may be changed when the expandable memory is plugged into a different slot of the host device, or the expandable memory expander card is plugged into a slot of a different host device. In this case, the FPL including at least the physical device information of the expandable memory may enable remapping from the device physical address to the host physical address when such hardware changes are made. Par. [0059] discloses the expandable memory device 118 may be connected to a port (e.g., a PCIe port) of a root complex 202 (e.g., via the second memory interface 116) of the host device 102.).
Referring to claim 6, Gim and Jung disclose the computing device of claim 3, wherein the processor is configured to generate a memory request (Gim – Par. [0059] & Fig. 2, the root complex 202 may connect a processor 206 (e.g., the host processor 106 in FIG. 1) to the expandable memory device 118 to generate transaction requests on behalf of the processor 206 to the expandable memory device 118.), and the root complex is configured to access a memory expander corresponding to a physical address of the memory request through the updated physical address space, based on the memory request (Gim – Par. [0061] & Fig. 2, The root complex 202 may connect (e.g., via a local bus or the like) the processing circuit 204 (comprises of the processor 206 and the memory 208) to the expandable memory device 118 via the second memory interface 116 (e.g., the connector and the protocol thereof) may include (e.g., may conform to) a CXL interconnect built on periphery component interconnect express (PCIe), such that the expandable memory device 118 may be a PCIe device connected to a PCIe port of the root complex 202.).
Referring to claim 7, Gim and Jung disclose the computing device of claim 6, wherein the root complex is configured to identify the memory expander corresponding to the physical address of the memory request on the updated physical address space, based on the memory request (Gim – Par. [0044] discloses the host physical address may be changed when the expandable memory is plugged into a different slot of the host device, or the expandable memory expander card is plugged into a slot of a different host device. Par. [0059] discloses the expandable memory device 118 may be connected to a port (e.g., a PCIe port) of a root complex 202 (e.g., via the second memory interface 116) of the host device 102.).
Referring to claim 8, Gim and Jung disclose the computing device of claim 7, wherein the root complex is configured to transmit the memory request to the root port connected with the memory expander corresponding to the physical address of the memory request, based on the identifying (Jung– See Par. [0089-0097] & Fig. 8, Steps S210 – S240.).
Referring to claim 9, Gim and Jung disclose the computing device of claim 8, wherein the root port connected with the memory expander corresponding to the physical address of the memory request is configured to convert the memory request into a CXL protocol message (Jung– Par. [0092] & Fig. 8, The on-chip cache 220A of the host CPU transmits the memory request to the CXL RP 210A (S210). The CXL RP 210A converts the memory request into the CXL flit and transmits the CXL flit to the CXL controller 311A (S220).), and the CXL controller is configured to transmit the CXL protocol message to the memory expander corresponding to the physical address of the memory request (Jung– Par. [0093] & Fig. 8, The CXL controller 311A converts the CXL flit back into the memory request, converts the byte address of the memory request into the block address, and then uses the block address to convert into a command that the existing storage 13A may understand and transmits the command to the existing storage 13A (S230). For example, when the existing storage 13A is the NVMe device, the CXL controller 311A may transmit an NVMe command through the connected interface.).
Referring to claim 18, note the rejections of claim 3 above. The Instant Claim recites substantially same limitations as the above-rejected and is therefore rejected under same prior-art teachings.
Referring to claim 19, note the rejections of claim 4 above. The Instant Claim recites substantially same limitations as the above-rejected and is therefore rejected under same prior-art teachings.
Referring to claim 20, note the rejections of claim 5 above. The Instant Claim recites substantially same limitations as the above-rejected and is therefore rejected under same prior-art teachings.
Conclusion
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R.I .Ill(c).
In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAYTON LEWIS-TAYLOR whose telephone number is (571) 2707754. The examiner can normally be reached on Monday through Thursday, 8AM TO 4PM, EASTERN TIME.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye, can be reached on (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Dayton Lewis-Taylor/
Examiner, Art Unit 2181