Detailed Action
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgements
2. Applicant’s arguments/remarks, filed 06/25/2026, are acknowledged. Amended claims 1, 6, 10-12, 14-6, and 18 are acknowledged. Claims 1-20 remain pending and have been examined.
Response to Arguments
3. Applicant's arguments filed 06/25/2026, with regards to independent claims 1 and 18, have been fully considered but they are not persuasive.
4. Applicant argues/remarks, on pg. 17
“…Oh does not teach:
wherein the row driver is configured to control the pixel so as to transfer the photo charges to the charge storage element and the first node during a first time period in which the photoelectric element is exposed to light” as recited in claim 1…”.
TX3 is configured to transfer photo charges from the second node (FD2) to the first node (FD1). During the exposure period, the row driver controls the second transfer transistor (TX3) to operate alternately with the first switch transistor (SX1), thereby distributing photo charges generated by a single photoelectric element to the first node (FD1) and the charge storage element (SD).
Similarly, on pg. 18 Applicant argues/remarks
“…claim 1 expressly recites “a photoelectric element” requiring that the claimed transfer operation be performed with respect to photo charges generated by a single photoelectric element…
…Oh relies on separate photodiodes rather than a single photoelectric element whose photo charges are selectively distributed between the first node and the charge storage element during exposure…”.
5. However, as mapped in the Non-Final office action, dated 03/25/2026, the stacked photoelectric conversion elements are viewed as sub-units of a photoelectric conversion acting within one pixel (pixel PX). Claim 1 does not read to limit the distribution of photo charges generated by a single photoelectric element or exclude sub-units of photoelectric conversion acting together within one pixel.
The argument/remark in this section is a narrower limitation which is not claimed in claim 1. Claim 1 does not read to limit distributing photo charges generated by a (the) single photoelectric element.
6. Applicant further states (pg. 17), the DRG transistor (mapped to TX3) is not configured to transfer photo charges from one floating diffusion node to another during an exposure period (see pg. 18).
7. However, the instant claim does not distinguish an exposure period from a non-exposure period; be it by means of a mechanical shutter or by an electronic shutter (in which case the photoelectric element is always exposed). Similarly, Oh does not specify a difference between mechanical or electronic shutter, as no shutter operation is specified. Thus, in both cases of the instant application and the cited reference, a time period wherein the photoelectric element is exposed is dependent on what type of shutter is employed (which the instant application doesn’t specify and further limit to claim).
Further, [0094] teaches charges generated by SPD are moved to FD2 and a signal corresponding to accumulated charges at FD2 are output through column line CL. Thus, in accordance the schematic of Fig. 2, an electric path from FD2 to FD1 is only through transistor DRG which is at a high between periods T8 and T9 (Fig. 5) while signals STS/SEL are high and charges generated at SPD are transferred to FD2 and further to column line CL.
The argument/remark in this section is a narrower limitation which is not claimed in claim 1. Claim 1 does not read to limit distributing photo charges generated by a (the) single photoelectric element.
Claim 1 does not provide enough distinguishing structural limitations, so to exclude the cited reference to not perform what is claimed.
8. Applicant’s arguments, see pg. 20, with respect to claim 10 have been fully considered and are persuasive. The rejection of claim 10 has been withdrawn.
9. In particular, the cited reference, according to Solheim US 10136084 B1 fails to teach a second node, as claimed in claim 10. Therefore, the cited reference also fails to teach a third transmission transistor disposed between the second node and the firs node.
10. The rejections of all claims dependent on independent claim 10 are therefore also withdrawn.
11. The rejection of method claim (independent claim) 18 is not withdrawn because it fails to claim the structural limitations of claim 10. Subject matter of amendment is addressed in the claim rejection (see below).
Claim Rejections - 35 USC § 102
12. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
13. Claims 1-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Oh et al. (US 2022/0272289 A1).
14. Regarding claim 1, an image sensor (…Oh teaches an image sensor 100 in [0027];
Fig. 1…), comprising:
a pixel (…[0028] teaches pixel array 110/plurality of pixels PX; Fig. 1 and Fig. 2…)
including
a photoelectric element configured to generate photo charges (…wherein [0031]
teaches that pixel PX includes a plurality of stacked photoelectric conversion elements;
Fig. 2…),
a driving transistor configured to generate a pixel signal based on a voltage of a first
node connected to the photoelectric element (…wherein [0064] teaches a driving transistor
DX which may output a voltage in accordance with a charge accumulated in at least one
of FD 1-3; Fig. 2…),
a charge storage element connected to the photoelectric element and configured to
store the photo charges (…wherein [0062] teaches C1 which may store charge; Fig. 2…),
a second transmission transistor connected between the first node and a second node
(…Oh, in [0060], teaches a second transmission transistor STG connecting SPD to FD2;
Fig. 2…),
a first transmission transistor connected between the second node and the photoelectric
element (…wherein [0060] teaches transmission transistor STG connected between
photodiode SPD and FD2; Fig. 2…), and
a first switch transistor connected between the second node and the charge storage
element (…Oh, in [0061-0062], teaches a first switch transistor SW1 connected between
FD2 and FD1; wherein FD2 connects to C1; Fig. 2…); and
a row driver connected to the pixel and configured to control the pixel (…wherein [0040]
teaches row driver 120 for driving pixel array 110; Fig. 1…), wherein
the row driver is configured to control the pixel so as to transfer the photo charges to the
charge storage element and the first node during the first time period (…wherein row driver
120 provides control signals as such SWS1; wherein overflow from SPD accumulates in
capacitor C1 during an exposure/readout period[0061-0062]…).
15. Regarding claim 2, Oh teaches the image sensor of claim 1 (see claim 1 above),
wherein the pixel further includes
a second switch transistor connected between the charge storage element and a
ground power source (…wherein Oh teaches, in [0114], switch transistor SW3 connected
between FD3 and C2; Fig. 9…), and
a first capacitor connected between the second switch transistor and the ground power
source (…wherein Oh, in [0114], teaches capacitor C2 connected between SW3 and VPIX;
Fig. 9…).
16. Regarding claim 3, Oh teaches the image sensor of claim 2 (see claim 2 above),
wherein the first capacitor comprises
a lateral overflow integration capacitor (LOFIC) (…wherein, as taught in [0115], overflowed charges from photodiode SPD may accumulate in capacitor C2…).
17. Regarding claim 5, Oh teaches the image sensor of claim 1 (see claim 1 above),
wherein: the pixel further includes
a second switch transistor (…wherein Oh, in [0100], teaches transistor SW2; Fig.
6…),
the charge storage element is a first capacitor (…[0062] teaches capacitor C1,
wherein overflow charge from photodiode SPD may accumulate in capacitor C1…),
the first switch transistor is connected between a first side of the first capacitor and the
first node (…wherein SW1 is connected between a side of capacitor C1 and FD1; Fig. 2
and Fig. 6…), and
the second switch transistor is connected between a second side of the first capacitor
and the first node (…wherein SW2, as depicted in Fig. 6, is connected between FD4 and
FD2…).
18. Regarding claim 6, teaches the image sensor of claim 1 (see claim 1 above), wherein:
the photoelectric element is configured to
generate the photo charges by being exposed to light during a first time period (…wherein Oh, in [0038-0039], teaches exposure time for generating pixel signals…).
19. Regarding claim 7, Oh teaches the image sensor of claim 6 (see claim 6 above),
wherein
the row driver is configured to control the pixel, such that, during the first time period, a
first operation of turning on the second transmission transistor and turning off the first switch
transistor (…wherein between T8 and T9 STS (second transmission transistor = STG) is
held high and SWS1 (first switch transistor = SW1) is held low; high conversion gain
HCG mode; Fig. 4…), and
a second operation of turning off the second transmission transistor and turning on the
first switch transistor are repeated (…wherein between periods T6 and T7, STS is held low
and SWS1 is held high; low conversion gain LCG mode; Fig. 4…).
20. Regarding claim 8, Oh teaches the image sensor of claim 7 (see claim 7 above), wherein:
the first operation is performed during a first period (...wherein the first operation falls
between periods T8 and T9…), and
the second operation is performed during a second period (…wherein the second
operation falls between periods T6 and T7…); and
photo charges among the photo charges corresponding to a ratio of the second period
divided by a sum of the second period and the first period are transferred to the charge storage
element (…wherein [0090] teaches that when SW1 is high, FD2 is connected to FD3 and
the pixel is in LCG mode; as such C1 is connected to FD3 and charges accumulated at
FD2 and FD3 may correspond to charges accumulated in capacitor C1 and charges
overflowed from photodiode SPD may accumulate in the capacitor C1 by the exposure
operation…).
21. Regarding claim 9, Oh teaches the image sensor of claim 6 (see claim 6 above),
Wherein the row driver is configured to
control the pixel, such that, during the first time period, a signal of a third potential between a first potential for turning on the first switch transistor (…wherein Oh, in [0090-0091] and [0094], teaches first switch transistor SW1 controlled by SWS1; SWS1 described with high/low levels; Fig. 4…) and
a second potential for turning off the first switch transistor is provided to a gate of the first
switch transistor (…wherein Oh, in [0090]–[0091], [0094], teaches SW1, first switch
transistor SW1 controlled by SWS1; SWS1 described with high/low levels; Fig. 4…), and
during the first time period, an operation of turning on the second transmission transistor
and an operation of turning off the second transmission transistor are repeated (…wherein the
timing diagram, as illustrated in Fig. 4, is viewed as an operation that is repetitively
performed during the operation of the pixel array…).
22. Claims 18-20 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by
Solheim et al. (US 10136084 B1).
23. Regarding claim 18, a driving method of an image sensor, the driving method comprising
alternately performing a first operation of transferring and storing photo charges of a photoelectric element generated during a first period to a charge storage element (…Solheim, in Fig. 4, step 418, teaches alternately the accumulation of charges on at least one capacitor; as evidenced in Fig. 2, C0 charges through transistor 270 connecting to FD230 (further, charge storage element is viewed to correspond to the storage area depicted in Fig. 2, which includes enable transistors 270/280 and capacitors C0 and C1)…) and
a second operation of transferring and storing photo charges of the photoelectric element generated during a second period after the first period to a first node connected to a gate electrode of a driving transistor (…Solheim, in column 9, lines 16-30, teaches time point 328 wherein after background noise are readout, signal charges of PD 202 are allowed to flow to FD 230; wherein the FD 230 is connected to the gate of transistor 250; Fig. 2-4…);
generating a first pixel signal based on a voltage of the first node (…wherein Solheim
teaches process block 430 (Fig. 4), in which at time 330, transferred charges from PD 202
to FD 230 are readout onto bitline 264; Fig. 2…); and
generating a second pixel signal based on a voltage of the charge storage element
(…wherein Solheim teaches process block 432/434 (Fig. 4) in which charges accumulated
in storage elements C0 is readout onto bitline 264; Fig. 2…).
24. Regarding claim 19, Solheim teaches the driving method of claim 18, further comprising
generating a third pixel signal based on a voltage of a first capacitor connected to the
charge storage element and configured to store photo charges overflowing from the photoelectric element (…wherein Solheim teaches process block 434 (Fig. 4) in which
charges accumulated in storage element C1 are readout onto bitline 264; Fig. 2…).
25. Regarding claim 20, the driving method of claim 18 (see claim 18 above), wherein
the generating the first pixel signal comprises generating a third pixel signal based on a
voltage of the first node and a voltage of a second capacitor connected to the first node
(…wherein Solheim teaches process block 434 (Fig. 4) in which charges accumulated in
storage element C1 are readout onto bitline 264 through FD 230; Fig. 2…).
Claim Rejections - 35 USC § 103
26. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
27. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. (US 2022/0272289 A1) in view of Velichko (US 2018/0115730 A1).
28. Regarding claim 4, Oh teaches the image sensor of claim 1 (see claim 1 above),
wherein
the charge storage element is a storage diode or a storage gate transistor (…Oh does
not specify a storage diode or a storage gate transistor for a charge storage element.
However, Velichko, in [0024], teaches readout circuitry associated with a pair of
split photodiodes to include a pixel charge storage region; e.g. a pinned storage diode or
a storage gate.
Therefore, it would have been obvious to one of ordinary skill in the art before the
effective filing date of the claimed invention that a storage diode, as taught by Velichko is
implemented as a means to free up a floating diffusion area that is useable to transit
several signals in different readout periods and thus can be easily implemented as a
storage device in the teaching of Oh’s image sensor…).
Allowable Subject Matter
29. Claim 10 is allowed (for reasons as specified above). The rejections of all claims dependent on independent claim 10 (11-17) are therefore also withdrawn.
Conclusion
30. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SURAFEL YILMAKASSAYE whose telephone number is (703)756-1910. The examiner can normally be reached Monday-Friday 8:30am-5:00pm.
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/SURAFEL YILMAKASSAYE/Examiner, Art Unit 2639
/TWYLER L HASKINS/Supervisory Patent Examiner, Art Unit 2639
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