Detailed Action
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
2. The information disclosure statement (IDS) submitted on 10/24/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claims 1-3 and 5-9 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Oh et al. (US 2022/0272289 A1).
5. Regarding claim 1, an image sensor (…Oh teaches an image sensor 100 in [0027]; Fig. 1…), comprising:
a pixel (…[0028] teaches pixel array 110/plurality of pixels PX; Fig. 1 and Fig. 2…) including
a photoelectric element configured to generate photo charges (…wherein [0031] teaches that pixel PX includes a plurality of stacked photoelectric conversion elements; Fig. 2…),
a driving transistor configured to generate a pixel signal based on a voltage of a first node connected to the photoelectric element (…wherein [0064] teaches a driving transistor DX which may output a voltage in accordance with a charge accumulated in at least one of FD 1-3; Fig. 2…),
a charge storage element connected to the photoelectric element and configured to store the photo charges (…wherein [0062] teaches C1 which may store charge; Fig. 2…),
a second transmission transistor connected between the first node and a second node (…Oh, in [0060], teaches a second transmission transistor STG connecting SPD to FD2; Fig. 2…),
a first transmission transistor connected between the second node and the photoelectric element (…wherein [0060] teaches transmission transistor STG connected between photodiode SPD and FD2; Fig. 2…), and
a first switch transistor connected between the second node and the charge storage element (…Oh, in [0061-0062], teaches a first switch transistor SW1 connected between FD2 and FD1; wherein FD2 connects to C1; Fig. 2…); and
a row driver connected to the pixel and configured to control the pixel (…wherein [0040] teaches row driver 120 for driving pixel array 110; Fig. 1…).
6. Regarding claim 2, Oh teaches the image sensor of claim 1 (see claim 1 above), wherein
the pixel further includes
a second switch transistor connected between the charge storage element and a ground power source (…wherein Oh teaches, in [0114], switch transistor SW3 connected between FD3 and C2; Fig. 9…), and
a first capacitor connected between the second switch transistor and the ground power source (…wherein Oh, in [0114], teaches capacitor C2 connected between SW3 and VPIX; Fig. 9…).
7. Regarding claim 3, Oh teaches the image sensor of claim 2 (see claim 2 above), wherein
the first capacitor comprises a lateral overflow integration capacitor (LOFIC) (…wherein, as taught in [0115], overflowed charges from photodiode SPD may accumulate in capacitor C2…).
8. Regarding claim 5, Oh teaches the image sensor of claim 1 (see claim 1 above), wherein:
the pixel further includes
a second switch transistor (…wherein Oh, in [0100], teaches transistor SW2; Fig. 6…),
the charge storage element is a first capacitor (…[0062] teaches capacitor C1, wherein overflow charge from photodiode SPD may accumulate in capacitor C1…),
the first switch transistor is connected between a first side of the first capacitor and the first node (…wherein SW1 is connected between a side of capacitor C1 and FD1; Fig. 2 and Fig. 6…), and
the second switch transistor is connected between a second side of the first capacitor and the first node (…wherein SW2, as depicted in Fig. 6, is connected between FD4 and FD2…).
9. Regarding claim 6, teaches the image sensor of claim 1 (see claim 1 above), wherein:
the photoelectric element is configured to
generate the photo charges by being exposed to light during a first time period (…wherein Oh, in [0038-0039], teaches exposure time for generating pixel signals…); and
the row driver is configured to control the pixel so as to transfer the photo charges to the charge storage element and the first node during the first time period (…wherein row driver 120 provides control signals as such SWS1; wherein overflow from SPD accumulates in capacitor C1 during an exposure/readout period[0061-0062]…).
10. Regarding claim 7, Oh teaches the image sensor of claim 6 (see claim 6 above), wherein
the row driver is configured to control the pixel, such that, during the first time period, a first operation of turning on the second transmission transistor and turning off the first switch transistor (…wherein between T8 and T9 STS (second transmission transistor = STG) is held high and SWS1 (first switch transistor = SW1) is held low; high conversion gain HCG mode; Fig. 4…), and
a second operation of turning off the second transmission transistor and turning on the first switch transistor are repeated (…wherein between periods T6 and T7, STS is held low and SWS1 is held high; low conversion gain LCG mode; Fig. 4…).
11. Regarding claim 8, teaches the image sensor of claim 7 (see claim 7 above), wherein:
the first operation is performed during a first period (...wherein the first operation falls between periods T8 and T9…), and
the second operation is performed during a second period (…wherein the second operation falls between periods T6 and T7…); and
photo charges among the photo charges corresponding to a ratio of the second period divided by a sum of the second period and the first period are transferred to the charge storage element (…wherein [0090] teaches that when SW1 is high, FD2 is connected to FD3 and the pixel is in LCG mode; as such C1 is connected to FD3 and charges accumulated at FD2 and FD3 may correspond to charges accumulated in capacitor C1 and charges overflowed from photodiode SPD may accumulate in the capacitor C1 by the exposure operation…).
12. Regarding claim 9, Oh teaches the image sensor of claim 6 (see claim 6 above), wherein
the row driver is configured to control the pixel, such that, during the first time period, a signal of a third potential between a first potential for turning on the first switch transistor (…wherein Oh, in [0090-0091] and [0094], teaches first switch transistor SW1 controlled by SWS1; SWS1 described with high/low levels; Fig. 4…) and
a second potential for turning off the first switch transistor is provided to a gate of the first switch transistor (…wherein Oh, in [0090]–[0091], [0094], teaches SW1, first switch transistor SW1 controlled by SWS1; SWS1 described with high/low levels; Fig. 4…), and
during the first time period, an operation of turning on the second transmission transistor and an operation of turning off the second transmission transistor are repeated (…wherein the timing diagram, as illustrated in Fig. 4, is viewed as an operation that is repetitively performed during the operation of the pixel array…).
13. Claims 10 and 14-20 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Solheim et al. (US 10136084 B1).
14. Regarding claim 10, an image sensor (…Solheim, in column 3, lines 28-33, teaches image sensor system 200; Fig. 2…), comprising:
a photoelectric element region in which a photoelectric element configured to generate photo charges by being exposed to light during a first time period is disposed (…wherein column 3, lines 51-56, teach a detecting photodiode PD 202 which accumulates photo-charges (which connects to FD 230 through TX 220); Fig. 2…);
a first transmission transistor region disposed in the photoelectric element region and configured to receive the photo charges (…column 3, lines 51-52, teach transfer transistor TX 220; Fig. 2…);
a first selection transistor region configured to receive the photo charges through the first transmission transistor region (…column 3, lines 37-40, teach a first enable transistor 270 connected to FD 230; Fig. 2…); and
a third transmission transistor region configured to receive the photo charges through the first transmission transistor region (…column 3, lines 37-40, teach enable transistor 280 also attached to FD 230; Fig. 2…), wherein,
during the first time period, the photo charges are alternately transferred to the first selection transistor region and the third transmission transistor region (…wherein column 7, lines 50-62, teach the accumulation of charges on C0 and C1 alternately; which charge through enable transistor 270 (first selection transistor) and 280 (a third transmission transistor); figures 2 and 4…).
15. Regarding claim 14, Solheim teaches the image sensor of claim 10 (see claim 10 above), wherein
the first selection transistor region(SX) (…Solheim, transistor 270; Fig. 2…) and the third transmission transistor region(TX3) (…Solheim, transistor 280; Fig. 2…) are disposed in a first direction from the first transmission transistor region(TX1) (…Solheim, TX 220; Fig. 2…) (…wherein transistors 270 and transistors 280, in accordance with Fig. 2, are at a distance horizontally directed, from transistor 220…).
16. Regarding claim 15, Solheim teaches the image sensor of claim 14 (see claim 14 above), wherein
the third transmission transistor region(TX3) (…Solheim, transistor 280; Fig. 2…) and the first selection transistor region(SX) (…Solheim, transistor 270; Fig. 2…) are spaced apart from each other in a second direction crossing the first direction (…wherein transistors 280 and 270, in accordance with Fig. 2, are separated by a margin vertically directed from each other…).
17. Regarding claim 16, Solheim teaches the image sensor of claim 10 (see claim 10), further comprising:
a second selection transistor region disposed apart from the first selection transistor region in a second direction (…wherein node 274 (Fig. 2) connects to transistor 270; as such the circuit branch transistor 270 to FD 230 is viewed as being vertically spaced from the circuit branch connecting transistor 270 to node 274…); and
a first capacitor region disposed apart from the second selection transistor region in the second direction (…wherein capacitor C0 connects to node 274 (Fig. 2) and is at a position vertical to node 274…).
18. Regarding claim 17, Solheim teaches the image sensor of claim 16 (see claim 16 above), wherein
the first capacitor region comprises a lateral overflow integration capacitor (LOFIC) (…wherein Solheim, in column 4, lines 10-17, teaches storage capacitors which stores charges from a saturated PD 202…).
19. Regarding claim 18, a driving method of an image sensor, the driving method
alternately performing a first operation of transferring photo charges of a photoelectric element generated during a first period to a charge storage element (…Solheim, in Fig. 4, step 418, teaches alternately the accumulation of charges on at least one capacitor; as evidenced in Fig. 2, C0 charges through transistor 270 connecting to FD230 (further, charge storage element is viewed to correspond to the storage area depicted in Fig. 2, which includes enable transistors 270/280 and capacitors C0 and C1)…) and
a second operation of transferring photo charges of the photoelectric element generated during a second period after the first period to a first node (…Solheim, in column 9, lines 16-30, teaches time point 328 wherein after background noise are readout, signal charges of PD 202 are allowed to flow to FD 230; Fig. 2-4…);
generating a first pixel signal based on a voltage of the first node (…wherein Solheim teaches process block 430 (Fig. 4), in which at time 330, transferred charges from PD 202 to FD 230 are readout onto bitline 264; Fig. 2…); and
generating a second pixel signal based on a voltage of the charge storage element (…wherein Solheim teaches process block 432/434 (Fig. 4) in which charges accumulated in storage elements C0 is readout onto bitline 264; Fig. 2…).
20. Regarding claim 19, Solheim teaches the driving method of claim 18, further comprising
generating a third pixel signal based on a voltage of a first capacitor connected to the charge storage element and configured to store photo charges overflowing from the photoelectric element (…wherein Solheim teaches process block 434 (Fig. 4) in which charges accumulated in storage element C1 are readout onto bitline 264; Fig. 2…).
21. Regarding claim 20, the driving method of claim 18 (see claim 18 above), wherein
the generating the first pixel signal comprises generating a third pixel signal based on a voltage of the first node and a voltage of a second capacitor connected to the first node (…wherein Solheim teaches process block 434 (Fig. 4) in which charges accumulated in storage element C1 are readout onto bitline 264 through FD 230; Fig. 2…).
Claim Rejections - 35 USC § 103
22. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
23. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. (US 2022/0272289 A1) in view of Velichko (US 2018/0115730 A1).
24. Regarding claim 4, Oh teaches the image sensor of claim 1 (see claim 1 above), wherein
the charge storage element is a storage diode or a storage gate transistor (…Oh does not specify a storage diode or a storage gate transistor for a charge storage element.
However, Velichko, in [0024], teaches readout circuitry associated with a pair of split photodiodes to include a pixel charge storage region; e.g. a pinned storage diode or a storage gate.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a storage diode, as taught by Velichko is implemented as a means to free up a floating diffusion area that is useable to transit several signals in different readout periods and thus can be easily implemented as a storage device in the teaching of Oh’s image sensor…).
25. Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Solheim et al. (US 10136084 B1) in view of Roy (US 2018/0061875 A1).
26. Regarding claim 11, Solheim teaches the image sensor of claim 10 (see claim 10 above), wherein
a gate of the first transmission transistor region comprises a vertical transfer gate (…though Solheim, in column 4, lines 28-32, teaches a 4 transistor (4T) pixel, Solheim doesn’t explicitly teach a vertical transfer gate. However, Roy teaches an image sensor pixel to include a vertical transfer gate transistor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a vertical transfer gate transistor, as taught by Roy, is employable in the design of an image sensor pixel whereby fixed pattern noise due to high lateral electric field is reduced…).
27. Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Solheim et al. (US 10136084 B1) in view of Chen et al. (US 2023/0029874 A1).
28. Regarding claim 12, Solheim teaches the image sensor of claim 10 (see claim 10 above), further comprising
a charge storage element (…wherein Solheim, in column 7, lines 50-62, teaches the accumulation of charges on C0 and C1; Fig. 2…) disposed apart from the first selection transistor region (…transistor 270; Fig. 2…) in a first direction and configured to store the photo charges, wherein the charge storage element is separated from the first selection transistor region through a deep trench isolation (DTI) (…Solheim does not specify to teach a deep trench isolation thus to isolate a charge storage element and a transistor.
However, Chen teaches a CMOS image sensor with a deep trench isolation (DTI) structure for pixel regions wherein pixel components reside therein; wherein each pixel includes a photodiode and associated transistors which are bounded by walls of deep trench isolation structure ([0016]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that deep trench isolation structures in a pixel design, as taught by Chen, are implemented in an image sensor wherein pixels are designed with a reduced optical and electrical crosstalk…).
29. Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Solheim et al. (US 10136084 B1) in view of Chen et al. (US 2023/0029874 A1) and in further view Ellis-Monaghan et al. (US 2010/0230729 A1).
30. Regarding claim 13, Solheim in view of Chen teaches the image sensor of claim 12 (see claim 12 above), wherein
a light blocking layer is located on the charge storage element (…Solheim in view of Chen does not further teach a light blocking layer. However, Ellis-Monaghan teaches a pixel sensor cell which includes a light shielding element. For example, [0015], teaches a light blocking layer shielding a thin film transistor and a metal-insulator-metal capacitor that are used in place of a floating diffusion within a pixel sensor cell.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a light blocking layer, as taught by Ellis-Monaghan, is implemented within a pixel sensor cell thereby avoiding spurious light effects…).
Conclusion
31. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SURAFEL YILMAKASSAYE whose telephone number is (703)756-1910. The examiner can normally be reached Monday-Friday 8:30am-5:00pm.
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/SURAFEL YILMAKASSAYE/Examiner, Art Unit 2639
/TWYLER L HASKINS/Supervisory Patent Examiner, Art Unit 2639