Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response to Amendment
No amendment was filed with the Response filed August 3, 2026.
Claims 1-12 are rejected over the previously applied reference(s).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2021/0191488 to Felix et al. (“Felix”).
With respect to claim 1, Felix discloses in Figs. 1-2 a method of controlling a dynamic voltage and frequency scaling circuit, comprising:
detecting (e.g., 13) a voltage droop relative to a current nominal voltage and frequency state;
responsive to said current nominal voltage and frequency state having a corresponding fallback state in a safe operating zone of voltage and frequency (e.g., when the voltage droop above a threshold at the current frequency as per Para. 37 is detected by 13, the clock supplied to processor 2 is first stopped “as a first” by stop and ramp logic 20 as per Para. 39, and then 20 provides the clock at a lower frequency as per Para. 40; here, in the foregoing determination to not stop the clock supplied to processor 2 after the initial stoppage of the clock upon detecting the voltage droop but supplying the clock at a lower frequency, wherein “Stopping the lock mitigates the droop” as per Para. 39, the supplying of the clock at a lower frequency, wherein the voltage droop would be reduced compared to the higher frequency clock, corresponds to the claimed fallback state in a/one safe operating zone), switching activity from a nominal source (e.g., 4 and 21) to a fallback source (e.g., the lower frequency of the clock is supplied to 20 after the voltage droop is detected by 13 as per Paras. 39-40); and
when a fallback to a safe operating zone is unavailable for said current nominal voltage and frequency state (e.g., the lower frequency of the clock is supplied to 20 after the voltage droop is detected by 13 as per Paras. 39-40 and is unavailable during the time that the clock supplied to 2 is altogether stopped, wherein “Stopping the lock mitigates the droop” as per Para. 39; here, in the foregoing determination to not stop the clock supplied to processor 2 after the initial stoppage of the clock upon detecting the voltage droop but supplying the clock at a lower frequency, wherein “Stopping the lock mitigates the droop” as per Para. 39, the supplying of the clock at a lower frequency, wherein the voltage droop would be reduced compared to the higher frequency clock, corresponds to the claimed fallback state in a/one safe operating zone (e.g., it is noted that the claim language does not state “a fall back to any safe operating zone is unavailable”) safe operating zone), pausing activity (e.g., providing clock to 20) of the dynamic voltage and frequency scaling circuit.
With respect to claim 2, the dynamic voltage and frequency scaling circuit comprises a clock circuit (e.g., 4).
With respect to claim 3, the nominal source (e.g., 4 and 21) comprises a first phase locked loop (e.g., 4 is a PLL according to Para. 31).
With respect to claim 4, the fallback source (e.g., the lower frequency clock may be provided by a second PLL according to Para. 31) comprises a second phase locked loop.
With respect to claim 5, the safe operating zone (e.g., the lower frequency of the clock is supplied to 20 after the voltage droop is detected by 13 as per Paras. 39-40) comprises a zone of the voltage domain in which there is sufficient available frequency reduction to permit continued operation in case of a maximum possible voltage droop (e.g., a voltage droop less than a threshold as per Para. 37, wherein a voltage droop above the threshold as per Para. 37 starts the mitigation steps in Paras. 39-40).
With respect to claim 6, outside the safe operating zone (e.g., a voltage droop above the threshold as per Para. 37 starts the mitigation steps in Paras. 39-40) comprises at least one zone (e.g., a voltage droop above the threshold as per Para. 37 starts the mitigation steps in Paras. 39-40) of the voltage domain in which a maximum possible voltage droop risks rendering the circuit inoperable (e.g., timing failures according to Abstract).
With respect to claim 7, the above discussion for claim 1 similarly applies.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8-12 are rejected under 35 U.S.C. 103 as being unpatentable over Felix.
With respect to claim 8, an electronic circuit comprising electronic logic components operable to perform the steps of the method according to claim 1 are shown in Fig. 2.
With respect to claim 9, Felix fails to explicitly disclose a non-transitory computer readable medium comprising a structure of data and imperatives operable to cause a device to construct a set of electronic logic components which, when embedded in an electronic device and activated thereon, cause the electronic device to perform the steps of the method according to claim 1. However, it was notoriously well known before the effective filing date of the claimed invention that functions of a circuit may be controlled/performed/enabled by a non-transitory computer readable medium comprising a structure of data and imperatives operable to cause a device to construct a set of electronic logic components which, when embedded in an electronic device and activated thereon, cause the electronic device to perform the steps of a method. The foregoing common knowledge or well-known in the art statement is taken to be admitted prior art because applicant failed to timely traverse the examiner’s assertion of official notice. See MPEP 2144.03(C). Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing of the claimed invention to control/perform/enable the functions of the Figs. 1-2 circuit of Felix using the notoriously well-known method of controlling/performing/enabling a circuit by using a non-transitory computer readable medium comprising a structure of data and imperatives operable to cause a device to construct a set of electronic logic components which, when embedded in an electronic device and activated thereon, cause the electronic device to perform the steps of a method because such a modification allows a computer to control/perform/enable the circuit.
With respect to claim 10, Felix fails to explicitly disclose that the Figs. 1-2 circuit is implemented in at least one packaged chip, wherein at least one system component (e.g., control/voltage supply circuit for Figs 1-2 circuit) and the chip are formed/assembled on a board. However, it was notoriously well known to a person of ordinary skill in the art before the effective filing date of the claimed invention that (1) a circuit may be formed on a chip to save space/costs and that (2) a chip and its controller/power supply circuit may be formed on a board to save space and connect the two. The foregoing common knowledge or well-known in the art statement is taken to be admitted prior art because applicant failed to timely traverse the examiner’s assertion of official notice. See MPEP 2144.03(C). Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to (1) form the Figs. 1-2 circuit of Felix as a chip in view of the notoriously well-known teaching of forming a circuit on a chip because such a modification saves space/costs and (2) to form the chip and its controller/power supply circuit on a board in view of the notoriously well-known teaching of forming a chip and its controller/power supply circuit on a board because such a modification saves spaces and allows connections between the two.
With respect to claim 11, implementing circuits on a chip and putting the chips on a board with other components are notoriously well-known as discussed for claim 10 and further use with other components would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to save costs/space and/or allow connections.
With respect to claim 12, Felix fails to explicitly disclose a non-transitory computer-readable medium to store computer-readable code for fabrication of the electronic circuit of claim 8. However, it was notoriously well known to a person of ordinary skill in the art before the effective filing date of the claimed invention that computer-readable code for fabrication of the electronic circuit may be stored on a non-transitory computer-readable medium. The foregoing common knowledge or well-known in the art statement is taken to be admitted prior art because applicant failed to timely traverse the examiner’s assertion of official notice. See MPEP 2144.03(C). Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to fabricate the Figs. 1-2 circuit of Felix using the notoriously well-known method of fabricating a circuit using a non-transitory computer-readable medium storing a computer-readable code for fabrication of the electronic circuit because the fabrication of the Figs. 1-2 circuit of Felix requires a specific implementation and the notoriously well-known method provides such a specific implementation.
Response to Arguments
Applicant's arguments filed August 3, 2026 have not been found persuasive. For example, Applicant argues that Felix does not disclose a fallback to a safe operating zone is unavailable for said current nominal voltage and frequency state, pausing activity of the dynamic voltage and frequency scaling circuit as required in claim 1. However, Felix discloses such a feature. It appears that Applicant’s argument is based on a requirement that the pause occurs when a fallback to any safe operating zone is unavailable. However, the argument is not commensurate with the claim scope.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jung KIM whose telephone number is (571)270-7964. The examiner can normally be reached on M-F from 9AM to 5:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Regis BETSCH, can be reached at (571)270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JUNG KIM/
Primary Examiner, Art Unit 2836
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