DETAILED ACTION
This office action is responsive to application 18/925,421 filed on October 24, 2024. Claims 1-16 are pending in the application and have been examined by the Examiner.
Information Disclosure Statement
The Information Disclosure Statement (IDS) filed on October 24, 2024 was received and has been considered by the Examiner.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Engelkemier et al. (US 11,102,445) in view of Kobayashi (US 2019/0012763).
Consider claim 1, Engelkemier et al. teaches:
A semiconductor device (first device, 102, figure 1) comprising:
a reception interface circuit (first physical layer device, 112) receiving a plurality of packets including a plurality of line data, respectively (i.e. receiving MIPI CSI-2 data packets from a car camera sensor, column 5, lines 32-50), and outputting an image composite signal generated by linking a line synchronization signal with each of the plurality of line data (The first physical layer device (112) links the received data packets into AVTP data packets, column 5, lines 43-50, column 6, lines 32-37. The created AVTP data packets include line start and line end fields which are communicated through vertical and horizontal sync indicators, column 3, lines 7-26, column 7, lines 21-31.).
Engelkemier et al. does not explicitly teach that the semiconductor device comprises a capture circuit provided at a subsequent stage of the reception interface circuit, wherein the capture circuit includes: a line counter receiving, as its input, the line synchronization signal included in the image composite signal, and counting the number of times of the input of the line synchronization signal; and a comparator comparing a count value counted by the line counter with a preset expected value of the number of lines, and outputting an error signal if the count value and the expected value do not match each other.
Kobayashi similarly teaches a semiconductor device (figures 1) which receives image data from an image sensor (image sensor, 400, paragraphs 0039-0042).
However, Kobayashi additionally teaches that the semiconductor device comprises a capture circuit (instruction control section, 300, figures 1 and 2, paragraphs 0041 and 0049), wherein the capture circuit (300) includes: a line counter (line counter, 320, figures 2 and 5, paragraph 0051) receiving, as its input (see figure 5), the line synchronization signal (“horizontal synchronization signal”) included in the image composite signal, and counting the number of times of the input of the line synchronization signal (“For each time when one line has been scanned, a horizontal synchronization signal is asserted, and in accordance with it, this line counter 320 performs counting one by one.” paragraph 0051); and a comparator (comparator, 324, figure 5) comparing a count value counted by the line counter (i.e. as output by flip-flop 321, figure 5, paragraph 0082) with a preset expected value of the number of lines (“REG_LCNT_MAX[7:0]”, paragraph 0083, see figure 5), and outputting an error signal if the count value and the expected value do not match each other (As detailed in paragraph 0072, “The comparator 314 is a comparator that compares the output Q of the flip-flop 311 with “REG_FCNT_MAX”. The “REG_FCNT_MAX” is a value of eight bits set in the control register 200, and sets the maximum value of the frame counter. In the case where the vertical synchronization signal is asserted in a state where the output Q of the flip-flop 311 has reached this maximum value, this frame counter 310 starts recounting from “0”. Paragraph 0084 details that the constitution of the line counter (320) is similar to that of the frame counter (310). The Examiner interprets the output of the comparator (324) to be an error signal if the count value from the flip-flop (321) and the “REG_LCNT_MAX[7:0]” value do not match.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to include a capture circuit as taught by Kobayashi provided at a subsequent stage of the reception interface circuit taught by Engelkemier et al. for the benefit of attaining an excellent effect that calculation contents can be switched over in robustness in a pixel region within a frame of image data (Kobayahi, paragraph 0015).
Consider claim 2, and as applied to claim 1 above, Engelkemier et al. further teaches that the reception interface circuit (112) is a circuit based on MIPI (Mobile Industry Processor Interface) CSI-2 (Camera Serial Interface 2) standards (i.e. receiving MIPI CSI-2 data packets from a car camera sensor, column 5, lines 32-50).
Consider claim 3, and as applied to claim 2 above, Engelkemier et al. further teaches that the image composite signal further includes a frame synchronization signal linked with the whole of the plurality of line data (The AVTP data packet includes start frame and end frame fields which are communicated through vertical and horizontal sync indicators, column 3, lines 7-26.).
Engelkemier et al. does not explicitly teach the line counter.
Kobayashi further teaches that the line counter (320) counts the number of times of the input of the line synchronization signal (“horizontal synchronization signal”, figure 5) within an assertive period of the frame synchronization signal (“vertical synchronization signal”, see paragraphs 0050 and 0051).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the line counter taught by the combination of Engelkemier and Kobayashi perform operations during an assertive period of a frame synchronization signal as taught by Kobayashi for the benefit of attaining an excellent effect that calculation contents can be switched over in robustness in a pixel region within a frame of image data (Kobayahi, paragraph 0015).
Consider claim 4, and as applied to claim 1 above, Engelkemier et al. further teaches that each of the plurality of packets is a packet transmitted by an image sensor generating image data based on image capturing (i.e. receiving MIPI CSI-2 data packets from a car camera sensor, column 5, lines 32-50).
Consider claim 7, and as applied to claim 1 above, Engelkemier et al. does not explicitly teach a processor, wherein the capture circuit writes the line data into a memory, and the processor reads out the line data written into the memory, and performs an image processing or an image recognition processing.
Kobayashi further teaches a processor (signal processing section, 500, figure 1), wherein the capture circuit (300) writes the line data into a memory (line buffer, 510, see figure 1), and the processor (500) reads out the line data written into the memory (510), and performs an image processing (i.e. via processing elements 520, paragraph 0051).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the semiconductor device taught by the combination of Engelkemier and Kobayashi include a processor configured as taught by Kobayashi for the benefit of attaining an excellent effect that calculation contents can be switched over in robustness in a pixel region within a frame of image data (Kobayahi, paragraph 0015).
Allowable Subject Matter
Claims 8-16 are allowed.
Claims 5 and 6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Consider claim 5, the prior art of record does not teach nor reasonably suggest that the capture circuit further includes a line division circuit dividing the line data of one line into a plurality of division line data and outputting an image composite signal that has been divided, generated by linking the line synchronization signal with each of the plurality of division line data, and the line counter receives, as its input, the line synchronization signal included in the image composite signal that has been divided, and counts the number of times of the input of the line synchronization signal, in combination with the other elements recited in parent claim 1.
Claim 6 contains allowable subject matter as depending from claim 5.
Consider claim 8, the closest prior art, Engelkemier et al. (US 11,102,445) teaches:
A semiconductor device (first device, 102, figure 1) comprising:
a reception interface circuit (first physical layer device, 112) receiving a plurality of packets including a plurality of line data, respectively (i.e. receiving MIPI CSI-2 data packets from a car camera sensor, column 5, lines 32-50), and outputting an image composite signal generated by linking a line synchronization signal with each of the plurality of line data (The first physical layer device (112) links the received data packets into AVTP data packets, column 5, lines 43-50, column 6, lines 32-37. The created AVTP data packets include line start and line end fields which are communicated through vertical and horizontal sync indicators, column 3, lines 7-26, column 7, lines 21-31.).
Engelkemier et al. does not explicitly teach that the semiconductor device comprises a capture circuit provided at a subsequent stage of the reception interface circuit, wherein the capture circuit includes: a line counter receiving, as its input, the line synchronization signal included in the image composite signal, and counting the number of times of the input of the line synchronization signal; and a comparator comparing a count value counted by the line counter with a preset expected value of the number of lines, and outputting an error signal if the count value and the expected value do not match each other.
Kobayashi (US 2019/0012763) similarly teaches a semiconductor device (figures 1) which receives image data from an image sensor (image sensor, 400, paragraphs 0039-0042).
However, Kobayashi additionally teaches that the semiconductor device comprises a capture circuit (instruction control section, 300, figures 1 and 2, paragraphs 0041 and 0049), wherein the capture circuit (300) includes: a line counter (line counter, 320, figures 2 and 5, paragraph 0051) receiving, as its input (see figure 5), the line synchronization signal (“horizontal synchronization signal”) included in the image composite signal, and counting the number of times of the input of the line synchronization signal (“For each time when one line has been scanned, a horizontal synchronization signal is asserted, and in accordance with it, this line counter 320 performs counting one by one.” paragraph 0051); and a comparator (comparator, 324, figure 5) comparing a count value counted by the line counter (i.e. as output by flip-flop 321, figure 5, paragraph 0082) with a preset expected value of the number of lines (“REG_LCNT_MAX[7:0]”, paragraph 0083, see figure 5), and outputting an error signal if the count value and the expected value do not match each other (As detailed in paragraph 0072, “The comparator 314 is a comparator that compares the output Q of the flip-flop 311 with “REG_FCNT_MAX”. The “REG_FCNT_MAX” is a value of eight bits set in the control register 200, and sets the maximum value of the frame counter. In the case where the vertical synchronization signal is asserted in a state where the output Q of the flip-flop 311 has reached this maximum value, this frame counter 310 starts recounting from “0”. Paragraph 0084 details that the constitution of the line counter (320) is similar to that of the frame counter (310). The Examiner interprets the output of the comparator (324) to be an error signal if the count value from the flip-flop (321) and the “REG_LCNT_MAX[7:0]” value do not match.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to include a capture circuit as taught by Kobayashi provided at a subsequent stage of the reception interface circuit taught by Engelkemier et al. for the benefit of attaining an excellent effect that calculation contents can be switched over in robustness in a pixel region within a frame of image data (Kobayahi, paragraph 0015).
However, the prior art of record does not teach nor reasonably suggest at least that the capture circuit includes a data extraction circuit receiving, as its input, the image composite signal, and extracting image data from the plurality of line data on the basis of a preset rule, and a synchronization signal reproduction circuit linking a line synchronization signal for counting with the image data extracted by the data extraction circuit, for each line, in combination with the other elements recited in claim 8.
Claims 9-16 are allowed as depending from an allowable claim 8.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
M (US 11,659,301) teaches a semiconductor device (105, figure 1) including a data synchronization module (130) configured to insert embedded synchronization data into received MIPI data packets (see column 5, lines 10-64, column 6, line 46 through column 7, line 31).
Shoyama (US 2011/0102650) teaches a semiconductor device (figure 1) having a synchronization code adding portion (33, see paragraphs 0038-0040).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALBERT H CUTLER whose telephone number is (571)270-1460. The examiner can normally be reached approximately Mon - Fri 8:00-4:30.
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/ALBERT H CUTLER/Primary Examiner, Art Unit 2637