DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending. Claims 1, 8 and 19 are independent.
Information Disclosure Statement
Applicant’s Information Disclosure Statements (IDSs) filed October 30, 2024, and November 5, 2024, have been considered.
Priority
Acknowledgment is made of applicant’s claim for domestic benefit based on prior application U.S. Pat. App. Ser. No. 17/895,988 previously filed on 8/25/22. Whereby, the prior-filed application has since been issued as U.S. Pat. No. 12,131,778 on 10/29/2024.
Applicant’s claim for the benefit of the prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged.
Specification
The disclosure is objected to because of the following informalities:
In the third sentence of para. 49, change “memoroy” to –memory–.
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 3-6, and 8-18 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, and 5-7 of U.S. Patent No. 12,131,778 B2 (“the reference patent”). The claims of the instant application and the claims of the reference patent are compared in the table below. Every element as set forth in the examined claims are found, either expressly or inherently described, in the reference patent, i.e., the instant claims are anticipated by the reference patent.
Regarding independent claim 1, U.S. Patent No. 12,131,778 B2 anticipates all limitations of the claim.
Instant Application
U.S. Patent
Independent Claim 1:
A device comprising: a memory array; and a controller configured to: determine whether to enhance a write pulse based on a type of write operation; and in response to determining to enhance the write pulse, apply the enhanced write pulse to at least one memory cell in the memory array.
Independent Claim 1:
A system comprising: a memory array including memory cells; memory configured to store a record associated with prior read operations for the memory cells;
and a controller configured to: apply pulses to the memory cells when performing read and write operations,
wherein for the write operations the pulses include at least one first write pulse, and at least one second write pulse of a greater magnitude than the first write pulse;
perform at least one read operation on at least one first memory cell of the memory array; in response to performing the read operation, add a first entry associated with the first memory cell to the record;
select, for performing a write operation on the first memory cell, a write pulse based on the record stored in the memory, wherein the selecting comprises determining that the first entry is in the record, and in response to determining that the first entry is in the record, selecting the second write pulse; and apply the second write pulse to the first memory cell for performing the write operation.
During a write operation, the magnitude of the write pulse varies depending on if a first write pulse is selected (i.e. un-enhanced or standard write pulse) or if a second write pulse is selected (i.e. enhanced write pulse), whereby the second write pulse is of greater magnitude. The condition to apply the second write pulse (i.e. determining whether to enhance the write pulse) is determined based on if the selected memory cell underwent a prior read operation, which means when a prior read is true for the target cell, the second—larger—write pulse is applied to the cell(s).
Regarding dependent claims 3-6 of independent claim 1, U.S. Patent No. 12,131,778 B2 anticipates all limitations of all the claims.
Instant Application
Reference Parent Case
Claim 3:
The device of claim 1, wherein the type of write operation is a RESET on SET write operation.
Claim 5 (dependent on claims 4 and 1):
The system of claim 4, wherein the write operation is a RESET on SET write operation.
Claim 4:
The device of claim 1, wherein the controller is further configured to: apply a pre-read voltage to the memory cell; and determine the type of write operation based on applying the pre-read voltage.
Claim 6 (dependent on claims 4 and 1):
The system of claim 4, wherein the controller is further configured to: apply, as part of the write operation, a pre-read voltage to the first memory cell; wherein determining whether the write operation is of the type that increases the magnitude of the threshold voltage is based on applying the pre-read voltage.
Claim 5:
The device of claim 4, wherein the pre-read voltage is applied to determine an existing state of the memory cell.
Claim 7 (dependent on claims 6, 4, and 1):
The system of claim 6, wherein the pre-read voltage is applied to determine an existing state of the first memory cell, and determining whether the write operation is of the type that increases the magnitude of the threshold voltage comprises comparing the existing state to a target state for the first memory cell.
Claim 6:
The device of claim 1, wherein the controller is further configured to determine the type of write operation by comparing an existing state of the memory cell to a target state.
Claim 7 (dependent on claims 6, 4, and 1):
The system of claim 6, wherein the pre-read voltage is applied to determine an existing state of the first memory cell, and determining whether the write operation is of the type that increases the magnitude of the threshold voltage comprises comparing the existing state to a target state for the first memory cell.
Regarding independent claim 8 and the dependent claims 9-18, U.S. Patent No. 12,131,778 B2 anticipates all limitations of all the claims.
Instant Application
U.S. Patent
Independent Claim 8:
A system comprising: a memory array;
and a controller configured to: perform at least one read operation on at least one memory cell of the array; store a characteristic associated with the memory cell; and select, for performing a write operation, a write pulse based on the characteristic.
Independent Claim 1:
A system comprising:
a memory array including memory cells;
memory configured to store a record associated with prior read operations for the memory cells;
and a controller configured to:
apply pulses to the memory cells when performing read and write operations, wherein for the write operations the pulses include at least one first write pulse, and at least one second write pulse of a greater magnitude than the first write pulse;
perform at least one read operation on at least one first memory cell of the memory array;
in response to performing the read operation, add a first entry associated with the first memory cell to the record;
select, for performing a write operation on the first memory cell, a write pulse based on the record stored in the memory,
wherein the selecting comprises determining that the first entry is in the record, and in response to determining that the first entry is in the record, selecting the second write pulse; and apply the second write pulse to the first memory cell for performing the write operation.
Claim 9:
The system of claim 8, wherein the controller is further configured to apply, as part of the write operation, a pre-read voltage to the memory cell.
Claim 6 (dependent on claims 4, and 1):
The system of claim 4, wherein the controller is further configured to: apply, as part of the write operation, a pre-read voltage to the first memory cell; wherein determining whether the write operation is of the type that increases the magnitude of the threshold voltage is based on applying the pre-read voltage.
Claim 10:
The system of claim 9, wherein the pre-read voltage is applied to determine an existing state of the memory cell, and the controller is further configured to compare the existing state to a target state.
Claim 7 (dependent on claims 6, 4, and 1):
The system of claim 6, wherein the pre-read voltage is applied to determine an existing state of the first memory cell, and determining whether the write operation is of the type that increases the magnitude of the threshold voltage comprises comparing the existing state to a target state for the first memory cell.
Claim 11:
The system of claim 8, further
comprising a random number generator, wherein storing the characteristic is based on a random number generated by the random number generator.
Claim 8 (dependent on claim 1):
The system of claim 1, further comprising a random number generator, wherein adding the first entry to the record is performed based on a random number generated by the random number generator.
Claim 12:
The system of claim 8, further comprising a counter configured to count a number of read operations associated with memory cells of the array.
Claim 9 (dependent on claim 1):
The system of claim 1, further comprising a counter configured to count a number of read operations associated with at least a portion of the memory cells, wherein adding the first entry to the record is performed based on the number of read operations.
Claim 13:
The system of claim 12, wherein storing the characteristic is performed based on the number of read operations.
Claim 9 (dependent on claim 1):
The system of claim 1, further comprising a counter configured to count a number of read operations associated with at least a portion of the memory cells, wherein adding the first entry to the record is performed based on the number of read operations.
Claim 14:
The system of claim 8, further comprising sensing circuitry configured to sense at least one current through the memory cell during the read operation.
Claim 10 (dependent on claim 1):
The system of claim 1, further comprising sensing circuitry configured to sense at least one current through the first memory cell during the read operation.
Claim 15:
The system of claim 8, wherein the at least one memory cell stores bits for a codeword, and the read operation is performed in response to receiving a read command for an address corresponding to the codeword.
Claim 11 (dependent on claim 1):
The system of claim 1, wherein the at least one first memory cell stores bits for a codeword, and the read operation is performed in response to receiving a read command for an address corresponding to the codeword.
Claim 16:
The system of claim 15, wherein the write operation is performed in response to receiving a write command to write a codeword corresponding to the address.
Claim 12 (dependent on claim 1):
The system of claim 1, wherein the first entry is an address in the memory array, and the write operation is performed in response to receiving a write command to write a codeword corresponding to the address.
Claim 17:
The system of claim 8, wherein the controller is further configured to: compare a count associated with the read operation to a random number; and determine that the count matches the random number.
Claim 13 (dependent on claim 1):
The system of claim 1, wherein the controller is further configured to: compare a count associated with the read operation to a random number; and determine that the count matches the random number; wherein adding the first entry to the record is further in response to determining that the count matches the random number.
Claim 18:
The system of claim 8, wherein the read operation is associated with an address of a codeword stored in the memory array.
Claim 14 (dependent on claim 1):
The system of claim 1, wherein the
read operation is associated with an address of a codeword stored in the memory array, and the first entry added to the record is the address.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 7 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 recites the limitation "the write pulse" in line 1. There is insufficient antecedent basis for this limitation in the claim.
Independent claim 1--which claim 7 depends upon--recites in line 1, “a write pulse” and “the enhanced write pulse”. It is unclear if “the write pulse” of claim 7 is referring to the phrase “a write pulse” or “the enhanced write pulse” presented in claim 1. Indefinite language is identified.
Following the procedure set forth in MPEP 2173.06 (II), for the purposes of compact prosecution, “the write pulse” of claim 7 is interpreted to descend from “a write pulse” of claim 1.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Philipp (US 7,571,901 B2).
Regarding independent claim 1, Philipp teaches a device (col. 15 line 38: a system) comprising:
a memory array (col. 15 line 40: a memory device);
and a controller configured to (col. 15 lines 44: a circuit configured to program): determine whether to enhance a write pulse based on a type of write operation (Fig. 7; col. 15 lines 50-59);
and in response to determining to enhance the write pulse, apply the enhanced write pulse to at least one memory cell in the memory array (Fig. 7; col. 15 lines 53-54).
In Figure 7, a flowchart of an operating method details the programming of a resistive memory element to a desired target resistance by repeatedly measuring the resistance of the memory element and reprogramming the memory element until the desired target resistance is achieved.
This reads on selecting and applying an enhanced write pulse to a memory cell in the memory array because, with regards to a phase change memory device, a level of current or voltage (e.g., of higher levels than a reference signal) is taught to be calculated during the step write pulse calculation step 414 in order to successfully program the memory element to a different resistance level (e.g., a resistance level greater than an initial resistance level).
Regarding claim 2, Philipp teaches the device of claim 1,
wherein the type of write operation increases a magnitude of a threshold voltage of the memory cell (col. 1 lines 30-36 and lines 51-54). “Threshold voltage” is understood with respect to the standard activation process for the activation transistor in a resistive memory element, e.g., 1T1R. However, a resistive phase change memory element experiences varying resistance levels due to the application of varying temperatures and cool down times that cause the material makeup of the memory element to alternate between amorphous and crystalline states.
When a certain resistance level is achieved by the phase change memory element, this translates to a change in the “threshold” of the cell. The change in threshold is attributed to an applied write pulse, whereby, the cell can be programmed to a higher or lower resistance level (i.e., a write pulse that programs the cell from crystalline to the amorphous state means the cell attains a higher resistance level (i.e., threshold voltage)).
Regarding claim 3, Philipp teaches the device of claim 1,
wherein the type of write operation is a RESET on SET write operation (FIG. 3: resistance states 200a, 200b, 200c, and 200d; see also col. 1 lines 44-48: memory may change from the amorphous state to the crystalline state and from the crystalline state to the amorphous state).
Figure 3 illustrates the following four resistance states for a memory element: substantially amorphous state 200a (i.e., highest resistance state), partially crystalline and partially amorphous state 200b (second highest resistance state), crystalline state 200c (i.e., second lowest resistance state), substantially crystalline state 200d (i.e., lowest resistance state).
When the memory element is programmed to substantially amorphous state 200a, this means the memory element is reset to the highest resistance state (i.e., stored data “00”).
When the memory element is programmed to substantially crystalline state 200d, this means the memory element is set to the lowest resistance state (i.e., stored data “11”).
A reset write operation occurring after a set write operation is possible (e.g., programming the memory element to state 200d and then to state 200a) because of the reversible nature of phase change as undergone by the phase change materials used in phase change memory devices.
Regarding claim 7, Philipp teaches the device of claim 1,
wherein the write pulse is a first write pulse (FIG. 7: write memory element 406; see also col. 12 lines 32-34: At 406, a write pulse or pulses including the best guess parameter is applied to the selected phase change element 106),
and the controller (FIG. 2: controller 120, phase change elements 106a, 106b, etc.) is further configured to:
determine whether to enhance a second write pulse based on a type of write operation (FIG. 7: measure resistance of memory element 408, is measured resistance within range of target resistance 410; see also col. 12 lines 45-46: At 408, the resistance of the selected phase change element 106 is measured or sensed; and col. 12 lines 49-51: At 410, the measured resistance of the selected phase change element 106 is compared to the target resistance);
and in response to determining not to enhance the second write,
apply the second write pulse using a magnitude less than a magnitude of the enhanced write pulse (FIG. 7: programming complete 412; see also col. 12 lines 51-57: If the measured resistance of the selected phase change element 106 is within a predetermined range…of the target resistance…programming of the selected phase change element 106 is complete at 412).
When a first write pulse is a standard write pulse, and a second write pulse is an enhancement of the standard write pulse, and the controller determines to apply the standard write pulse instead of the enhanced version, this reads on the limitation of applying a second write pulse that is of a magnitude less than the magnitude of the enhanced write pulse. This is because in the instances when an enhanced write pulse (i.e. the standard write pulse of a greater amplitude) is not necessary, a standard write pulse is being applied by default.
Claims 8, 12-16, and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kwon et al. (US 9,646,687 B2).
Regarding independent claim 8, Kwon teaches a system comprising:
a memory array (FIG. 17: memory cell array 410);
and a controller (FIG. 17: memory controller 401, and control logic 430) configured to:
perform at least one read operation on at least one memory cell of the array (col. 2 lines 30-33: a control logic for controlling…a read operation…with respect to the memory cell array);
store a characteristic associated with the memory cell (col. 6 lines 14-17: control logic 130…may be used to monitor memory operations (e.g., write and/or read operations) directed to the memory device 100; see also col. 6 lines 30-43: “For example [in the case of monitoring write operations] control logic 130 may be used (e.g.,) to count a number [of] received write commands, which would disclose to those skilled in the art that when the read operations are monitored, then the number of received read commands would instead be counted);
and select, for performing a write operation, a write pulse based on the characteristic (col. 6 lines 35-39: For example, the control logic 130 may cause execution of the recovery operation with respect to a particular memory cell region whenever the write cycle with respect to the memory cell array 110 reaches a particular value; see also col. 6 lines 2-6: The effects of the reset wear out phenomenon may be mitigated by applying a so-called ‘recovery pulse’ to the target memory cell, where the recovery pulse is greater than the reset write pulse normally applied during the reset write operation).
Regarding claim 12, Kwon teaches the system of claim 8,
further comprising a counter configured to
count a number of read operations associated with memory cells of the array (col. 6 lines 14-17: control logic 130…may be used to monitor memory operations (e.g., write and/or read operations) directed to the memory device 100; see also col. 6 lines 42-43: control logic 130 may be used (e.g., to count a number [of] received write commands).
The control logic unit which executes “counting” of memory operations reads on the definition of a “counter” module as known in the field of art. Also, counting read operations in addition to write operations falls within the list of potential responsibilities described for the control logic unit of Kwon.
Regarding claim 13, Kwon teaches the system of claim 12,
wherein storing the characteristic (Instant application discloses in the Specification, paragraphs 76 and 77, an exemplary “characteristic” is “a read count” or “data associated with an expected risk of the imprint effect”; Kwon records a number of read operations for at least one memory cell which satisfies the claimed “characteristic” in col. 6 lines 14-17: control logic 130…may be used to monitor memory operations (e.g., write and/or read operations) directed to the memory device 100; see also col. 6 lines 30-43: “For example [in the case of monitoring write operations] control logic 130 may be used (e.g.,) to count a number [of] received write commands, which would disclose to those skilled in the art that when the read operations are monitored, then the number of received read commands would instead be counted) is performed based on the number of read operations (col. 6 lines 14-17: control logic 130…may be used to monitor memory operations (e.g., write and/or read operations) directed to the memory device 100; see also col. 6 lines 42-43: control logic 130 may be used (e.g.,) to count a number [of] received write commands).
Regarding claim 14, Kwon teaches the system of claim 8,
further comprising sensing circuitry configured to
sense at least one current through the memory cell during the read operation (FIG. 2: SA 121; see also col. 8 lines 39-48: during a read operation, the write/read circuit…the sense amplifier 121 may include a current generator (or a voltage generator), and in order to determine data, the sense amplifier 121 may include a comparator that is connected to a node (e.g., a sensing node) of the bit line BL).
Regarding claim 15, Kwon teaches the system of claim 8,
wherein the at least one memory cell stores bits for a codeword, and the read operation is performed in response to receiving a read command for an address corresponding to the codeword (col. 6 lines 39-42: In making the determination as to whether or not a recovery operation should be performed in relation to a received write command, a corresponding address may be further considered by the control logic 130; see also col. 6 lines 47-55: the recovery controller 132 may check at least one address bit of the address, and a memory cell region including a memory cell to which the write data is to be written may be detected. In this regard, separate write cycle values may be maintained for each one of the designated memory cell regions, and whenever a write cycle with respect to a particular memory cell region reaches its reference value, the recovery operation may be performed in relation that memory cell region).
The address of a memory cell in a memory cell array is unique. This uniqueness allows a specific memory cell to be easily targeted during a memory operation, and individually monitored. Specifying the target memory cell using its unique address in write and/or read commands reads on the limitation, granted that a memory cell storing a codeword is equivalent to the unique address of the memory cell.
Regarding claim 16, Kwon teaches the system of claim 15,
wherein the write operation is performed in response to receiving a write command to write a codeword corresponding to the address (col. 6 lines 39-42; see also col. 6 lines 47-55).
The address of a memory cell in a memory cell array is unique. This uniqueness allows a specific memory cell to be easily targeted during a memory operation, and individually monitored. Specifying the target memory cell using its unique address in write and/or read commands reads on the limitation. This is because a memory cell, the stored codeword of the memory cell, and the unique address of the memory cell all address the same “unique entity”. Therefore, writing to a memory cell corresponding to a specified memory cell address is equivalent to writing a codeword corresponding to the specified codeword address.
Regarding claim 18, Kwon teaches the system of claim 8,
wherein the read operation is associated with an address of a codeword stored in the memory array (col. 6 lines 39-42; see also col. 6 lines 47-55; see also col. 10 lines 4-8: In other embodiments of the inventive concept, all of the address bit values in both the row address…and the column address… portions of an address will be checked when a recovery operation is to be performed in a unit of singularly designated memory cells).
The address of a memory cell in a memory cell array is unique. This uniqueness allows a specific memory cell to be easily targeted during a memory operation, and individually monitored. Specifying the target memory cell using its unique address in write and/or read commands reads on the limitation. This is because a memory cell, the stored codeword of the memory cell, and the unique address of the memory cell all address the same “unique entity”. Therefore, writing and reading to a memory cell corresponding to a specified memory cell address is equivalent to writing and reading a codeword corresponding to the specified codeword address.
Regarding independent claim 19, Kwon teaches a method comprising (FIG. 14: flowchart summarizing an operating method):
determining, by a controller (col. 5 lines 49-54: control logic 130 may be used to control the periodic execution of a so-called “recovery operation”),
that a risk of imprint exceeds a threshold and dynamically selecting, based on the risk (col. 6 lines 14-17: used to monitor memory operations (e.g., write and/or read operations; see also col. 6 lines 17-20: determine whether or not it is necessary to perform a recovery operation; see also col. 6 lines 35-39: for example…execution of the recovery operation…whenever the write cycle…reaches a particular value (e.g., first reference value)),
a regular write pulse or an enhanced write pulse (col. 6 lines 2-6: the recovery pulse is greater than the reset write pulse normally applied during the reset write operation).
Figure 14 is a determination flowchart for a memory device for whether to proceed with a recovery operation by monitoring a count of write operations. When the write count is calculated to have exceeded a maximum threshold write count, a recovery pulse is generated. Recovery pulses, illustrated in Figure 13, can be a pulse that is greater in amplitude (i.e. voltage level) than the reset write pulse normally applied during a reset write operation (col. 6 lines 2-6).
The recovery operation serves to “prevent degradation in the reliability of stored data due to the conventionally understood ‘reset wear out phenomenon’” (col. 5 lines 49-51) when a reset write operation is performed, a filament associated with the target memory cell may not be ‘cut’ in a manner sufficient to enable the state of the memory cell to be changed to the reset state” (col. 5 lines 64-67 and col. 6 lines 1-2). This reads on determining if a risk of imprint exceeds a threshold – with respect to the definition of an “imprint” effect being a “segregation of electrical states in the memory cells which degrades the ability to reset the memory cells (e.g., by performing a RESET on SET write operation” (i.e., a cell being unable to perform a reset operation after a set operation) as defined in the application’s specification – that would require selecting a regular write pulse or an enhanced write pulse, based on the risk.
Regarding claim 20, Kwon teaches the method of claim 19,
wherein the risk is based on a number of read operations (col. 6 lines 39-43: thus, if the recovery operation is executed whenever a number of executed write operations reaches the first reference value, the control logic 130 may be used (e.g.,) to count a number received write commands; see also col. 6 lines 25-29).
A count of read operations can replace the count of write operations prerequisite for conducting a recovery operation. Philipp discloses, “the control logic may be used to determine whether or not execution of a recovery operation is necessary for each respective memory cell region by monitoring at least one ‘memory operation’ (e.g. a read, write, and/or erase operation)”(col. 6 lines 25-29).
This means the risk can be based on a number of read operations considering that both read and write operations, in excess, can disturb the memory elements such that the reset operation eventually fails. Whereby, Kwon teaches that tracking the count of one memory operation over another is not significantly different for the purpose of satisfying the conditions for executing a recovery operation.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
Claims 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Philipp (US 7,571,901 B2) as applied to claim 1 above, and further in view of Lee et al. (US 11,367,484 B1).
Regarding claim 4, Philipp teaches the device of claim 1.
Philipp does not teach the controller is further configured to: apply a pre-read voltage to the memory cell; and determine the type of write operation based on applying the pre-read voltage.
Lee teaches the controller (Lee, FIG. 1: memory controller 120) is further configured to:
apply a pre-read voltage to the memory cell (Lee, FIG. 5: Apply a first pre-read voltage to memory cells 501);
and determine the type of write operation based on applying the pre-read voltage (Lee, col. 6 lines 30-32: controller 120 initiates a programming operation by applying a first pre-read voltage to memory cells 110; see also col. 7 lines 52-55: a memory cell may be read…to determine the stored state of the memory cell; and col. 9 lines 50-53: After determining the existing programming state of each memory cell…the controller makes a determination of a mode of programming to use for programming the memory cells).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the memory device of Philipp to incorporate Lee’s teachings of a pre-read step during a programming operation, that is controllable by a memory controller, in order to determine the existing programming state of a memory cell prior to write and determine what write pulse(s) would be most suitable to apply.
Philipp and Lee are analogous art to the claimed invention as both are directed to resistive memory, in particular, phase change memory (PCM). A common endeavor in the field is ensuring reliable resistance states of the memory cells as according to Philipp, “the amount of crystalline material coexisting with amorphous material should be precisely controlled to ensure consistent resistance values for multi-bit storage” (col. 2 lines 11-14).
Improvement in reliability ties into improvement in cycling endurance of a PCM memory device when the device is able to withstand a greater number of write/read cycles. A technique known in the art is to limit the application of strong current and/or voltage pulses (i.e., programming and read signals) since PCM cells change state in response to temperature changes caused by, according to Philipp, “driving current through the phase change material itself…or through a resistive heater adjacent the phase change material” (Philipp, col. 1 lines 48-51). Overheating of a cell can damage the phase change material of the cell and cause performance issues like unintended change in resistance value over time (i.e., drift).
One of ordinary skill in the art would have been motivated to modify the memory device of Philipp to incorporate the conditional pre-read operation taught by Lee in order to alleviate the strain that excessive use of strong pulses can have on the lifespan of a resistive memory device.
Regarding claim 5, the combination of Philipp and Lee teaches the device of claim 4,
wherein the pre-read voltage is applied to determine an existing state of the memory cell (Lee, col. 5 lines 56-64: sensing circuitry 122…used to sense a state of each memory cell…senses a current…caused by applying the pre-read voltage).
Regarding claim 6, the combination of Philipp and Lee teaches the device of claim 1,
wherein the controller (Lee, FIG. 1: memory controller 120) is further configured to determine the type of write operation by comparing an existing state of the memory cell to a target state (Lee, col. 6 lines 44-50: controller 120 determines whether the existing programming state and the target programming state for each cell are equal. If the existing and target programming states are equal, then no write voltage is applied…programming states are different, then a write voltage is applied).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the memory device of Philipp to incorporate Lee’s teachings of a pre-read step during a programming operation, that is controllable by a memory controller, in order to determine the existing programming state of a memory cell prior to write and determine what write pulse(s) would be most suitable to apply to achieve the target programming state.
Philipp and Lee are analogous art to the claimed invention as both are directed to resistive memory, in particular, phase change memory (PCM). A common endeavor in the field is ensuring reliable resistance states of the memory cells as according to Philipp, “the amount of crystalline material coexisting with amorphous material should be precisely controlled to ensure consistent resistance values for multi-bit storage” (col. 2 lines 11-14).
Improvement in reliability directly ties into improvement in cycling endurance of a PCM memory device when the device is able to withstand a greater number of write/read cycles. A technique known in the art is to limit the application of strong current and/or voltage pulses (i.e., programming and read signals) since PCM cells change state in response to temperature changes caused by, according to Philipp, “driving current through the phase change material itself…or through a resistive heater adjacent the phase change material” (Philipp, col. 1 lines 48-51). Overheating of a cell can damage the phase change material of the cell and cause performance issues like unintended change in resistance value over time (i.e., drift).
One of ordinary skill in the art would have been motivated to modify the memory device of Philipp to incorporate the conditional pre-read operation taught by Lee in order to alleviate the strain that inefficient application of programming pulses can have on the lifespan of a resistive memory device.
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al. (US 9,646,687 B2) as applied to claim 8, and further in view of Lee et al. (US 11,367,484 B1).
Regarding claim 9, Kwon teaches the system of claim 8.
Kwon does not teach the controller is further configured to apply, as part of the write operation, a pre-read voltage to the memory cell.
Lee teaches the controller (Lee, FIG. 1: memory controller 120) is further configured to apply,
as part of the write operation (Lee, col. 6 lines 29-32: In response to receiving the write command, controller 120 initiates a programming operation by applying a first pre-read voltage to memory cells 110),
a pre-read voltage to the memory cell (Lee, FIG. 5: Apply a first pre-read voltage to memory cells 501).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the memory device of Kwon to incorporate Lee’s teachings of a pre-read step during a programming operation, that is controllable by a memory controller, in order to determine the existing programming state of a memory cell prior to write.
Kwon and Lee are analogous art to the claimed invention as both are directed to resistive memory, in particular, phase change memory (PCM). A common endeavor in the field is ensuring reliable resistance states of the memory cells as according to Philipp, “the amount of crystalline material coexisting with amorphous material should be precisely controlled to ensure consistent resistance values for multi-bit storage” (col. 2 lines 11-14).
Improvement in reliability ties into improvement in cycling endurance of a PCM memory device when the device is able to withstand a greater number of write/read cycles. A technique known in the art is to limit the application of strong current and/or voltage pulses (i.e., programming and read signals) since PCM cells change state in response to temperature changes caused by, according to Philipp, “driving current through the phase change material itself…or through a resistive heater adjacent the phase change material” (Philipp, col. 1 lines 48-51). Overheating of a cell can damage the phase change material of the cell and cause performance issues like unintended change in resistance value over time (i.e., drift).
One of ordinary skill in the art would have been motivated to modify the memory device of Kwon to incorporate the conditional pre-read operation taught by Lee in order to alleviate the strain that excessive use of strong pulses can have on the lifespan of a resistive memory device.
Regarding claim 10, the combination of Kwon and Lee teaches the system of claim 9,
wherein the pre-read voltage is applied to determine an existing state of the memory cell (Lee, col. 5 lines 56-64: sensing circuitry 122…used to sense a state of each memory cell…senses a current…caused by applying the pre-read voltage).,
and the controller (Lee, FIG. 1: memory controller 120) is further configured to
compare the existing state to a target state (Lee, col. 6 lines 30-32: controller 120 initiates a programming operation by applying a first pre-read voltage to memory cells 110; see also col. 7 lines 52-55: a memory cell may be read…to determine the stored state of the memory cell; and col. 9 lines 50-53: After determining the existing programming state of each memory cell…the controller makes a determination of a mode of programming to use for programming the memory cells).
Allowable Subject Matter
Claims 11 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 11, the closest prior art, Kwon, teaches the system of claim 8 (see prior paragraph regarding claim 8).
Kwon does not teach the system further comprising a random number generator, wherein storing the characteristic is based on a random number generated by the random number generator.
Regarding claim 17, the closest prior art, Kwon, teaches the system of claim 8 (see prior paragraph regarding claim 8).
Kwon does not teach the controller is further configured to:
compare a count associated with the read operation to a random number;
and determine that the count matches the random number.
Conclusion
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/N.T.P./Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825
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