Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I and Species I (fig. 1) directed to claims 1-12 in the reply filed on 8/19/2026 is acknowledged.
Claims 13-19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected subject matter
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-9 and 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US PG. Pub. 2022/0174816).
Regarding claim 1 – Kim teaches a circuit module (figs. 3 & 11) comprising: a circuit substrate (fig. 11, 1000A [paragraph 0146] Kim states, “one electronic component 200 may be mounted on the printed circuit board 1000A”); and a product (200); wherein the circuit substrate (fig. 3, 1000A) includes: a multilayer body (see multilayer body of 110, 120 & 130) including a plurality of resin layers (121 & 111 [paragraph 0041 & 0054] Kim states, “the first insulating layer 111, at least one of a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide…the second insulating layer 121, at least one of a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide”) stacked on each other in a direction of a Z axis (see fig. 3), each of the plurality of the resin layers (121 & 111) including a positive main surface (top surface of resin layer 121) positioned on a positive side of the Z axis; a mounting electrode (122 [paragraph 0060] Kim states, “the pad 122 may be a conductive material such as copper (Cu)”) on the positive main surface of a resin layer (121) which is positioned farther toward the positive side of the Z axis than other resin layers of the plurality of resin layers (claimed structure shown in figure 3); an inner conductive layer (112 [paragraph 0046] Kim states, “he first wiring layer 112 may be a conductive material such as copper (Cu)”) provided in the multilayer body (110/120/130) and overlapping the mounting electrode (122) as seen in the direction of the Z axis (see fig. 3); and a first interlayer connection conductor (123 [paragraph 0052] Kim states, “via 123”) extending through a resin layer (121) of the plurality of the resin layers in the direction of the Z axis, an end (top end) of the first interlayer connection conductor (123) on the positive side (top side) of the Z axis contacts the mounting electrode (122), and an end (bottom end) of the first interlayer connection conductor (123) on a negative side (bottom side) of the Z axis contacts the inner conductive layer (112); the product (fig. 11, 200) includes: a connector solid-phase (200S [paragraph 0146 & 0149] Kim states, “connection conductor 200S…The connection conductor 200S may be formed of solder, but is not limited thereto, and a conductive material may be used without limitation”) bonded to the mounting electrode (122); the first interlayer connection conductor (fig. 3, 123) includes a first region (123B) and a second region (123A); the first region (123B) and the second region (123A) are sequentially provided in a direction toward the negative side of the Z axis in order of the first region (123B) and the second region (123A); the mounting electrode (122) is in contact with the first region (123B); and a Young's modulus of the second region (123A) is lower than a Young's modulus of the first region (123B [paragraph 0066] Kim states, “the first metal layer 123A and the second metal layer 123B may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The material of forming each of the first metal layer 123A and the second metal layer 123B may be the same or different from each other”; the first region can be selected to be copper (Young’s modulus of 117GPa), and the second region can be selected to be tin (Young’s modulus of 47GPa); see attached NPL from engineeringtoolbox.com).
Regarding claim 2 – Kim teaches the circuit module according to Claim 1, wherein a volume of the first region (fig. 3, 123B) is about 30% or higher of a volume of the first interlayer connection conductor (123; figure 3 shows the first region 123B being magnitudes greater (5X or more) than that of the second region 123A which is a seed layer, therefore the first region takes up 30% or higher volume than the entire interlayer connection conductor 123).
Regarding claim 3 – Kim teaches the circuit module according to Claim 1, wherein a material (fig. 3, copper as described in rejection of claim 1 above) of the first region (fig. 3, 123B) is the same as a material of the mounting electrode (122, copper as described in rejection to claim 1 above).
Regarding claim 4 – Kim teaches the circuit module according to Claim 3, wherein the material of the first region (fig. 3, 123B) and the material of the mounting electrode (122) are copper (both are copper as stated in paragraph 0060 & 0066 as quoted in the rejection to claim 1 above), aluminum, or silver.
Regarding claim 5 – Kim teaches the circuit module according to Claim 1, wherein a material of the second region (fig. 3, 123A) is an alloy including tin as a main component (second region 123A is listed to include tin and alloys thereof in paragraph 0066 as quoted in the rejection to claim 1 above).
Regarding claim 6 – Kim teaches the circuit module according to Claim 1, wherein the circuit substrate (fig. 3, 1000A) includes a second interlayer connection conductor (113 [paragraph 0049] Kim states, “A material of the first via 113 may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof”) positioned farther toward the negative side (bottom/lower side) of the Z axis than the first interlayer connection conductor (123) and extends through a resin layer (111) of the plurality of the resin layers (111 & 121) in the direction of the Z axis; and a Young's modulus of the second interlayer connection conductor (113) is lower than the Young's modulus of the first region (123B; via 113 is made of tin (Sn) and has a Young’s modulus of 47GPa and the first region 123B made of Copper (Cu) with a Young’s modulus of 117GPa; see comparison of tin and copper as described in the rejection to claim 1 above).
Regarding claim 7 – Kim teaches the circuit module according to Claim 6, wherein a material of the second interlayer connection conductor (fig. 3, 113) is an alloy including tin as a main component ([paragraph 0049] Kim states, “A material of the first via 113 may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof”).
Regarding claim 8 – Kim teaches the circuit module according to Claim 1, wherein the circuit substrate (fig. 3, 1000A) includes a protection layer (140 [paragraph 0085] Kim states, “first protective layer 140”) covering the positive main surface (top surface) of the resin layer (121) positioned farther toward the positive side of the Z axis than the other resin layers (see fig. 3).
Regarding claim 9 – Kim teaches the circuit module according to Claim 1, wherein a material of the plurality of resin layers (fig. 3, 121 & 111) is a thermoplastic resin (121 & 111 [paragraph 0041 & 0054] Kim states, “the first insulating layer 111, at least one of a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide…the second insulating layer 121, at least one of a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide”).
Regarding claim 11 – Kim teaches the circuit module according to Claim 1, wherein a Young's modulus of a lower half (fig. 3, half including part of first region and all of second region) of the first interlayer connection conductor (123) is different from a Young's modulus of an upper half (half including only first region) of the first interlayer connection conductor (123; The lower half having the copper and tin elements will have a different Young’s modulus that that of the upper half only have the copper element).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. in view of Yanagisawa et al. (US PG. Pub. 2017/0040249).
Regarding claim 10 – Kim teaches the circuit module according to Claim 1, but fails to teach wherein a material for a surface of the connector is gold.
Yanagisawa teaches a circuit module (fig. 15, 2) wherein a material for a surface of the connector (62) is gold ([paragraph 0123] Yanagisawa states, “The terminals 62 of the semiconductor chip 60 include solder bumps or gold bumps etc.”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit module having a product with a connector solid-phase bonded to the mounting electrode as taught by Kim with the material for a surface of the connector being gold as taught by Yanagisawa because gold is known to be highly conductive and resistant to corrosion allowing for a long service life.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. in view of Takada et al. (US PG. Pub. 2020/0091104).
Regarding claim 12 – Kim teaches the circuit module according to Claim 1, but fails to teach wherein the first interlayer connection conductor has a truncated cone shape.
Takada teaches a circuit module (fig. 1) having a first interlayer connection conductor (combination of via features 23 & 32) wherein the first interlayer connection conductor (23/32) has a truncated cone shape (figure 1 shows a taper shape of the interlayer connection conductor 23/32 [paragraph 0134] Takada states, “the opening in the protection film and the via hole in the insulating sheet each have the tapered shape”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit module with a circuit substrate that has a first interlayer connection conductor as taught by Kim with the first interlayer connection conductor having a truncated cone shape as taught by Takada because Takada states, “When the opening in the protection film and the via hole in the insulating sheet each have the tapered shape, it is possible to make the maximum diameter of the bonding layer greater than the maximum diameter of the via conductor when forming the bonding layer through the opening of the protection film” [paragraph 0124].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ahn et al. (US Patent 10455708) discloses a multilayer substrate with two-layer vias.
Enomoto et al. (US PG. Pub. 6831235) discloses a printed-circuit board with two-layer vias.
Asai et al. (US Patent 6534723) discloses a multilayer PCB and semiconductor device with two-layer vias.
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/STEVEN T SAWYER/Primary Examiner, Art Unit 2847
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