Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
1. The office acknowledges the receipt of the following and placed of record in the file: Amendment dated 7/13/ 2026.
2. Claims 1-20 are presented for examination.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Felix et al. (“Felix”), US 20210190835 and Mark Alen Lenkin (“Lenkin”), EP 2711725.
Regarding Claims 1 and 12, Felix teaches a method of monitoring a clock signal at a circuit, the method comprising:
receiving, at a delay monitor [Para: 0008(“receiving at a tap sampled delay line …”) and 0068(“tap sampled delay line 52”)], a gateable clock signal [Para: 0008(as “producing a set of samples of the first clock signals” from tapping of the delay line where “the first clock signal is delayed version of the sampled clock signal”, see 0009 or gateable clock) and 0049(“removing a portion of the clock pulses”)];
analysing, by the delay monitor, the clock signal to generate a measurement value [Para: 0008(“determining a magnitude of the voltage droop by measuring from the set of samples” by measuring clock edge position (see 0014) of first clock signal from delay line)], wherein the measurement value is responsive to the clock signal and/or a voltage [Para: 0068(“delay lines 51, 52 are such that the time taken for a signal to propagate through each stage (i.e. the delay associated with each stage) is dependent upon the voltage supplied to them”)]; and
comparing, by the delay monitor, the measurement value with a threshold [Para: 0014 and 0068(“By measuring the position of the edge of the first clock signal and comparing it to an average position …”)]; and
storing the measurement value for further analysis based on comparison [Para: 0084 (“The fine average filter 55 receives different output values from the encoder 54 … for a detected position of the clock edge”)].
Felix does not disclose expressly storing the measurement value when the comparison does not meet the threshold; or
discarding the measurement value when the measurement value meets the threshold.
In the same field of endeavor (e.g., measuring phase noise in clock signal for clock signal used for sampling as statistical data ensuring integrity), Lenkin teaches storing the measurement value when the comparison does not meet the threshold; or
discarding a measurement value when the measurement value meets a threshold [Para: 0055(when “phase noise energy meet 20 Hrtz may be removed from sampled data” as historical baseline value of a clock signal, discard sampled data that is of questionable data etc.)].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Felix’s teachings of analyzing, by the delay monitor, the clock signal to generate a measurement value which is responsive to the clock signal and/or a voltage with Lenkin’s teachings of discarding the measurement value when the measurement value meets the threshold would allow Felix to achieve an accurate result from the frequency to determine a droop value in every iteration in order to have an efficient system.
Regarding Claims 2 and 13, Felix teaches wherein the method comprises:
generating a plurality of measurement values during a sampling period [Para: 0008(“producing a set of samples of the first clock signals” for clock cycle periods as stated in para 0080)].
Regarding Claims 3 and 14, Felix teaches wherein the method comprises:
generating, by the delay monitor, a measurement value for each clock cycle within the sampling period [Para: 0008(“determining a magnitude of the voltage droop by measuring from the set of samples” by measuring clock edge position (see 0014) of first clock signal from delay line for clock cycle periods as stated in para 0080)].
Regarding Claims 4 and 15, Felix teaches wherein the method comprises:
generating statistical data, wherein the statistical data is based on the plurality of measurement values generated during the sampling period [Para: 0008(“determining a magnitude of the voltage droop by measuring from the set of samples” by measuring clock edge position (see 0014) of first clock signal from delay line for clock cycle periods as stated in para 0080)].
Regarding Claim 5, Felix teaches wherein the method comprises:
determining, by the delay monitor, from the statistical data, the maximum measurement value and/or minimum measurement value during the sampling period [Para: 0068 and 0084(“… averages these values over time to produce an average value (shown as RDL_FINE_AVG[5:0]) for a detected position of the clock edge”)].
Regarding Claims 6 and 16, Felix teaches wherein the method comprises:
sending, by the delay monitor, the statistical data to a system control processor [Fig-3(see the signal from droop detector 13 to processor 2 and see para 0048-0049)].
Regarding Claim 7, Felix teaches wherein the measurement value corresponds to the number of gates traversed by the clock signal in a delay line of the delay monitor during a clock cycle, and wherein the measurement value corresponds to the output of an encoder [Fig-5(at the output of encoder of encoder 54)].
Regarding Claims 8 and 17, One of ordinary skill in the art would make the threshold is a programmable threshold, and receiving, by the delay monitor, the programmable threshold from firmware and utilizing a GPU based on user requirement in order to satisfy user criteria and to have an efficient system.
Regarding Claim 9, Felix teaches wherein the voltage is supplied by a power distribution network [see Fig-1-3, 5 and 7].
Regarding Claim 10, Felix teaches determining a dynamic voltage variation based on or in response to the measurement value [Para: 0068(“The change in the position of the edge of the first clock signal indicates a change in V.sub.DD”)].
Regarding Claim 11, Felix teaches where the delay monitor and the circuit are driven by the same gateable clock signal [See clock circuit 4 in Fig-3 and 5].
Regarding Claim 18, Felix teaches Claim 12, implemented in at least one packaged chip (single chip-2);
at least one system component (MPIC 7); and
a board, wherein the at least one packaged chip (single chip 2) and the at least one system component (MPIC 7) are assembled on the board [Para: 0044 and Fig-1].
Regarding Claim 19, Felix teaches claim 18 assembled on a further board with at least one other product (13) component [Fig-1].
Regarding Claim 20, Felix teaches computer-readable medium to store computer-readable code for fabrication of the circuitry of claim 12 [Para: 0044(machine learning require software code to execute)].
Response to Arguments
4. Applicant's arguments filed on 7/13/2026 have been fully considered but they are not persuasive. Applicant argues regarding claim 1 that “Felix Fails to Disclose the Required Comparing of a Measurement Value with a Threshold”. Claim simply recites “analyzing, by the delay monitor, the clock signal to generate a measurement value, wherein the measurement value is responsive to the clock signal … comparing, by the delay monitor, the measurement value with a threshold” where threshold means “a point or a place for beginning” , “ a point at which physiological effect begins” (according to dictionary definition) or simply be a point with which the comparison takes place by the delay monitor. Felix teaches a delay monitor analyze clock signal/s to generate a measurement values by producing a set of samples of the clock signal (of processor) to determine a change in clock edge position and then compare the measured values with a threshold or an average clock edge position (which is determined before) in order to determine a “deviation in the clock edge position from the average clock position” [para: 0008-0014]. In other words, Felix is comparing the measured value with a point or threshold such as an average clock edge position, in order to determine deviation which ultimately determines a delay in clock paths (and voltage droop). Therefore, Felix teaches the argued feature as to the extant it is claimed.
Applicant further argues that “One skilled in the art would understand that a "threshold" is typically a static or programmable limit. The "average position" in Felix is a dynamically calculated baseline derived from previous measurements … These are distinct technical functions”. However, this is not claimed.
Applicant further argues that Lenkin does not teach “storing the measurement value for further analysis when the comparison does not meet the threshold" and "discarding the measurement value when the measurement value meets the threshold" because Lenkin determines which data to discard by identifying data points that are considered invalid or unreliable due to hardware-level errors, rather than by comparing a measurement value to a performance threshold and Neither Felix nor Lenkin supply a threshold-based comparison for filtering data. Examiner disagrees.
Felix and Lenkin both teach a threshold-based comparison. First, Felix teaches analyzing, by the delay monitor, the clock signal to generate a measurement value, wherein the measurement value is responsive to the clock signal … comparing, by the delay monitor, the measurement value with a threshold. On the other hand, Lenkin teaches discarding a measurement value when measurement value meets a point or a threshold as set forth above. The combination of Felix and Lenkin teaches the argued feature.
Second, it appears that the applicant is arguing the references individually. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED H REHMAN whose telephone number is (571)272-1412. The examiner can normally be reached 8.00 - 5.00.
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/MOHAMMED H REHMAN/Primary Examiner, Art Unit 2176
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