DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. KR10-2023-0175381 and KR10-2024-0103301, filed on 12/06/2023 and 8/02/2024 respectively.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/24/2024, 03/31/2025, 9/29/2025 and 2/12/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6, 9-11 is/are rejected under 35 U.S.C. 102(a1) as being anticipated by Choi et al. (KR 101497608, hereinafter Choi).
Regarding to claim 1, Choi discloses an insert module for test hander (fig. 1 shows a test socket), comprising:
a pitch adjuster (fig. 2[10]) configured to seat at least one electronic device (fig. 2[50]) thereon, and comprising
a first side electrically (fig. 2 [top side of 10]) connected to connection pins of the electronic device (fig. 2 shows [10] with pads 15 connected to pins 51 of 50), and
a second side (fig. 2 [bottom side of 10]) provided with electrical contact means (fig. 2 [bottom side of 10] with pads 16) at a second pitch wider than a first pitch of the connection pins (fig. 2 shows pitch of 16s wider than 15s); and
a holder configured to hold the seated electronic device (fig. 1-2 show holder to hold device 50).
Regarding to claim 2, Choi discloses the insert module of claim 1, wherein the electronic device comprises a high bandwidth memory (abstract discloses test socket used when inspecting a semiconductor which includes high bandwidth memory).
Regarding to claim 3, Choi discloses the insert module of claim 2, wherein the pitch adjuster (fig. 2[10]) is configured to electrically connect with the connection pins at a plurality of points (fig. 2 shows [10] with plurality connection pins 15).
Regarding to claim 4, Choi discloses the insert module of claim 3, wherein the first pitch is 0.5 mm or less (first pattern 12 having the same pitch as the terminal 51 of the package 50 and the pitch of the first pattern 12 is 0.35 mm or less).
Regarding to claim 5, Choi discloses the insert module of claim 4, wherein the second pitch is 2 to 10 times the first pitch.
Choi discloses a first pattern (first pitch) from .35 mm or less and a second pattern 13 (second pitch) having the same pitch as the contact pad 2a of the test board 2 and the pitch of the second pattern 13 is 0.5 mm or more, thus when the first pitch is equal or less than .25 mm then the second pitch is time the first pitch.
Regarding to claim 6, Choi discloses the insert module of claim 3, wherein the pitch adjuster comprises: a plurality of first pins arranged at the first pitch (fig. 2 shows [10] with pads 15 at the first pitch 12); and a plurality of second pins arranged at the second pitch (fig. 2 shows [10] with second pads 16 at the second pitch 13).
Regarding to claim 9, Choi discloses the insert module of claim 6, wherein the pitch adjuster (fig. 2[10]) further comprises a pitch adjusting block provided between the first pin (fig. 2[15]) and the second pin (fig. 2[16]), and the pitch adjusting block comprises a plurality of connectors to electrically connect the first pins and the second pins (fig. 2 shows wire [14] connect 15 to 16), respectively.
Regarding to claim 10, Choi discloses the insert module of claim 9, wherein at least some of the conductors are provided at an angle (fig. 2 shows 14s at angle).
Regarding to claim 11, Choi discloses the insert module of claim 6, wherein the holder comprises: an upper block (fig. 2[40]) formed with a hole (fig. 2[41]) in a center portion thereof to pass the electronic device (fig. 2[50]) therethrough; and a lower block (fig. 2[20]) provided with the pitch adjuster (fig. 2[10]) in a center portion thereof (fig. 2[21]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi as applied to claim 6 above, and further in view of Naito et al. (WO 0161364, provided by applicant, hereinafter Naito).
Regarding to claim 7, Choi discloses the insert module of claim 6, except wherein the first pin has a width of 0.2 mm or less.
NAITO discloses the IC have the size of 5-15 mm and contact tips 171 have a gap 178 of 0.5 to 1.0 mm from the second contact tips 172 to accommodate a solder ball 202 having a diameter of 0.3 mm to 0.7 mm.
Therefore, at the time before the effective filing date, it would be obvious to a POSITA to have the width of 0.2 mm or less as matter of design choice to conform with a specific IC.
Regarding to claim 8, Choi discloses the insert module of claim 6, except wherein the second pin has a diameter of 0.3 mm to 3 mm.
NAITO discloses the IC have the size of 5-15 mm and contact tips 171 have a gap 178 of 0.5 to 1.0 mm from the second contact tips 172 to accommodate a solder ball 202 having a diameter of 0.3 mm to 0.7 mm.
Therefore, at the time before the effective filing date, it would be obvious to a POSITA to have the second pin has a diameter of 0.3 mm to 3 mm as matter of design choice to conform with a specific IC.
Claim(s) 12-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi as applied to claim 11 above, and further in view of Cho (KR 102139584, hereinafter Cho).
Regarding to claim 12, Choi discloses the insert module of claim 11, except wherein the holder further comprises a latching link having a first side rotatably connected to the upper block and a second side rotatably connected to the lower block.
Cho discloses a socket device for semiconductor included a pitch adjuster 210 where the socket comprises a latching link (231) rotatably to connect the upper block 200 to lower block (combination of 220 and 210).
Therefore, at the time before the effective filing date, it would be obvious to a POSITA to incorporate the latch in order to form and secure the test socket.
Regarding to claim 13, Choi in view of Cho discloses the insert module of claim 12, except wherein the latching link is configured to pivot upward upon the upper block moving close to the lower block.
The latch as shown in fig. 3 of Cho include 231 rotate inward to connect the upper block to the lower block. However, the claim does not claim a specific structure of the latch.
Therefore, at the time before the effective filing date, it would be obvious to a POSITA to a to design a latch to pivot upward instead of inward as a matter of design choice without unexpected result.
Regarding to claim 14, Choi in view of Cho discloses the insert module of claim 13, wherein the latching link further comprises a latching unit, and wherein one side of the latching unit is rotatably connected to the upper block, wherein a pushing block configured to press an upper portion of the electronic device is provided on the other side of the latching unit (fig .8 of Cho shows a latching link included the latching unit 812 connect to upper block 810 to press the upper portion of device D).
Regarding to claim 15, Choi in view of Cho discloses the insert module of claim 14, further comprising at least one elastic unit provided between the upper block and the lower block, and providing a restoring force to return the upper block to an original position (fig. 7-8 of Cho shows spring 2311 and 813).
Regarding to claim 16, Choi in view of Cho discloses the insert module of claim 13, wherein the pushing block comprises a thermal pad provided at an end portion thereof to be in contact with the electronic device (fig .8 of Cho show 812 in contact with D and consider as thermal pad).
Claim(s) 17 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Na et al (KR 20110011462, hereinafter Na), and further in view of Choi.
Regarding to claim 17, Na discloses a test tray for an electronic device (fig. 5 show test tray included carrier board 200), comprising:
a board comprising a lower portion configured to electrically connect with a tester (fig. 4 shows carrier board 200 with circuit board 220 connected to tester);
an insert module configured to hold the electronic device loaded therein during a test (fig. 1 shows insert 100); and
a base frame configured to arrange the plurality of insert modules thereon (fig. 5 shows plurality of 100 arrange in 200).
However, Na does not disclose the insert module comprising:
a pitch adjuster configured to seat the electronic device thereon, and comprising a first side electrically connected to connection pins of the electronic device, and a second side provided with electrical contact means at a second pitch wider than a first pitch of the connection pins; and a holder configured to hold the seated electronic device.
Fig. 1-2 of Choi shows an insert comprising:
a pitch adjuster (fig. 2[10]) configured to seat the electronic device thereon (fig. 2[50]), and comprising a first side (fig. 2 [top side of 10]) electrically connected to connection pins of the electronic device (fig. 2 shows [10] with pads 15 connected to pins 51 of 50), and a second side (fig. 2 [bottom side of 10]) provided with electrical contact means (fig. 2 [bottom side of 10] with pads 16) at a second pitch wider than a first pitch of the connection pins (fig. 2 shows pitch of 16s wider than 15s); and a holder (fig. 1-2 show holder) configured to hold the seated electronic device (fig. 2[50]).
Regarding to claim 20, Na in view of Choi discloses the test tray of claim 17, wherein the electronic device comprises a high bandwidth memory (HBM) (abstract discloses test socket used when inspecting a semiconductor which is included high bandwidth memory).
Claim(s) 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Na in view of Choi as applied to claim 17 above, and further in view of Bischof et al. (US 20070001703 hereinafter Bischof).
Regarding to claim 18, Na in view of Choi discloses the test tray of claim 17, further comprising: a sub-tray comprising a lower portion configured to electrically connect with the board (fig. 5 of Na shows a sub-tray which is a portion of 200 i.e. 2 right columns of 100 considered as sub-tray), and configured to arrange the plurality of insert modules thereon (plurality of inserts 100 arranged at 2 right columns).
Even if Na in view of Choi does not disclose a sub-tray, Bischof discloses a concept of test tray comprising two arrangement modules (the arrangement module interpreted as sub-tray of the test tray).
Therefore, at the time before the effective filing date, it would be obvious to a POSITA to incorporate Bischof into Na in view of Choi in order to have the test tray for different type of IC by exchanging the arrangement modules.
Regarding to claim 19, Na in view of Choi and Bischof discloses the test tray of claim 18, wherein the sub-tray is detachably configured in the board (Bischof shows the detachable sub-trays).
Conclusion
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/SON T LE/ Primary Examiner, Art Unit 2858
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