DETAILED ACTION
Claims 1-24 are pending.
The office acknowledges the following papers:
Claims, specification, and remarks filed on 5/11/2026.
Withdrawn objections and rejections
The specification objections have been withdrawn due to amendment.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the "right to exclude" granted by a patent and to prevent possible harassment by multiple assignees. See In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970);and, In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent is shown to be commonly owned with this application. See 37 CFR 1.130(b).
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
Applicants can file an eTerminal Disclaimer (eTD) in utility applications filed under 35 U.S.C. 111(a) or in compliance with 35 U.S.C. 371, and design applications. Filing an eTD via EFS-Web is highly recommended due to an extensive backlog for processing paper TDs. However, applicants may still file a TD for manual review.
Claims 1-24 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-24 of U.S. Patent No. 12,130,915 in view of Reid et al. (U.S. 2019/0163902), in view of Mukherjee et al. (U.S. 2017/0286315), in view of Official Notice.
Instant Application
U.S. Patent No. 12,130,915
1. A processor core comprising:
1. A processor core comprising:
an instruction fetch circuit to fetch instructions;
an instruction fetch circuit to fetch instructions;
storage for a data structure comprising a plurality of entries that each include an address space identifier (ASID) and a privilege level bit; and
storage for a data structure comprising a plurality of entries that each include a thread identification (TID) and a privilege level bit; and
a branch predictor, coupled to the instruction fetch circuit and the storage, to predict a target instruction corresponding to a branch instruction based on at least one entry of the plurality of entries in the storage, and cause the target instruction to be fetched by the instruction fetch circuit.
a branch predictor, coupled to the instruction fetch circuit and the storage, to predict a target instruction corresponding to a branch instruction based on at least one entry of the plurality of entries in the storage, and cause the target instruction to be fetched by the instruction fetch circuit.
Claims 9 and 17 are similar to claim 1 and are rejected for the same reasons. Dependent claims 2-8, 10-16, and 18-24 are read upon by the dependent claims 2-8, 10-16, and 18-24 of U.S. Patent No. 12,130,915.
New Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-24 are rejected under 35 U.S.C. 103 as being unpatentable over Reid et al. (U.S. 2019/0163902), in view of Mukherjee et al. (U.S. 2017/0286315), in view of Official Notice.
As per claim 1:
Reid and Mukherjee disclosed a processor core comprising:
an instruction fetch circuit to fetch instructions (Reid: Figure 2 element 6, paragraph 119);
storage for a data structure comprising a plurality of entries that each include an address space identifier (ASID) and a privilege level bit (Mukherjee: Figures 2-3 elements 240 and 304-306, paragraphs 30-34)(Reid: Figure 2 elements 2 and 37, paragraph 119-120)(Mukherjee disclosed an invalidation tracking structure (ITS) with entries that include exception level bits (i.e. privilege level bit) and a ASID field. The combination implements the ITS and TLBI instructions of Mukherjee into the processor of Reid for implementing faster TLB invalidations.); and
a branch predictor, coupled to the instruction fetch circuit and the storage (Mukherjee: Figures 2-3 elements 240 and 304-306, paragraphs 30-34)(Reid: Figures 2 elements 4-6, paragraph 119)(The combination implements the ITS and TLBI instructions of Mukherjee into the processor of Reid for implementing faster TLB invalidations.), to predict a target instruction corresponding to a branch instruction based on at least one entry of the plurality of entries in the storage, and cause the target instruction to be fetched by the instruction fetch circuit (Mukherjee: Figures 2-3 elements 240 and 304-306, paragraphs 30-34)(Reid: Figures 2-3 and 9 elements 4, 37, 140-144, and 152, paragraphs 119, 121, and 138)(The branch predictor predicts for branch instructions at a fetch address if a branch is taken or not. Predicted taken branches output target addresses to the fetch queue for fetching instructions from. The combination implements the ITS and TLBI instructions of Mukherjee into the processor of Reid for implementing faster TLB invalidations. Official notice is given that page faults are generated when TLB misses occur for the advantage of bringing the requested instruction from external memory to main memory. Thus, it would have been obvious to one of ordinary skill in the art to implement page faults for a TLB miss in Reid. In view of the above official notice, predictions occur based on hits to the TLB occurring for the fetch address, which are present due to the lack of a TLBI instruction invalidating them. Additionally, in view of the official notice, a hit within the TLB can occur based on a previously invalidated entry from a TLBI instruction.).
The advantage of TLBI instructions and the corresponding invalidation tracking structure is that TLB entries can be more quickly removed (Mukherjee: Paragraphs 3 and 28). Thus, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date to implement the TLBI instructions and ITS of Mukherjee into the processing system of Reid for the above advantage.
As per claim 2:
Reid and Mukherjee disclosed the processor core of claim 1, wherein the privilege level bit is selectable between a kernel and a user level (Mukherjee: Figures 2-3 elements 240 and 304-306, paragraphs 30-34)(Reid: Figure 2 element 37, paragraphs 57, 74-75, and 120)(Mukherjee disclosed exception levels from 0-4. Official notice is that exception level 0 is a user level and exception level 1 is an OS kernel level in ARM systems. Thus, it would have been obvious to one of ordinary skill in the that the exception levels 0-4 include both user and kernel levels.).
As per claim 3:
Reid and Mukherjee disclosed the processor core of claim 2, wherein the plurality of entries each include a software mode identifier (Mukherjee: Figures 2-3 elements 240 and 304-306, paragraphs 30-34)(Reid: Figure 2 element 37, paragraph 120)(Official notice is given that TLBs include entries with protection keys (i.e. software mode ID) for the advantage of increased security. Thus, it would have been obvious to one of ordinary skill in the art to implement protection keys within the TLB entries of Reid and the ITS of Mukherjee.).
As per claim 4:
The additional limitation(s) of claim 4 basically recite the additional limitation(s) of claim 3. Therefore, claim 4 is rejected for the same reason(s) as claim 3.
As per claim 5:
Reid and Mukherjee disclosed the processor core of claim 1, wherein the branch predictor is to predict the target instruction corresponding to the branch instruction without being controlled by a different privilege domain (Reid: Figure 2 elements 4-6, paragraph 119)(Reid makes no mention of domains when performing branch predictions.).
As per claim 6:
Reid and Mukherjee disclosed the processor core of claim 1, wherein the address space identifier comprises a virtual identification (ID) that differentiates virtual-to-physical mappings in use (Mukherjee: Figures 2-3 elements 240 and 304-306, paragraphs 30-34)(Reid: Figure 2 element 37, paragraph 120).
As per claim 7:
Reid and Mukherjee disclosed the processor core of claim 1, wherein the plurality of entries are for return instructions (Mukherjee: Figures 2-3 elements 240 and 304-306, paragraphs 30-34)(Reid: Figure 2 elements 4 and 37, paragraphs 103 and 119-120)(Branch instructions can include function returns. Thus, performing address translations for function returns uses the TLB entries. Additionally, the ITS allows for invalidating TLB entries related to function returns.).
As per claim 8:
Reid and Mukherjee disclosed the processor core of claim 1, further comprising a key register to store cryptographically sealed assets that indicate a privilege level of executing software (Mukherjee: Figures 2-3 elements 240 and 304-306, paragraphs 30-34)(Reid: Figure 2 elements 4 and 37, paragraphs 119-120)(Official notice is given that key registers can be used to store protected key data for the advantage of reducing attacks. Thus, it would have been obvious to one of ordinary skill in the art to implement a key register in Reid that indicates privilege levels.).
As per claim 9:
Claim 9 essentially recites the same limitations of claim 1. Therefore, claim 9 is rejected for the same reasons as claim 1.
As per claim 10:
The additional limitation(s) of claim 10 basically recite the additional limitation(s) of claim 2. Therefore, claim 10 is rejected for the same reason(s) as claim 2.
As per claim 11:
The additional limitation(s) of claim 11 basically recite the additional limitation(s) of claim 3. Therefore, claim 11 is rejected for the same reason(s) as claim 3.
As per claim 12:
The additional limitation(s) of claim 12 basically recite the additional limitation(s) of claim 4. Therefore, claim 12 is rejected for the same reason(s) as claim 4.
As per claim 13:
The additional limitation(s) of claim 13 basically recite the additional limitation(s) of claim 5. Therefore, claim 13 is rejected for the same reason(s) as claim 5.
As per claim 14:
The additional limitation(s) of claim 14 basically recite the additional limitation(s) of claim 6. Therefore, claim 14 is rejected for the same reason(s) as claim 6.
As per claim 15:
The additional limitation(s) of claim 15 basically recite the additional limitation(s) of claim 7. Therefore, claim 15 is rejected for the same reason(s) as claim 7.
As per claim 16:
The additional limitation(s) of claim 16 basically recite the additional limitation(s) of claim 8. Therefore, claim 16 is rejected for the same reason(s) as claim 8.
As per claim 17:
Claim 17 essentially recites the same limitations of claim 1. Claim 17 additionally recites the following limitations:
for a match in the storage of a current instruction pointer for a branch instruction to an entry of the plurality of entries in the storage, predict a target instruction corresponding to the branch instruction and cause the target instruction to be fetched by the instruction fetch circuit (Mukherjee: Figures 2-3 elements 240 and 304-306, paragraphs 30-34)(Reid: Figures 2-3 and 9 elements 4, 37, 140-144, and 152, paragraphs 119, 121, and 138)(The branch predictor predicts for branch instructions at a fetch address if a branch is taken or not. Predicted taken branches (i.e. matches) output target addresses to the fetch queue for fetching instructions from. The combination implements the ITS and TLBI instructions of Mukherjee into the processor of Reid for implementing faster TLB invalidations. Official notice is given that page faults are generated when TLB misses occur for the advantage of bringing the requested instruction from external memory to main memory. Thus, it would have been obvious to one of ordinary skill in the art to implement page faults for a TLB miss in Reid. In view of the above official notice, predictions occur based on hits to the TLB occurring for the fetch address, which are present due to the lack of a TLBI instruction invalidating them. Additionally, in view of the official notice, a hit within the TLB can occur based on a previously invalidated entry from a TLBI instruction.) and,
for no match in the storage of the current instruction pointer to the plurality of entries in the storage, cause a next sequential instruction pointer from the current instruction pointer to be fetched by the instruction fetch circuit (Mukherjee: Figures 2-3 elements 240 and 304-306, paragraphs 30-34)(Reid: Figures 2-3 and 9 elements 4, 37, 140-144, and 152, paragraphs 119, 121, and 138)(The combination implements the ITS and TLBI instructions of Mukherjee into the processor of Reid for implementing faster TLB invalidations. In view of the above official notice, a page fault occurs based on not hitting the TLB (i.e. no match) for the fetch address. Once the page fault is resolved and the instruction for the fetch address is brought into the processor, fetching, decoding, and branch prediction resume. The branch predictor predicts for branch instructions at a fetch address if a branch is taken or not. Not predicted taken branches output sequential addresses to the fetch queue for fetching instructions from, which is performed after the page fault is resolved.).
As per claim 18:
The additional limitation(s) of claim 18 basically recite the additional limitation(s) of claim 2. Therefore, claim 18 is rejected for the same reason(s) as claim 2.
As per claim 19:
The additional limitation(s) of claim 19 basically recite the additional limitation(s) of claim 3. Therefore, claim 19 is rejected for the same reason(s) as claim 3.
As per claim 20:
The additional limitation(s) of claim 20 basically recite the additional limitation(s) of claim 4. Therefore, claim 20 is rejected for the same reason(s) as claim 4.
As per claim 21:
The additional limitation(s) of claim 21 basically recite the additional limitation(s) of claim 5. Therefore, claim 21 is rejected for the same reason(s) as claim 5.
As per claim 22:
The additional limitation(s) of claim 22 basically recite the additional limitation(s) of claim 6. Therefore, claim 22 is rejected for the same reason(s) as claim 6.
As per claim 23:
The additional limitation(s) of claim 23 basically recite the additional limitation(s) of claim 7. Therefore, claim 23 is rejected for the same reason(s) as claim 7.
As per claim 24:
The additional limitation(s) of claim 24 basically recite the additional limitation(s) of claim 8. Therefore, claim 24 is rejected for the same reason(s) as claim 8.
Response to Arguments
The arguments presented by Applicant in the response, received on 5/11/2026 are considered persuasive.
Applicant argues for claim 1:
“The cover page of Reid (see the excerpt thereof reproduced below for convenience) indicates (i) a filing date of October 2, 2018 (thus AFTER the Applicant's effective filing date of June 28, 2018), and (ii) that it is a continuation-in-part of application number 15/825,524 filed on November 29, 2017. However, the Office action relies on multiple portions of Reid that are not present in parent application number 15/825,524, and thus are not prior art to the Applicant's application. For example, the Office action on pages 3-4 refers to FIG. 20 and paragraph [0176] of Reid, but that disclosure does not appear to be present within the parent application No. 15/825,524, and thus that disclosure is not entitled to the November 29, 2017 filing date.”
This argument is found to be persuasive for the following reason. The examiner agrees that the CIP application doesn’t include figure 20, which shows details of TLB entries. Instead, Reid only shows a generic TLB in figure 2 that has a proper prior art date that can be used in a rejection. A new non-final rejection has been applied based on the above arguments.
Conclusion
The following is text cited from 37 CFR 1.111(c): In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB A. PETRANEK whose telephone number is (571)272-5988. The examiner can normally be reached on M-F 8:00-4:30.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on (571) 270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JACOB PETRANEK/Primary Examiner, Art Unit 2183
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