DETAILED ACTION
Claims 1-24 are pending.
The office acknowledges the following papers:
IDS filed on 1/23/2025.
Priority
The effective filing date for the subject matter defined in the pending claims in this application is 6/28/2018.
Drawings
The Examiner contends that the drawings submitted on 10/24/2024 are acceptable for examination proceedings.
Specification
The disclosure is objected to because of the following informalities:
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. The Applicant’s cooperation is requested in correcting any errors of which the Applicant may become aware.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: “MICROARCHITECTURAL MECHANISMS FOR THE PREVENTION OF SIDE-CHANNEL ATTACKS USING A ADDRESS SPACE IDENTIFIER (ASID) AND A PRIVILEGE LEVEL BIT”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-24 are rejected under 35 U.S.C. 103 as being unpatentable over Reid et al. (U.S. 2019/0163902), in view of Official Notice.
As per claim 1:
Reid disclosed a processor core comprising:
an instruction fetch circuit to fetch instructions (Reid: Figure 2 element 6, paragraph 119);
storage for a data structure comprising a plurality of entries that each include an address space identifier (ASID) and a privilege level bit (Reid: Figure 20 element 4, paragraph 176)(The translation lookaside buffer (i.e. data structure) includes entries that store fields for an ASID and privilege level.); and
a branch predictor, coupled to the instruction fetch circuit and the storage (Reid: Figures 2 and 20 elements 4-6, paragraphs 119 and 176), to predict a target instruction corresponding to a branch instruction based on at least one entry of the plurality of entries in the storage, and cause the target instruction to be fetched by the instruction fetch circuit (Reid: Figures 2-3, 9, and 20 elements 4, 140-144, and 152, paragraphs 119, 121, 138, and 176-178)(The branch predictor predicts for branch instructions at a fetch address if a branch is taken or not. Predicted taken branches output target addresses to the fetch queue for fetching instructions from. Official notice is given that page faults are generated when TLB misses occur for the advantage of bringing the requested instruction from external memory to main memory. Thus, it would have been obvious to one of ordinary skill in the art to implement page faults for a TLB miss in Reid. In view of the above official notice, predictions occur based on hits to the TLB occurring for the fetch address.).
As per claim 2:
Reid disclosed the processor core of claim 1, wherein the privilege level bit is selectable between a kernel and a user level (Reid: Figure 20 element 4, paragraphs 57, 74-75, and 176).
As per claim 3:
Reid disclosed the processor core of claim 2, wherein the plurality of entries each include a software mode identifier (Reid: Figure 20 element 4, paragraph 176)(Official notice is given that TLBs include entries with protection keys (i.e. software mode ID) for the advantage of increased security. Thus, it would have been obvious to one of ordinary skill in the art to implement protection keys within the TLB entries of Reid.).
As per claim 4:
The additional limitation(s) of claim 4 basically recite the additional limitation(s) of claim 3. Therefore, claim 4 is rejected for the same reason(s) as claim 3.
As per claim 5:
Reid disclosed the processor core of claim 1, wherein the branch predictor is to predict the target instruction corresponding to the branch instruction without being controlled by a different privilege domain (Reid: Figures 2 and 20 elements 4-6, paragraphs 119 and 176)(Reid makes no mention of domains when performing branch predictions.).
As per claim 6:
Reid disclosed the processor core of claim 1, wherein the address space identifier comprises a virtual identification (ID) that differentiates virtual-to-physical mappings in use (Reid: Figure 20 element 4, paragraph 176).
As per claim 7:
Reid disclosed the processor core of claim 1, wherein the plurality of entries are for return instructions (Reid: Figures 2 and 20 element 4, paragraphs 103, 119, and 176)(Branch instructions can include function returns. Thus, performing address translations for function returns uses the TLB entries.).
As per claim 8:
Reid disclosed the processor core of claim 1, further comprising a key register to store cryptographically sealed assets that indicate a privilege level of executing software (Reid: Figures 2 and 20 element 4, paragraphs 119 and 176)(Official notice is given that key registers can be used to store protected key data for the advantage of reducing attacks. Thus, it would have been obvious to one of ordinary skill in the art to implement a key register in Reid that indicates privilege levels.).
As per claim 9:
Claim 9 essentially recites the same limitations of claim 1. Therefore, claim 9 is rejected for the same reasons as claim 1.
As per claim 10:
The additional limitation(s) of claim 10 basically recite the additional limitation(s) of claim 2. Therefore, claim 10 is rejected for the same reason(s) as claim 2.
As per claim 11:
The additional limitation(s) of claim 11 basically recite the additional limitation(s) of claim 3. Therefore, claim 11 is rejected for the same reason(s) as claim 3.
As per claim 12:
The additional limitation(s) of claim 12 basically recite the additional limitation(s) of claim 4. Therefore, claim 12 is rejected for the same reason(s) as claim 4.
As per claim 13:
The additional limitation(s) of claim 13 basically recite the additional limitation(s) of claim 5. Therefore, claim 13 is rejected for the same reason(s) as claim 5.
As per claim 14:
The additional limitation(s) of claim 14 basically recite the additional limitation(s) of claim 6. Therefore, claim 14 is rejected for the same reason(s) as claim 6.
As per claim 15:
The additional limitation(s) of claim 15 basically recite the additional limitation(s) of claim 7. Therefore, claim 15 is rejected for the same reason(s) as claim 7.
As per claim 16:
The additional limitation(s) of claim 16 basically recite the additional limitation(s) of claim 8. Therefore, claim 16 is rejected for the same reason(s) as claim 8.
As per claim 17:
Claim 17 essentially recites the same limitations of claim 1. Claim 17 additionally recites the following limitations:
for a match in the storage of a current instruction pointer for a branch instruction to an entry of the plurality of entries in the storage, predict a target instruction corresponding to the branch instruction and cause the target instruction to be fetched by the instruction fetch circuit (Reid: Figures 2-3, 9, and 20 elements 4, 140-144, and 152, paragraphs 119, 121, 138, and 176-178)(The branch predictor predicts for branch instructions at a fetch address if a branch is taken or not. Predicted taken branches (i.e. matches) output target addresses to the fetch queue for fetching instructions from. Official notice is given that page faults are generated when TLB misses occur for the advantage of bringing the requested instruction from external memory to main memory. Thus, it would have been obvious to one of ordinary skill in the art to implement page faults for a TLB miss in Reid. In view of the above official notice, predictions occur based on hits to the TLB occurring for the fetch address.) and,
for no match in the storage of the current instruction pointer to the plurality of entries in the storage, cause a next sequential instruction pointer from the current instruction pointer to be fetched by the instruction fetch circuit (Reid: Figures 2-3, 9, and 20 elements 4, 140-144, and 152, paragraphs 119, 121, 138, and 176-178)( In view of the above official notice, a page fault occurs based on not hitting the TLB (i.e. no match) for the fetch address. Once the page fault is resolved and the instruction for the fetch address is brought into the processor, fetching, decoding, and branch prediction resume. The branch predictor predicts for branch instructions at a fetch address if a branch is taken or not. Not predicted taken branches output sequential addresses to the fetch queue for fetching instructions from, which is performed after the page fault is resolved.).
As per claim 18:
The additional limitation(s) of claim 18 basically recite the additional limitation(s) of claim 2. Therefore, claim 18 is rejected for the same reason(s) as claim 2.
As per claim 19:
The additional limitation(s) of claim 19 basically recite the additional limitation(s) of claim 3. Therefore, claim 19 is rejected for the same reason(s) as claim 3.
As per claim 20:
The additional limitation(s) of claim 20 basically recite the additional limitation(s) of claim 4. Therefore, claim 20 is rejected for the same reason(s) as claim 4.
As per claim 21:
The additional limitation(s) of claim 21 basically recite the additional limitation(s) of claim 5. Therefore, claim 21 is rejected for the same reason(s) as claim 5.
As per claim 22:
The additional limitation(s) of claim 22 basically recite the additional limitation(s) of claim 6. Therefore, claim 22 is rejected for the same reason(s) as claim 6.
As per claim 23:
The additional limitation(s) of claim 23 basically recite the additional limitation(s) of claim 7. Therefore, claim 23 is rejected for the same reason(s) as claim 7.
As per claim 24:
The additional limitation(s) of claim 24 basically recite the additional limitation(s) of claim 8. Therefore, claim 24 is rejected for the same reason(s) as claim 8.
Conclusion
The following is text cited from 37 CFR 1.111(c): In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections.
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Mukherjee et al. (U.S. 2015/0134931), taught compressing process context IDs.
Podaima et al. (U.S. 2016/0350225), taught speculative pre-fetches.
Mukherjee (U.S. 2016/0140040), taught TLB invalidations.
Mukherjee (U.S. 2017/0286315), taught TLB invalidations.
Parker et al. (U.S. 2020/0371966), taught translation context identifier fields with an ASID field.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB A. PETRANEK whose telephone number is (571)272-5988. The examiner can normally be reached on M-F 8:00-4:30.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on (571) 270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JACOB PETRANEK/Primary Examiner, Art Unit 2183