Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. This office acknowledges receipt of the following item(s) from the Applicant:
Information Disclosure Statement (IDS) was considered.
Papers submitted under 35 U.S.C. 119(a)-(d) have been placed of record in the file.
2. Claims 1-8 are presented for examination.
Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. § 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
4. Claims 1-3 are rejected under 35 U.S.C. § 103(a) as being unpatentable over Yoon US Pub. No. 20180350415 in view of Yoon et al. US Pub. No. 20180336937.
As per claim 1, Figs. 6 and 8 of Yoon ‘415 disclose a semiconductor device comprising: an alignment data generation circuit (Fig. 6)configured to: align first and second latch data (LD1 and LD3) generated from a first group of input data (DD1 and DD2) in synchronization with a first internal strobe signal (DINDQS<1>; output the aligned first and second latch data as first alignment data (AD<1>-AD<4>; align a first and second latch data (LD5 and LD7) generated from a second group of the input data (DD3 and DD4) in synchronization with a second internal strobe signal (DINDQS<3>; output the aligned first and second latch data as second alignment data (AD<9>-AD<12>; and a write data generation circuit (360 of Fig. 2) configured to: generate first and second write data (ID1-ID2) from the first and second alignment data in synchronization with a latch clock (WTEN of 360 of Fig. 2 or 20 of Fig. 1)
Yoon ‘415 fails to disclose the first and second operation mode and wherein the first write data and the second write data have an identical data window in a continuous operation of the first operation mode and the second operation mode. However, Figs. 2, 5 and 7 of Yoon ‘937 disclose the first and second operation mode (Fig. 2, par. 37) and wherein the first write data and the second write data have an identical data window (par. 160) in a continuous operation of the first operation mode and the second operation mode. It would have been obvious to a person of ordinary skill in the art at the time invention was made to modify Yoon ‘415’s write data generation circuit which utilizes the first and second operation mode as taught by Yoon ‘937 in order to control the desired write data bits.
As per claims 2-3, Figs. 1 and 3 of Yoon ‘415 disclose wherein: the first internal strobe signal and the second internal strobe signal are generated in synchronization with a strobe signal (DQS), and the latch clock is generated in synchronization with a clock.
Allowable Subject matter
5. Claims 4-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
6. The following is a statement of reasons for the indication of allowable subject matter:
Claims include allowable subject matter since the prior art made of record and considered pertinent to the applicants’ disclosure, taken individually or in combination, does not teach or suggest the claimed invention having wherein: the input data for generating the first and second latch data in the first operation mode is input as 2N bits, and the input data for generating the first and second latch data in the second operation mode is input as N bits, where N is a natural number in claim 4; wherein the alignment data generation circuit comprises: a first latch configured to generate bits of the first alignment data by latching first and second pre-alignment data that are generated from the first and second latch data in synchronization with the first internal strobe signal; a second latch configured to generate bits of the second alignment data by latching the first and second pre-alignment data in synchronization with the second internal strobe signal; a third latch configured to generate bits of the first alignment data by latching the first and second latch data in synchronization with the first internal strobe signal; and a fourth latch configured to generate bits of the second alignment data by latching the first and second latch data in synchronization with the second internal strobe signal in claim 5; and wherein the write data generation circuit comprises: a fifth latch configured to generate bits of the first write data and bits of first pre-write data by latching bits of the first alignment data in synchronization with the latch clock: a first selection transfer circuit configured to generate bits of the second write data from any one of the bits of the first pre-write data and bits of the second alignment data based on a logic level of a burst enable signal; a sixth latch configured to generate bits of the first write data and bits of the first pre-write data by latching bits of the first alignment data in synchronization with the latch clock; and a second selection transfer circuit configured to generate bits of the second write data from any one of the bits of the first pre-write data and the bits of the second alignment data based on a logic level of the burst enable signal in claim 6.
7. When responding to the office action, Applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner to locate the appropriate paragraphs.
8. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the date of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to HOAI V HO whose telephone number is (571)272-1777. The examiner can normally be reached 7:00 AM -- 5:30 PM from Thursday and Friday of the first week of a bi-week and Tuesday and Wednesday of the second week.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached on (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is (571)-273-8300.
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/HOAI V HO/Primary Examiner, Art Unit 2827
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