Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1, 3, 7, 12, 17, and 20 have been amended. Claims 5-6 are cancelled. Claims 1-4 and 7-20 are currently under review.
Response to Arguments
Applicant's arguments filed August 3, 2026 have been fully considered but they are not persuasive. The Applicant argues at the top of page 13 of the remarks that the amended claims are obvious in view of the cited references.
The Office disagrees. The Applicant further argues at the top of page 14 of the remarks that the first register serves as a means for switching the output mode of the detection circuit while the level of the enable signal serves as a means for switching the output mode of the control circuit, a second register where different values are stored in the register correspond to applying different magnitudes of the data amount threshold for comparing data variation with the data amount threshold, and at the middle of page 14 of the remarks that none of the references teaches any register or method of changing a circuit output signal based on a value stored in a register, however the claim limitations do not specify the same. Additionally the claim limitations do not specify or further define a “first value” and a “second value”, and that the data amount threshold is merely determined by a value stored in the second register without further specifying how the determination is made, therefore the cited references in combination continue to teach the amended claim limitations.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 and 7-19 are rejected under 35 U.S.C. 103 as being unpatentable over Kuei et al. (Pub. No.: US 2018/0374427 A1) hereinafter referred to as Kuei in view of in view of Gu (Pub. No.: US 2004/0100458 A1) and in view of Park et al. (Pub. No.: US 2022/0189365 A1).
With respect to Claim 1, Kuei teaches a panel driving circuit (fig. 2; ¶19) for outputting drive signals to a display panel through a plurality of drive channels (fig. 4; ¶24), the panel driving circuit comprising: a detection circuit (fig. 2, item L1’, L2’, and item 208: for each channel; ¶19, “Note that each of the modules illustrated in FIG. 2 refers to a set of modules in a plurality of channels of the source driver 20”; - a plurality of sets of L1’, L2’, and 208 corresponds to a detection circuit; ¶24, “The comparator 208 may compare the data code of the line data n with the corresponding data code of the line data n+1 in each channel”) configured to, for each of the plurality of drive channels, output a first detection signal in a case of detecting that a data change amount of a drive signal output through the respective drive channel is greater than a data amount threshold (¶24, “a difference value Δch_1 is generated according to the difference between the data code ch_1(n) and the data code ch_1(n+1)”; ¶31, “when the comparator 208 determines that the difference value between the data codes is greater than an upper threshold, the power level of the output driver 206 may be increased” – a first detection signal corresponds to a power level control); and output a second detection signal in a case of detecting that the data change amount of the drive signal output through the respective drive channel is not greater than the data amount threshold (¶24, “a difference value Δch_1 is generated according to the difference between the data code ch_1(n) and the data code ch_1(n+1)”; ¶31, “When the comparator 208 determines that the difference value between the data codes is less than a lower threshold, the power level of the output driver 206 may be decreased. When the comparator 208 determines that the difference value between the data codes is between the upper threshold and the lower threshold, the power level of the output driver 206 may not change” – a second detection signal corresponds to a different power level control); a control circuit (fig. 2, item 208 functions also as a control circuit; ¶19, “Note that each of the modules illustrated in FIG. 2 refers to a set of modules in a plurality of channels of the source driver 20”; - item 208 collectively for all the channels corresponds to a control circuit;) configured to receive the first detection signal and the second detection signal (received internally via computation), and output a first control signal based on the first detection signal (¶31- a first control signal corresponds to a power level control); and output a second control signal based on the second detection signal (¶31 - a second control signal corresponds to a different power level control), wherein the first control signal indicates to boost a slew rate of the panel driving circuit in the respective drive channel (¶31, “when the comparator 208 determines that the difference value between the data codes is greater than an upper threshold, the power level of the output driver 206 may be increased”), and the second control signal indicates not to boost the slew rate of the panel driving circuit in the respective drive channel (¶31, “When the comparator 208 determines that the difference value between the data codes is less than a lower threshold, the power level of the output driver 206 may be decreased. When the comparator 208 determines that the difference value between the data codes is between the upper threshold and the lower threshold, the power level of the output driver 206 may not change”); and an output circuit (fig. 2, item 202, 204, and 206; ¶19, “Note that each of the modules illustrated in FIG. 2 refers to a set of modules in a plurality of channels of the source driver 20”; - a plurality of sets of 202, 204, and 206 corresponds to an output circuit”) configured to receive the first control signal and the second control signal (fig. 2, item 206 receives the first control signal and the second control signal), and output the drive signal to the display panel through the drive channel at a first slew rate based on the second control signal (fig. 5; ¶22; ¶24, “the slew rate or power level of the output driver 206 in the channel ch_1 may be adjusted or controlled according to the difference value Δch_1, so that the output driver 206 may output the data code ch_1(n+1) with an adequate driving capability”); and output the drive signal to the display panel through the drive channel at a second slew rate based on the first control signal (¶22; ¶24, “the slew rate or power level of the output driver 206 in the channel ch_1 may be adjusted or controlled according to the difference value Δch_1, so that the output driver 206 may output the data code ch_1(n+1) with an adequate driving capability”), wherein the second slew rate is a rate after the first slew rate is boosted (fig. 8; ¶22; ¶24; ¶31); wherein the detection circuit comprises a first register (fig. 2, item L1’) and a second register (fig. 2, item L2’), the detection circuit is configured to output the first detection signal (fig. 2, first detection signal = power level control; ¶22) for each of the plurality of drive channels when a value stored in the first register is a first value (¶22, “the comparator 208 may compare the line data n+1 stored in the latch L1′”, line data n+1 = first value; ¶23, “Please note that the data codes in each channel may be compared at the same time”), and the data amount threshold is determined by a value stored in the second register (¶22, “the comparator 208 may generate a signal indicating the power level for the output driver 206 to transmit the line data n+1”; ¶24, “For example, the data code ch_1(n) is compared with the data code ch_1(n+1) in the channel ch_1, and a difference value Δch_1 is generated according to the difference between the data code ch_1(n) and the data code ch_1(n+1). Therefore, the slew rate or power level of the output driver 206 in the channel ch_1 may be adjusted or controlled according to the difference value Δch_1” – the data amount threshold is based on the determined difference between the data codes); wherein the control circuit comprises a plurality of control sub-circuits; wherein a respective one of the plurality of control sub-circuits comprises a gate circuit (fig. 2 is a schematic diagram of a source driver where item 208 functions as a control sub-circuit for a channel, therefore item 208 is also considered a gate circuit since it is disposed in the source driver).
Kuei does not mention the control circuit outputs a first control signal based on the first detection signal and an enable signal; and output a second control signal based on the second detection signal and the enable signal, and wherein the enable signal indicates whether to output the first control signal and the second control signal to control a function of adjusting a slew rate of a corresponding drive channel; wherein a first input terminal of the gate circuit is coupled with an enable signal terminal and configured to receive the enable signal provided by the enable signal terminal; a second input terminal of the gate circuit is coupled with the detection circuit and configured to receive the first detection signal or the second detection signal output by the detection circuit; and an output terminal of the gate circuit is coupled with the output circuit and configured to output the first control signal based on the first detection signal and the enable signal; and output the second control signal based on the second detection signal and the enable signal; wherein a first input terminal of the gate circuit is coupled with an enable signal terminal and configured to receive the enable signal provided by the enable signal terminal; a second input terminal of the gate circuit is coupled with the detection circuit and configured to receive the first detection signal or the second detection signal output by the detection circuit; and an output terminal of the gate circuit is coupled with the output circuit and configured to output the first control signal based on the first detection signal and the enable signal; and output the second control signal based on the second detection signal and the enable signal.
Park teaches a panel driving circuit for outputting drive signals to a display panel through a plurality of drive channels (fig. 2; ¶59; ¶68), the panel driving circuit comprising: a detection circuit (fig. 2, items 102, 101 and figs. 3-4, item XOR) configured to, output a first detection signal in a case of detecting that a data change amount of a drive signal output through the drive channel is greater than a data amount threshold (¶76, “if D1<x> and D2<x> are different from each other, it means there is a big change between the first data and the second data and the slew rate needs to be boosted”); and output a second detection signal in a case of detecting that the data change amount of the drive signal output through the drive channel is not greater than the data amount threshold (¶75, “compare whether D1<x> and D2<x> are the same, and if the two are the same, it means there is a little change between the first data and the second data and the slew rate (i.e. the voltage conversion rate) does not need to be boosted”); a control circuit (figs. 3-4, item 10612) configured to receive the first detection signal and the second detection signal (¶79, item 10612 receives a signal that is either the first detection signal: ‘1’ or the second detection signal: ‘0’), and output a first control signal based on the first detection signal and an enable signal (fig. 3, item OENB; ¶80-81; ¶85); and output a second control signal based on the second detection signal and the enable signal (figs. 3-4, item OENB; ¶80; ¶82; ¶85), wherein the first control signal indicates to boost a slew rate of the panel driving circuit (¶81), and the second control signal indicates not to boost the slew rate of the panel driving circuit (¶82), and wherein the enable signal indicates whether to output the first control signal and the second control signal to control a function of adjusting a slew rate (¶85; ¶87; ¶123-124); and an output circuit (fig. 3, items 10613 and 1062) configured to receive the first control signal and the second control signal, and output the drive signal to the display panel through the drive channel at a first slew rate based on the second control signal (¶83; ¶90); and output the drive signal to the display panel through the drive channel at a second slew rate based on the first control signal, wherein the second slew rate is a rate after the first slew rate is boosted (¶83; ¶90); wherein the control circuit comprises a gate circuit (figs. 3-4, item 10612: D flip-flop is composed of logic circuits which are gate circuits); wherein a first input terminal of the gate circuit is coupled with an enable signal terminal and configured to receive the enable signal provided by the enable signal terminal (figs. 3-4, item OENB); a second input terminal of the gate circuit is coupled with the detection circuit and configured to receive the first detection signal or the second detection signal output by the detection circuit (figs. 3-4, item 10612 is coupled to the output of item 10611); and an output terminal of the gate circuit is coupled with the output circuit and configured to output the first control signal based on the first detection signal and the enable signal (figs. 3-4, item 10612 is coupled to items 10613 and 1062); and output the second control signal based on the second detection signal and the enable signal (¶83; ¶90).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the panel driving circuit of Kuei, such that the control circuit outputs a first control signal based on the first detection signal and an enable signal; and output a second control signal based on the second detection signal and the enable signal, and wherein the enable signal indicates whether to output the first control signal and the second control signal to control a function of adjusting a slew rate of a corresponding drive channel; wherein a first input terminal of the gate circuit is coupled with an enable signal terminal and configured to receive the enable signal provided by the enable signal terminal; a second input terminal of the gate circuit is coupled with the detection circuit and configured to receive the first detection signal or the second detection signal output by the detection circuit; and an output terminal of the gate circuit is coupled with the output circuit and configured to output the first control signal based on the first detection signal and the enable signal; and output the second control signal based on the second detection signal and the enable signal; such that a respective one of the plurality of control sub-circuits of Kuei comprises a gate circuit of Park, resulting in wherein a first input terminal of the gate circuit is coupled with an enable signal terminal and configured to receive the enable signal provided by the enable signal terminal; a second input terminal of the gate circuit is coupled with the detection circuit and configured to receive the first detection signal or the second detection signal output by the detection circuit; and an output terminal of the gate circuit is coupled with the output circuit and configured to output the first control signal based on the first detection signal and the enable signal; and output the second control signal based on the second detection signal and the enable signal, as taught by Park so as to adjust the slew rate in a panel to improve image quality (¶2).
Kuei and Park combined do not teach wherein the gate circuit comprises an AND gate, and only in a case that a potential of the first detection signal received by the second input terminal of the gate circuit, and a potential of the enable signal received by the first input terminal of the gate circuit are both high potential, the control circuit outputs the first control signal based on the first detection signal and the enable signal.
Gu teaches a control circuit (fig. 3, item 42; ¶25) configured to receive a first detection signal and a second detection signal (fig. 3, the output of item 38 is either a first detection signal or a second detection signal; ¶24-25), and output a first control signal based on the first detection signal and an enable signal (¶24, “The data enable signal is used along with the pixel data in the comparator 38 in order to ensure that the first pixel of every scan line is always checked out from the LUT. The comparator 38 outputs a high value if the comparison between the Red_data 1d and the Red_data.sub.--2d is different”); and output a second control signal based on the second detection signal and the enable signal (¶24, “The data enable signal is used along with the pixel data in the comparator 38 in order to ensure that the first pixel of every scan line is always checked out from the LUT. The comparator 38 … outputs a low value if the comparison between Red_data.sub.--1d and Red_data.sub.--2d is the same”), wherein the control circuit comprises a gate circuit (fig. 3, item 42; ¶25, “AND gate 42”); wherein the gate circuit comprises an AND gate (fig. 3, item 42), and only in a case that a potential of the first detection signal received by the second input terminal of the gate circuit, and a potential of the enable signal received by the first input terminal of the gate circuit are both high potential, the control circuit outputs the first control signal based on the first detection signal and the enable signal (¶25, “The first AND gate 42 generates a first comparator output CMP.sub.--1d that is high when the comparison between the Red_data.sub.--1d and the Red_data.sub.--2d is different and the first data enable delay signal DEN.sub.--1d is high”).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the combined panel driving circuit of Kuei and Park by replacing the control circuit of Kuei and Park with the teachings of Gu, resulting in wherein the gate circuit comprises an AND gate, and only in a case that a potential of the first detection signal received by the second input terminal of the gate circuit, and a potential of the enable signal received by the first input terminal of the gate circuit are both high potential, the control circuit outputs the first control signal based on the first detection signal and the enable signal, so as to optimize power consumption (¶2; ¶10) and to provide simple logic for the output of the detection circuit to be used as a control signal for an output circuit.
With respect to Claim 2, claim 1 is incorporated, Kuei teaches wherein the detection circuit is configured to: determine that the data change amount of the drive signal output through the respective drive channel is greater than the data amount threshold in a case of detecting that a difference between a respective data amount of the drive signal output through the respective drive channel at a current moment and a respective data amount of the drive signal output at another moment adjacent to the current moment is greater than a difference threshold (fig. 4; ¶24; ¶31); and determine that the data change amount of the drive signal output through the respective drive channel is not greater than the data amount threshold in a case of detecting that the difference between a respective data amount of the drive signal output through the respective drive channel at the current moment and a respective data amount of the drive signal output at another moment adjacent to the current moment is not greater than the difference threshold (fig. 4; ¶24; ¶31).
With respect to Claim 3, claim 2 is incorporated, Kuei teaches wherein the detection circuit comprises: a storage sub-circuit configured to store the drive signal output through the respective drive channel at the current moment and the drive signal output through the respective drive channel at another moment adjacent to the current moment (figs. 2-3,items L1’ and L2’; ¶19; ¶21); and a comparison sub-circuit configured to compare whether the difference between the respective data amount of the drive signal output through the respective drive channel at the current moment and the respective data amount of the drive signal output at another moment adjacent to the current moment is greater than the difference threshold (fig. 2, item 208; ¶19; ¶22; ¶31), and output the first detection signal and/or the second detection signal based on a comparison result (¶19, the first detection signal and/or the second detection signal is generated by item 208 and used with its own components to generate a power level control).
With respect to Claim 4, claim 1 is incorporated, Kuei teaches wherein the plurality of control sub-circuits are in one-to-one correspondence with the plurality of drive channels (¶19, “Note that each of the modules illustrated in FIG. 2 refers to a set of modules in a plurality of channels of the source driver 20” –each item 208 of each of the channels corresponds to a control sub-circuit).
Kuei and Gu combined do not explicitly mention each of the control sub-circuits being configured to output the first control signal based on the received first detection signal and the enable signal; and output the second control signal based on the received second detection signal and the enable signal.
Park teaches a panel driving circuit for outputting drive signals to a display panel through a plurality of drive channels (fig. 2; ¶59; ¶68), the panel driving circuit comprising: a detection circuit (fig. 2, items 102, 101 and figs. 3-4, item XOR) configured to, output a first detection signal in a case of detecting that a data change amount of a drive signal output through the drive channel is greater than a data amount threshold (¶76, “if D1<x> and D2<x> are different from each other, it means there is a big change between the first data and the second data and the slew rate needs to be boosted”); and output a second detection signal in a case of detecting that the data change amount of the drive signal output through the drive channel is not greater than the data amount threshold (¶75, “compare whether D1<x> and D2<x> are the same, and if the two are the same, it means there is a little change between the first data and the second data and the slew rate (i.e. the voltage conversion rate) does not need to be boosted”); a control circuit (figs. 3-4, item 10612) configured to receive the first detection signal and the second detection signal (¶79, item 10612 receives a signal that is either the first detection signal: ‘1’ or the second detection signal: ‘0’), and output a first control signal based on the first detection signal and an enable signal (fig. 3, item OENB; ¶80-81; ¶85); and output a second control signal based on the second detection signal and the enable signal (figs. 3-4, item OENB; ¶80; ¶82; ¶85), wherein the first control signal indicates to boost a slew rate of the panel driving circuit (¶81), and the second control signal indicates not to boost the slew rate of the panel driving circuit (¶82), and wherein the enable signal indicates whether to output the first control signal and the second control signal to control a function of adjusting a slew rate (¶85; ¶87; ¶123-124); and an output circuit (fig. 3, items 10613 and 1062) configured to receive the first control signal and the second control signal, and output the drive signal to the display panel through the drive channel at a first slew rate based on the second control signal (¶83; ¶90); and output the drive signal to the display panel through the drive channel at a second slew rate based on the first control signal, wherein the second slew rate is a rate after the first slew rate is boosted (¶83; ¶90); wherein the control circuit comprises a gate circuit (figs. 3-4, item 10612: D flip-flop is composed of logic circuits which are gate circuits); wherein a first input terminal of the gate circuit is coupled with an enable signal terminal and configured to receive the enable signal provided by the enable signal terminal (figs. 3-4, item OENB); a second input terminal of the gate circuit is coupled with the detection circuit and configured to receive the first detection signal or the second detection signal output by the detection circuit (figs. 3-4, item 10612 is coupled to the output of item 10611); and an output terminal of the gate circuit is coupled with the output circuit and configured to output the first control signal based on the first detection signal and the enable signal (figs. 3-4, item 10612 is coupled to items 10613 and 1062); and output the second control signal based on the second detection signal and the enable signal (¶83; ¶90).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the combined panel driving circuit of Kuei and Gu, such that the control circuit outputs a first control signal based on the first detection signal and an enable signal; and output a second control signal based on the second detection signal and the enable signal, as taught by Park, resulting in wherein a first input terminal of the gate circuit is coupled with an enable signal terminal and configured to receive the enable signal provided by the enable signal terminal; a second input terminal of the gate circuit is coupled with the detection circuit and configured to receive the first detection signal or the second detection signal output by the detection circuit; and an output terminal of the gate circuit is coupled with the output circuit and configured to output the first control signal based on the first detection signal and the enable signal; and output the second control signal based on the second detection signal and the enable signal, as taught by Park resulting in each of the control sub-circuits being configured to output the first control signal based on the received first detection signal and the enable signal; and output the second control signal based on the received second detection signal and the enable signal, so as to adjust the slew rate in a panel to improve image quality (¶2).
With respect to Claim 7, claim 1 is incorporated, Kuei teaches wherein the output circuit (fig. 2, item 202, 204, and 206; ¶19, “Note that each of the modules illustrated in FIG. 2 refers to a set of modules in a plurality of channels of the source driver 20”; - a plurality of sets of 202, 204, and 206 corresponds to an output circuit”) comprises: a plurality of output sub-circuits in one-to-one correspondence with the plurality of drive channels (fig. 2, item 202, 204, and 206 corresponds to one drive channel), each output sub-circuit being configured to output the drive signal to the display panel through a corresponding drive channel (¶20) at the first slew rate based on the received second control signal (¶22; ¶24, “the slew rate or power level of the output driver 206 in the channel ch_1 may be adjusted or controlled according to the difference value Δch_1, so that the output driver 206 may output the data code ch_1(n+1) with an adequate driving capability”; ¶26-27); and output the drive signal to the display panel through a corresponding drive channel (¶20) at the second slew rate based on the received first control signal (¶22; ¶24, “the slew rate or power level of the output driver 206 in the channel ch_1 may be adjusted or controlled according to the difference value Δch_1, so that the output driver 206 may output the data code ch_1(n+1) with an adequate driving capability”; ¶26-27).
Kuei and Gu combined do not teach wherein the detection circuit further comprises a third register, and the second slew rate is determined by a value stored in the third register.
Park teaches a panel driving circuit for outputting drive signals to a display panel through a plurality of drive channels (fig. 2; ¶59; ¶68), the panel driving circuit comprising: a detection circuit (fig. 2, items 102, 101 and figs. 3-4, item 10611 = XOR and item 10612 = register) configured to, output a first detection signal in a case of detecting that a data change amount of a drive signal output through the drive channel is greater than a data amount threshold (¶76, “if D1<x> and D2<x> are different from each other, it means there is a big change between the first data and the second data and the slew rate needs to be boosted”); and output a second detection signal in a case of detecting that the data change amount of the drive signal output through the drive channel is not greater than the data amount threshold (¶75, “compare whether D1<x> and D2<x> are the same, and if the two are the same, it means there is a little change between the first data and the second data and the slew rate (i.e. the voltage conversion rate) does not need to be boosted”); a control circuit (figs. 3-4, item 10612) configured to receive the first detection signal and the second detection signal (¶79, item 10612 receives a signal that is either the first detection signal: ‘1’ or the second detection signal: ‘0’), and output a first control signal based on the first detection signal and an enable signal (fig. 3, item OENB; ¶80-81; ¶85); and output a second control signal based on the second detection signal and the enable signal (figs. 3-4, item OENB; ¶80; ¶82; ¶85), wherein the first control signal indicates to boost a slew rate of the panel driving circuit (¶81), and the second control signal indicates not to boost the slew rate of the panel driving circuit (¶82), and wherein the enable signal indicates whether to output the first control signal and the second control signal to control a function of adjusting a slew rate (¶85; ¶87; ¶123-124); and an output circuit (fig. 3, items 10613 and 1062) configured to receive the first control signal and the second control signal, and output the drive signal to the display panel through the drive channel at a first slew rate based on the second control signal (¶83; ¶90); and output the drive signal to the display panel through the drive channel at a second slew rate based on the first control signal, wherein the second slew rate is a rate after the first slew rate is boosted (¶83; ¶90); wherein the control circuit comprises a gate circuit (figs. 3-4, item 10612: D flip-flop is composed of logic circuits which are gate circuits); wherein a first input terminal of the gate circuit is coupled with an enable signal terminal and configured to receive the enable signal provided by the enable signal terminal (figs. 3-4, item OENB); a second input terminal of the gate circuit is coupled with the detection circuit and configured to receive the first detection signal or the second detection signal output by the detection circuit (figs. 3-4, item 10612 is coupled to the output of item 10611); and an output terminal of the gate circuit is coupled with the output circuit and configured to output the first control signal based on the first detection signal and the enable signal (figs. 3-4, item 10612 is coupled to items 10613 and 1062); and output the second control signal based on the second detection signal and the enable signal (¶83; ¶90); wherein the detection circuit further comprises a third register (figs. 3-4, within item 1061 is a register = item 10612; ¶78), and the second slew rate is determined by a value stored in the third register (¶80).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the combined panel driving circuit of Kuei and Gu, wherein the detection circuit further comprises a third register, and the second slew rate is determined by a value stored in the third register, as taught by Park so as to adjust the slew rate in a panel to improve image quality (¶2) and provide detection circuit implementations.
With respect to Claim 8, claim 7 is incorporated, Kuei teaches wherein a respective output sub-circuits comprises: a level shifter (fig. 2, item 202) configured to convert a potential of a reference signal (level shifters by default have a reference signal used to define a voltage level to which the input signal is shifted); a decoder (fig. 2, item 204) configured to perform digital-to-analog conversion processing on the reference signal after potential conversion (¶19); and an output buffer (fig. 2, item 206; ¶20, “The output driver 206 may be realized with an operational amplifier, a buffer, or other circuits capable of driving the source node of the thin-film transistor (TFT) on the display panel to reach the gray scale voltage according to the received data code”) configured to buffer the signal output after the digital-to-analog conversion processing into the drive signal at the first slew rate based on the second control signal and output to the display panel (¶22; ¶24; ¶31, “When the comparator 208 determines that the difference value between the data codes is between the upper threshold and the lower threshold, the power level of the output driver 206 may not change”); and buffer the signal output after the digital-to-analog conversion processing into the drive signal at the second slew rate based on the first control signal, and output to the display panel (¶22; ¶24; ¶31, “when the comparator 208 determines that the difference value between the data codes is greater than an upper threshold, the power level of the output driver 206 may be increased”).
With respect to Claim 9, claim 1 is incorporated, Kuei and Gu combined do not mention wherein first input terminals of gate circuits in the plurality of control sub-circuits are coupled with a same enable signal terminal.
Park teaches a panel driving circuit for outputting drive signals to a display panel through a plurality of drive channels (fig. 2; ¶59; ¶68), the panel driving circuit comprising: a detection circuit (fig. 2, items 102, 101 and figs. 3-4, item XOR) configured to, output a first detection signal in a case of detecting that a data change amount of a drive signal output through the drive channel is greater than a data amount threshold (¶76, “if D1<x> and D2<x> are different from each other, it means there is a big change between the first data and the second data and the slew rate needs to be boosted”); and output a second detection signal in a case of detecting that the data change amount of the drive signal output through the drive channel is not greater than the data amount threshold (¶75, “compare whether D1<x> and D2<x> are the same, and if the two are the same, it means there is a little change between the first data and the second data and the slew rate (i.e. the voltage conversion rate) does not need to be boosted”); a control circuit (figs. 3-4, item 10612) configured to receive the first detection signal and the second detection signal (¶79, item 10612 receives a signal that is either the first detection signal: ‘1’ or the second detection signal: ‘0’), and output a first control signal based on the first detection signal and an enable signal (fig. 3, item OENB; ¶80-81; ¶85); and output a second control signal based on the second detection signal and the enable signal (figs. 3-4, item OENB; ¶80; ¶82; ¶85), wherein the first control signal indicates to boost a slew rate of the panel driving circuit (¶81), and the second control signal indicates not to boost the slew rate of the panel driving circuit (¶82), and wherein the enable signal indicates whether to output the first control signal and the second control signal to control a function of adjusting a slew rate (¶85; ¶87; ¶123-124); and an output circuit (fig. 3, items 10613 and 1062) configured to receive the first control signal and the second control signal, and output the drive signal to the display panel through the drive channel at a first slew rate based on the second control signal (¶83; ¶90); and output the drive signal to the display panel through the drive channel at a second slew rate based on the first control signal, wherein the second slew rate is a rate after the first slew rate is boosted (¶83; ¶90); wherein the control circuit comprises a gate circuit (figs. 3-4, item 10612: D flip-flop is composed of logic circuits which are gate circuits); wherein a first input terminal of the gate circuit is coupled with an enable signal terminal and configured to receive the enable signal provided by the enable signal terminal (figs. 3-4, item OENB); a second input terminal of the gate circuit is coupled with the detection circuit and configured to receive the first detection signal or the second detection signal output by the detection circuit (figs. 3-4, item 10612 is coupled to the output of item 10611); and an output terminal of the gate circuit is coupled with the output circuit and configured to output the first control signal based on the first detection signal and the enable signal (figs. 3-4, item 10612 is coupled to items 10613 and 1062); and output the second control signal based on the second detection signal and the enable signal (¶83; ¶90); wherein the first input terminal of the gate circuit is coupled with an enable signal terminal.
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the combined panel driving circuit of Kuei and Gu, wherein the first input terminal of the gate circuit is coupled with an enable signal terminal for each control sub-circuit of Kuei, resulting in wherein first input terminals of gate circuits in the plurality of control sub-circuits are coupled with a same enable signal terminal, such that for each , as taught by Park so as to adjust the slew rate in a panel to improve image quality (¶2).
With respect to Claim 10, claim 1 is incorporated, Kuei teaches wherein potentials of the first detection signal and the second detection signal are different (¶24; ¶28; ¶31).
With respect to Claim 11, claim 2 is incorporated, Kuei teaches wherein potentials of the first control signal and the second control signal are different (¶24; ¶28; ¶31 – the power level is adjusted depending on the first control signal and the second control signal).
With respect to Claim 12, Kuei teaches a method (fig. 8) for driving a panel driving circuit (fig. 2; ¶19), wherein the panel driving circuit outputs drive signals to a display panel through a plurality of drive channels (fig. 4; ¶24), and the panel driving circuit comprises a detection circuit (fig. 2, item L1’, L2’, and item 208: for each channel; ¶19, “Note that each of the modules illustrated in FIG. 2 refers to a set of modules in a plurality of channels of the source driver 20”; - a plurality of sets of L1’, L2’, and 208 corresponds to a detection circuit; ¶24, “The comparator 208 may compare the data code of the line data n with the corresponding data code of the line data n+1 in each channel”), a control circuit (fig. 2, item 208 functions also as a control circuit; ¶19, “Note that each of the modules illustrated in FIG. 2 refers to a set of modules in a plurality of channels of the source driver 20”; - item 208 collectively for all the channels corresponds to a control circuit”), and an output circuit (fig. 2, item 202, 204, and 206; ¶19, “Note that each of the modules illustrated in FIG. 2 refers to a set of modules in a plurality of channels of the source driver 20”; - a plurality of sets of 202, 204, and 206 corresponds to an output circuit”); and the method comprises: for each of the plurality of drive channels, detecting, by the detection circuit, whether a data change amount of a drive signal output through the respective drive channel is greater than a data amount threshold (fig. 8, item 802, 806, and 808; ¶24, “The comparator 208 may compare the data code of the line data n with the corresponding data code of the line data n+1 in each channel. For example, the data code ch_1(n) is compared with the data code ch_1(n+1) in the channel ch_1, and a difference value Δch_1 is generated according to the difference between the data code ch_1(n) and the data code ch_1(n+1)”; ¶31, “when the comparator 208 determines that the difference value between the data codes is greater than an upper threshold, the power level of the output driver 206 may be increased” – a first detection signal corresponds to a power level control; ¶34; ¶36-37); controlling, by the control circuit, the output circuit to output the drive signal to the display panel through the drive channel at a first slew rate in a case of detecting that the data change amount of the drive signal output through the drive channel is not greater than the data amount threshold (fig. 8, item 802, 806 - No and 808 – No OR item 802 and 806 - Yes; ¶24, “a difference value Δch_1 is generated according to the difference between the data code ch_1(n) and the data code ch_1(n+1)”; ¶31, “When the comparator 208 determines that the difference value between the data codes is less than a lower threshold, the power level of the output driver 206 may be decreased. When the comparator 208 determines that the difference value between the data codes is between the upper threshold and the lower threshold, the power level of the output driver 206 may not change” – a second detection signal corresponds to a different power level control; ¶34; ¶36; ¶38; ¶40; ¶46); and controlling, by the control circuit, the output circuit to output the drive signal to the display panel through the drive channel at a second slew rate in a case of detecting that the data change amount of the drive signal output through the drive channel is greater than the data amount threshold (fig. 8, item 802, 806 - No, and 808 – Yes; ¶34; ¶36-37; ¶39; ¶46); wherein the second slew rate is a rate after the first slew rate is boosted (fig. 8; ¶22; ¶24; ¶31); wherein the detection circuit comprises a first register (fig. 2, item L1’) and a second register (fig. 2, item L2’), the detection circuit is configured to output the first detection signal (fig. 2, first detection signal = power level control; ¶22) for each of the plurality of drive channels when a value stored in the first register is a first value (¶22, “the comparator 208 may compare the line data n+1 stored in the latch L1′”, line data n+1 = first value; ¶23, “Please note that the data codes in each channel may be compared at the same time”), and the data amount threshold is determined by a value stored in the second register (¶22, “the comparator 208 may generate a signal indicating the power level for the output driver 206 to transmit the line data n+1”; ¶24, “For example, the data code ch_1(n) is compared with the data code ch_1(n+1) in the channel ch_1, and a difference value Δch_1 is generated according to the difference between the data code ch_1(n) and the data code ch_1(n+1). Therefore, the slew rate or power level of the output driver 206 in the channel ch_1 may be adjusted or controlled according to the difference value Δch_1” – the data amount threshold is based on the determined difference between the data codes); wherein the control circuit comprises a plurality of control sub-circuits; wherein a respective one of the plurality of control sub-circuits comprises a gate circuit (fig. 2 is a schematic diagram of a source driver where item 208 functions as a control sub-circuit for a channel, therefore item 208 is also considered a gate circuit since it is disposed in the source driver).
Kuei does not mention wherein a first input terminal of the gate circuit is coupled with an enable signal terminal and configured to receive the enable signal provided by the enable signal terminal; a second input terminal of the gate circuit is coupled with the detection circuit and configured to receive a first detection signal or a second detection signal output by the detection circuit; and an output terminal of the gate circuit is coupled with the output circuit and configured to output a first control signal based on the first detection signal and the enable signal; and output a second control signal based on the second detection signal and the enable signal, wherein the enable signal indicates whether to output the first control signal and the second control signal to control a function of adjusting a slew rate of a corresponding drive channel.
Park teaches a method (fig. 5; ¶161) for driving a panel driving circuit, wherein the panel driving circuit outputs drive signals to a display panel through a drive channel (fig. 2; ¶59; ¶68), and the panel driving circuit comprising: a detection circuit (fig. 2, items 102, 101 and figs. 3-4, item XOR), a control circuit (figs. 3-4, item 10612), and an output circuit (fig. 3, items 10613 and 1062); and the method comprises: for the drive channel, detecting, by the detection circuit (fig. 2, items 102, 101 and figs. 3-4, item XOR), whether a data change amount of a drive signal output through the drive channel is greater than a data amount threshold (fig. 5, item 502; ¶75, “compare whether D1<x> and D2<x> are the same, and if the two are the same, it means there is a little change between the first data and the second data and the slew rate (i.e. the voltage conversion rate) does not need to be boosted”; ¶76, “if D1<x> and D2<x> are different from each other, it means there is a big change between the first data and the second data and the slew rate needs to be boosted”; ¶163); controlling, by the control circuit (figs. 3-4, item 10612), the output circuit to output the drive signal to the display panel through the drive channel at a first slew rate in a case of detecting that the data change amount of the drive signal output through the drive channel is not greater than the data amount threshold (¶82; ¶163; ¶166); and controlling, by the control circuit, the output circuit to output the drive signal to the display panel through the drive channel at a second slew rate in a case of detecting that the data change amount of the drive signal output through the drive channel is greater than the data amount threshold (¶81; ¶163; ¶165); wherein the second slew rate is a rate after the first slew rate is boosted (¶83; ¶90); wherein the control circuit comprises a gate circuit (figs. 3-4, item 10612: D flip-flop is composed of logic circuits which are gate circuits); wherein a first input terminal of the gate circuit is coupled with an enable signal terminal and configured to receive the enable signal provided by the enable signal terminal (figs. 3-4, item OENB); a second input terminal of the gate circuit is coupled with the detection circuit and configured to receive a first detection signal or a second detection signal output by the detection circuit (figs. 3-4, item 10612 is coupled to the output of item 10611); and an output terminal of the gate circuit is coupled with the output circuit and configured to output a first control signal based on the first detection signal and the enable signal (figs. 3-4, item 10612 is coupled to items 10613 and 1062); and output a second control signal based on the second detection signal and the enable signal (¶83; ¶90), wherein the enable signal indicates whether to output the first control signal and the second control signal to control a function of adjusting a slew rate of a corresponding drive channel (¶85; ¶87; ¶123-124).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Kuei, such that a respective one of the plurality of control sub-circuits of Kuei comprises a gate circuit of Park, resulting in wherein a first input terminal of the gate circuit is coupled with an enable signal terminal and configured to receive the enable signal provided by the enable signal terminal; a second input terminal of the gate circuit is coupled with the detection circuit and configured to receive a first detection signal or a second detection signal output by the detection circuit; and an output terminal of the gate circuit is coupled with the output circuit and configured to output a first control signal based on the first detection signal and the enable signal; and output a second control signal based on the second detection signal and the enable signal, wherein the enable signal indicates whether to output the first control signal and the second control signal to control a function of adjusting a slew rate of a corresponding drive channel, as taught by Park so as to adjust the slew rate in a panel to improve image quality (¶2).
Kuei and Park combined do not mention wherein the gate circuit comprises an AND gate, and only in a case that a potential of the first detection signal received by the second input terminal of the gate circuit, and a potential of the enable signal received by the first input terminal of the gate circuit are both high potential, the control circuit outputs the first control signal based on the first detection signal and the enable signal.
Gu teaches a control circuit (fig. 3, item 42; ¶25) configured to receive a first detection signal and a second detection signal (fig. 3, the output of item 38 is either a first detection signal or a second detection signal; ¶24-25), and output a first control signal based on the first detection signal and an enable signal (¶24, “The data enable signal is used along with the pixel data in the comparator 38 in order to ensure that the first pixel of every scan line is always checked out from the LUT. The comparator 38 outputs a high value if the comparison between the Red_data 1d and the Red_data.sub.--2d is different”); and output a second control signal based on the second detection signal and the enable signal (¶24, “The data enable signal is used along with the pixel data in the comparator 38 in order to ensure that the first pixel of every scan line is always checked out from the LUT. The comparator 38 … outputs a low value if the comparison between Red_data.sub.--1d and Red_data.sub.--2d is the same”), wherein the control circuit comprises a gate circuit (fig. 3, item 42; ¶25, “AND gate 42”); wherein the gate circuit comprises an AND gate (fig. 3, item 42), and only in a case that a potential of the first detection signal received by the second input terminal of the gate circuit, and a potential of the enable signal received by the first input terminal of the gate circuit are both high potential, the control circuit outputs the first control signal based on the first detection signal and the enable signal (¶25, “The first AND gate 42 generates a first comparator output CMP.sub.--1d that is high when the comparison between the Red_data.sub.--1d and the Red_data.sub.--2d is different and the first data enable delay signal DEN.sub.--1d is high”).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Kuei and Park, by replacing the control circuit of Kuei and Park with the teachings of Gu, resulting in wherein the gate circuit comprises an AND gate, and only in a case that a potential of the first detection signal received by the second input terminal of the gate circuit, and a potential of the enable signal received by the first input terminal of the gate circuit are both high potential, the control circuit outputs the first control signal based on the first detection signal and the enable signal, so as to optimize power consumption (¶2; ¶10) and to provide simple logic for the output of the detection circuit to be used as a control signal for an output circuit.
With respect to Claim 13, claim 12 is incorporated, Kuei teaches wherein controlling, by the control circuit, the output circuit to output the drive signal to the display panel through the respective drive channel at the first slew rate comprises: outputting a second detection signal in the case of detecting, by the detection circuit, that the data change amount of the drive signal output through the respective drive channel is not greater than the data amount threshold (fig. 8, item 806- Yes or item 806 – No and 808 – No; ¶24, “a difference value Δch_1 is generated according to the difference between the data code ch_1(n) and the data code ch_1(n+1)”; ¶31, “When the comparator 208 determines that the difference value between the data codes is less than a lower threshold, the power level of the output driver 206 may be decreased. When the comparator 208 determines that the difference value between the data codes is between the upper threshold and the lower threshold, the power level of the output driver 206 may not change” – a second detection signal corresponds to a different power level control; ¶36-37); outputting, by the control circuit, a second control signal based on the second detection signal (¶31 - a second control signal corresponds to a different power level control), wherein the second control signal indicates not to boost a slew rate of the panel driving circuit in the respective drive channel (fig. 8, item 808 – No and item 814; ¶37; ¶40); and outputting, by the output circuit, the drive signal to the display panel through the respective drive channel at the first slew rate based on the second control signal (fig. 8, items 802, 806 – No, item 808 – No, item 814, and item 826; ¶46).
Kuei and Gu combined do not mention outputting, by the control circuit, a second control signal based on the second detection signal and an enable signal.
Park teaches a method (fig. 5; ¶161) for driving a panel driving circuit, wherein the panel driving circuit outputs drive signals to a display panel through a drive channel (fig. 2; ¶59; ¶68), and the panel driving circuit comprising: a detection circuit (fig. 2, items 102, 101 and figs. 3-4, item XOR), a control circuit (figs. 3-4, item 10612), and an output circuit (fig. 3, items 10613 and 1062); and the method comprises: for the drive channel, detecting, by the detection circuit (fig. 2, items 102, 101 and figs. 3-4, item XOR), whether a data change amount of a drive signal output through the drive channel is greater than a data amount threshold (fig. 5, item 502; ¶75, “compare whether D1<x> and D2<x> are the same, and if the two are the same, it means there is a little change between the first data and the second data and the slew rate (i.e. the voltage conversion rate) does not need to be boosted”; ¶76, “if D1<x> and D2<x> are different from each other, it means there is a big change between the first data and the second data and the slew rate needs to be boosted”; ¶163); controlling, by the control circuit (figs. 3-4, item 10612), the output circuit to output the drive signal to the display panel through the drive channel at a first slew rate in a case of detecting that the data change amount of the drive signal output through the drive channel is not greater than the data amount threshold (¶82; ¶163; ¶166); and controlling, by the control circuit, the output circuit to output the drive signal to the display panel through the drive channel at a second slew rate in a case of detecting that the data change amount of the drive signal output through the drive channel is greater than the data amount threshold (¶81; ¶163; ¶165); wherein the second slew rate is a rate after the first slew rate is boosted (¶83; ¶90); wherein the control circuit comprises a gate circuit (figs. 3-4, item 10612: D flip-flop is composed of logic circuits which are gate circuits); wherein a first input terminal of the gate circuit is coupled with an enable signal terminal and configured to receive the enable signal provided by the enable signal terminal (figs. 3-4, item OENB); a second input terminal of the gate circuit is coupled with the detection circuit and configured to receive a first detection signal or a second detection signal output by the detection circuit (figs. 3-4, item 10612 is coupled to the output of item 10611); and an output terminal of the gate circuit is coupled with the output circuit and configured to output a first control signal based on the first detection signal and the enable signal (figs. 3-4, item 10612 is coupled to items 10613 and 1062); and output a second control signal based on the second detection signal and the enable signal (¶83; ¶90), wherein the enable signal indicates whether to output the first control signal and the second control signal to control a function of adjusting a slew rate of a corresponding drive channel (¶85; ¶87; ¶123-124); wherein controlling, by the control circuit (figs. 3-4, item 10612), the output circuit (fig. 3, items 10613 and 1062) to output the drive signal to the display panel through the drive channel at the first slew rate comprises: outputting a second detection signal in the case of detecting, by the detection circuit, that the data change amount of the drive signal output through the drive channel is not greater than the data amount threshold (¶75, “compare whether D1<x> and D2<x> are the same, and if the two are the same, it means there is a little change between the first data and the second data and the slew rate (i.e. the voltage conversion rate) does not need to be boosted”); outputting, by the control circuit, a second control signal based on the second detection signal and an enable signal (figs. 3-4, item OENB; ¶80; ¶82; ¶85), wherein the second control signal indicates not to boost a slew rate of the panel driving circuit in the drive channel (¶82); and outputting, by the output circuit, the drive signal to the display panel through the drive channel at the first slew rate based on the second control signal (¶83; ¶90).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the combined method of Kuei and Gu, to output, by the control circuit, a second control signal based on the second detection signal and an enable signal, as taught by Park so as to adjust the slew rate in a panel to improve image quality (¶2).
With respect to Claim 14, claim 13 is incorporated, Kuei teaches wherein controlling, by the control circuit, the output circuit to output the drive signal to the display panel through the respective drive channel at the second slew rate comprises: outputting a first detection signal in the case of detecting, by the detection circuit, that the data change amount of the drive signal output through the respective drive channel is greater than the data amount threshold (fig. 8, item 806- No, item 808 – Yes; ¶24, “a difference value Δch_1 is generated according to the difference between the data code ch_1(n) and the data code ch_1(n+1)”; ¶31, “When the comparator 208 determines that the difference value between the data codes is less than a lower threshold, the power level of the output driver 206 may be decreased. When the comparator 208 determines that the difference value between the data codes is between the upper threshold and the lower threshold, the power level of the output driver 206 may not change” – a second detection signal corresponds to a different power level control; ¶36-37); outputting, by the control circuit, a first control signal based on the first detection signal (¶31 - a first control signal corresponds to a power level control), wherein the first control signal indicates to boost the slew rate of the panel driving circuit in the respective drive channel (fig. 8, item 808 Yes, item 812, and item 826; ¶37; ¶39); and outputting, by the output circuit, the drive signal to the display panel through the respective drive channel at the second slew rate based on the first control signal (fig. 8, items 802, 806 – No, item 808 – Yes, item 812, and item 826; ¶46).
Kuei and Gu combined do not mention outputting, by the control circuit, a first control signal based on the first detection signal and the enable signal.
Park teaches a method (fig. 5; ¶161) for driving a panel driving circuit, wherein the panel driving circuit outputs drive signals to a display panel through a drive channel (fig. 2; ¶59; ¶68), and the panel driving circuit comprising: a detection circuit (fig. 2, items 102, 101 and figs. 3-4, item XOR), a control circuit (figs. 3-4, item 10612), and an output circuit (fig. 3, items 10613 and 1062); and the method comprises: for the drive channel, detecting, by the detection circuit (fig. 2, items 102, 101 and figs. 3-4, item XOR), whether a data change amount of a drive signal output through the drive channel is greater than a data amount threshold (fig. 5, item 502; ¶75, “compare whether D1<x> and D2<x> are the same, and if the two are the same, it means there is a little change between the first data and the second data and the slew rate (i.e. the voltage conversion rate) does not need to be boosted”; ¶76, “if D1<x> and D2<x> are different from each other, it means there is a big change between the first data and the second data and the slew rate needs to be boosted”; ¶163); controlling, by the control circuit (figs. 3-4, item 10612), the output circuit to output the drive signal to the display panel through the drive channel at a first slew rate in a case of detecting that the data change amount of the drive signal output through the drive channel is not greater than the data amount threshold (¶82; ¶163; ¶166); and controlling, by the control circuit, the output circuit to output the drive signal to the display panel through the drive channel at a second slew rate in a case of detecting that the data change amount of the drive signal output through the drive channel is greater than the data amount threshold (¶81; ¶163; ¶165); wherein the second slew rate is a rate after the first slew rate is boosted (¶83; ¶90); wherein the control circuit comprises a gate circuit (figs. 3-4, item 10612: D flip-flop is composed of logic circuits which are gate circuits); wherein a first input terminal of the gate circuit is coupled with an enable signal terminal and configured to receive the enable signal provided by the enable signal terminal (figs. 3-4, item OENB); a second input terminal of the gate circuit is coupled with the detection circuit and configured to receive a first detection signal or a second detection signal output by the detection circuit (figs. 3-4, item 10612 is coupled to the output of item 10611); and an output terminal of the gate circuit is coupled with the output circuit and configured to output a first control signal based on the first detection signal and the enable signal (figs. 3-4, item 10612 is coupled to items 10613 and 1062); and output a second control signal based on the second detection signal and the enable signal (¶83; ¶90), wherein the enable signal indicates whether to output the first control signal and the second control signal to control a function of adjusting a slew rate of a corresponding drive channel (¶85; ¶87; ¶123-124); wherein controlling, by the control circuit (figs. 3-4, item 10612), the output circuit (fig. 3, items 10613 and 1062) to output the drive signal to the display panel through the drive channel at the first slew rate comprises: outputting a second detection signal in the case of detecting, by the detection circuit, that the data change amount of the drive signal output through the drive channel is not greater than the data amount threshold (¶75, “compare whether D1<x> and D2<x> are the same, and if the two are the same, it means there is a little change between the first data and the second data and the slew rate (i.e. the voltage conversion rate) does not need to be boosted”); outputting, by the control circuit, a second control signal based on the second detection signal and an enable signal (figs. 3-4, item OENB; ¶80; ¶82; ¶85), wherein the second control signal indicates not to boost a slew rate of the panel driving circuit in the drive channel (¶82); and outputting, by the output circuit, the drive signal to the display panel through the drive channel at the first slew rate based on the second control signal (¶83; ¶90); wherein controlling, by the control circuit, the output circuit to output the drive signal to the display panel through the drive channel at the second slew rate comprises: outputting a first detection signal in the case of detecting, by the detection circuit, that the data change amount of the drive signal output through the drive channel is greater than the data amount threshold (¶76, “if D1<x> and D2<x> are different from each other, it means there is a big change between the first data and the second data and the slew rate needs to be boosted”); outputting, by the control circuit, a first control signal based on the first detection signal and the enable signal (fig. 3, item OENB; ¶80-81; ¶85), wherein the first control signal indicates to boost the slew rate of the panel driving circuit in the drive channel (¶81); and outputting, by the output circuit, the drive signal to the display panel through the drive channel at the second slew rate based on the first control signal (¶83; ¶90).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the combined method of Kuei and Gu, to output, by the control circuit, a first control signal based on the first detection signal and the enable signal, as taught by Park so as to adjust the slew rate in a panel to improve image quality (¶2).
With respect to Claim 15, claim 12 is incorporated, Kuei teaches wherein detecting, by the detection circuit, whether the data change amount of the drive signal output through the respective drive channel is greater than the data amount threshold comprises: detecting whether a difference between a data amount of the drive signal output through the respective drive channel at a current moment and a data amount of the drive signal output at another moment adjacent to the current moment is greater than a difference threshold (fig. 4; fig. 8, item 806 and item 808; ¶24; ¶31); determining that the data change amount of the drive signal output through the respective drive channel is greater than the data amount threshold in the case of detecting that the difference between the data amount of the drive signal output through the respective drive channel at the current moment and the data amount of the drive signal output at another moment adjacent to the current moment is greater than the difference threshold (fig. 4; fig. 8, item 806 – No and item 808 – Yes; ¶24; ¶31); and determining that the data change amount of the drive signal output through the respective drive channel is not greater than the data amount threshold in the case of detecting that the difference between the data amount of the drive signal output through the respective drive channel at the current moment and the data amount of the drive signal output at another moment adjacent to the current moment is not greater than the difference threshold (fig. 4; fig. 8, item 806 – No and item 808 No; ¶24; ¶31).
With respect to Claim 16, claim 15 is incorporated, Kuei teaches wherein the detection circuit comprises a storage sub-circuit (figs. 2-3,items L1’ and L2’) and a comparison sub-circuit (fig. 2, item 208); the storage sub-circuit stores the drive signal output through the respective drive channel at the current moment and the drive signal output through the respective drive channel at another moment adjacent to the current moment (¶19; ¶21); detecting whether the difference between the data amount of the drive signal output through the respective drive channel at the current moment and the data amount of the drive signal output at another moment adjacent to the current moment is greater than the difference threshold comprises: comparing, by the comparison sub-circuit, whether the difference between the data amount of the drive signal output through the respective drive channel at the current moment and the data amount of the drive signal output at another moment adjacent to the current moment is greater than the difference threshold (fig. 8, item 808; ¶19; ¶22; ¶31; ¶37).
With respect to Claim 17, claim 13 is incorporated, Kuei teaches wherein the plurality of control sub-circuits are in one-to-one correspondence with the plurality of drive channels (¶19, “Note that each of the modules illustrated in FIG. 2 refers to a set of modules in a plurality of channels of the source driver 20” –each item 208 of each of the channels corresponds to a control sub-circuit); the output circuit (fig. 2, item 202, 204, and 206; ¶19, “Note that each of the modules illustrated in FIG. 2 refers to a set of modules in a plurality of channels of the source driver 20”; - a plurality of sets of 202, 204, and 206 corresponds to an output circuit”) comprises a plurality of output sub-circuits in one-to-one correspondence with the plurality of drive channels (fig. 2, item 202, 204, and 206 corresponds to one drive channel); controlling, by the control circuit, the output circuit (fig. 2, item 206 is part of the output circuit that receives a control signal = power level control) to output the drive signal to the display panel through the respective drive channel at the first slew rate in the case of detecting that the data change amount of the drive signal output through the respective drive channel is not greater than the data amount threshold (fig. 8, item 806 – yes or item 806 – no and item 808 – no; ¶36; ¶37) comprises: controlling, by a respective one of the plurality of control sub-circuits corresponding to the respective drive channel, a corresponding output sub-circuit to output the drive signal to the display panel through the respective drive channel at the first slew rate (fig. 8, item 814 and 826; ¶40; ¶46); and controlling, by the control circuit, the output circuit to output the drive signal to the display panel through the respective drive channel at the second slew rate in the case of detecting that the data change amount of the drive signal output through the respective drive channel is greater than the data amount threshold (fig. 8, item 806 – No and item 808 – yes) comprises: controlling, by the respective control sub-circuit corresponding to the respective drive channel, the corresponding output sub-circuit to output the drive signal to the display panel through the respective drive channel at the second slew rate (fig. 8, item 812 and item 826; ¶39; ¶46).
Kuei and Gu combined do not teach wherein the detection circuit further comprises a third register, and the second slew rate is determined by a value stored in the third register.
Park teaches a method (fig. 5; ¶161) for driving a panel driving circuit, wherein the panel driving circuit outputs drive signals to a display panel through a drive channel (fig. 2; ¶59; ¶68), and the panel driving circuit comprising: a detection circuit (fig. 2, items 102, 101 and figs. 3-4, item XOR), a control circuit (figs. 3-4, item 10612), and an output circuit (fig. 3, items 10613 and 1062); and the method comprises: for the drive channel, detecting, by the detection circuit (fig. 2, items 102, 101 and figs. 3-4, item XOR), whether a data change amount of a drive signal output through the drive channel is greater than a data amount threshold (fig. 5, item 502; ¶75, “compare whether D1<x> and D2<x> are the same, and if the two are the same, it means there is a little change between the first data and the second data and the slew rate (i.e. the voltage conversion rate) does not need to be boosted”; ¶76, “if D1<x> and D2<x> are different from each other, it means there is a big change between the first data and the second data and the slew rate needs to be boosted”; ¶163); controlling, by the control circuit (figs. 3-4, item 10612), the output circuit to output the drive signal to the display panel through the drive channel at a first slew rate in a case of detecting that the data change amount of the drive signal output through the drive channel is not greater than the data amount threshold (¶82; ¶163; ¶166); and controlling, by the control circuit, the output circuit to output the drive signal to the display panel through the drive channel at a second slew rate in a case of detecting that the data change amount of the drive signal output through the drive channel is greater than the data amount threshold (¶81; ¶163; ¶165); wherein the second slew rate is a rate after the first slew rate is boosted (¶83; ¶90); wherein the control circuit comprises a gate circuit (figs. 3-4, item 10612: D flip-flop is composed of logic circuits which are gate circuits); wherein a first input terminal of the gate circuit is coupled with an enable signal terminal and configured to receive the enable signal provided by the enable signal terminal (figs. 3-4, item OENB); a second input terminal of the gate circuit is coupled with the detection circuit and configured to receive a first detection signal or a second detection signal output by the detection circuit (figs. 3-4, item 10612 is coupled to the output of item 10611); and an output terminal of the gate circuit is coupled with the output circuit and configured to output a first control signal based on the first detection signal and the enable signal (figs. 3-4, item 10612 is coupled to items 10613 and 1062); and output a second control signal based on the second detection signal and the enable signal (¶83; ¶90), wherein the enable signal indicates whether to output the first control signal and the second control signal to control a function of adjusting a slew rate of a corresponding drive channel (¶85; ¶87; ¶123-124); wherein the detection circuit further comprises a third register (figs. 3-4, within item 1061 is a register = item 10612; ¶78), and the second slew rate is determined by a value stored in the third register (¶80).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the combined method of Kuei and Gu, wherein the detection circuit further comprises a third register, and the second slew rate is determined by a value stored in the third register, as taught by Park so as to adjust the slew rate in a panel to improve image quality (¶2) and provide detection circuit implementations.
With respect to Claim 18, claim 14 is incorporated, Kuei teaches wherein potentials of the first detection signal and the second detection signal are different (¶24; ¶28; ¶31).
With respect to Claim 19, claim 14 is incorporated, Kuei teaches wherein potentials of the first control signal and the second control signal are different (¶24; ¶28; ¶31 – the power level is adjusted depending on the first control signal and the second control signal).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (Pub. No.: US 2023/0113898 A1) hereinafter referred to as Kim, Kuei, Park, and Gu.
With respect to Claim 20, Kim teaches a display device (fig. 1, item 1; ¶25) comprising: a display panel (fig. 1,item 10; ¶25) and a panel driving circuit (fig. 1, item 30); wherein the panel driving circuit is configured to output drive signals to the display panel through a plurality of drive channels (¶36, the plurality of data lines corresponds to the plurality of drive channels); the display panel is configured to display a picture based on the drive signals (¶26); and the panel driving circuit comprises: a detection circuit (fig. 2, item 31 and 33) configured to, for each of the plurality of drive channels, output a first detection signal in a case of detecting that a data change amount of a drive signal output through the respective drive channel is greater than a data amount threshold (¶43; ¶46, “When the source output enable signal SOE is the enable level and the difference between the first display data DATA1 and the second display data DATA2 exceeds the preset value, the data comparator 33 may generate the first control signal Sc1 of the disable level and generate the second control signal Sc2 of the enable level”); and output a second detection signal in a case of detecting that the data change amount of the drive signal output through the respective drive channel is not greater than the data amount threshold (¶43; ¶46, “when the source output enable signal SOE is the enable level and the difference between the first display data DATA1 and the second display data DATA2 is equal to or smaller than a preset value, the data comparator 33 may generate the first control signal Sc1 of the enable level and generate the second control signal Sc2 of the disable level”); a control circuit (fig. 2, item 33 also functions as a control circuit) configured to output a first control signal based on the first detection signal and an enable signal (fig. 2, item Sc2: first control signal; ¶46); and output a second control signal based on the second detection signal and the enable signal (fig. 2, item Sc1: second control signal; ¶46); wherein the control circuit comprises a gate circuit (fig. 2, item 33 also functions as a control circuit and comprises a gate circuit); wherein the detection circuit comprises a first register (fig. 2, item L1’) and a second register (fig. 2, item L2’), the detection circuit is configured to output the first detection signal (fig. 2, first detection signal = power level control; ¶22) for each of the plurality of drive channels when a value stored in the first register is a first value (¶22, “the comparator 208 may compare the line data n+1 stored in the latch L1′”, line data n+1 = first value; ¶23, “Please note that the data codes in each channel may be compared at the same time”), and the data amount threshold is determined by a value stored in the second register (¶22, “the comparator 208 may generate a signal indicating the power level for the output driver 206 to transmit the line data n+1”; ¶24, “For example, the data code ch_1(n) is compared with the data code ch_1(n+1) in the channel ch_1, and a difference value Δch_1 is generated according to the difference between the data code ch_1(n) and the data code ch_1(n+1). Therefore, the slew rate or power level of the output driver 206 in the channel ch_1 may be adjusted or controlled according to the difference value Δch_1” – the data amount threshold is based on the determined difference between the data codes); wherein a first input terminal of the gate circuit is coupled with an enable signal terminal and configured to receive the enable signal provided by the enable signal terminal (fig. 2, item 33; ¶44); a second input terminal of the gate circuit is coupled with the detection circuit and configured to receive the first detection signal or the second detection signal output by the detection circuit (fig. 2, logic within item 33 receives the first detection signal or the second detection signal); and an output terminal of the gate circuit is coupled with the output circuit and configured to output the first control signal based on the first detection signal and the enable signal (fig. 2, output of item 33 is coupled to item 34 of the output circuit; Sc2 = first control signal); and output the second control signal based on the second detection signal and the enable signal (fig. 2, item 33 outputs item Sc1 = second control signal).
Kim does not mention wherein the first control signal indicates to boost a slew rate of the panel driving circuit in the respective drive channel, and the second control signal indicates not to boost the slew rate of the panel driving circuit in the respective drive channel; wherein the enable signal indicates whether to output the first control signal and the second control signal to control a function of adjusting a slew rate of a corresponding drive channel; and an output circuit, configured to output the drive signal to the display panel through the respective drive channel at a first slew rate based on the second control signal; and output the drive signal to the display panel through the respective drive channel at a second slew rate based on the first control signal, wherein the second slew rate is a rate after the first slew rate is boosted;
Park teaches a panel driving circuit for outputting drive signals to a display panel through a plurality of drive channels (fig. 2; ¶59; ¶68), the panel driving circuit comprising: a detection circuit (fig. 2, items 102, 101 and figs. 3-4, item XOR) configured to, output a first detection signal in a case of detecting that a data change amount of a drive signal output through the drive channel is greater than a data amount threshold (¶76, “if D1<x> and D2<x> are different from each other, it means there is a big change between the first data and the second data and the slew rate needs to be boosted”); and output a second detection signal in a case of detecting that the data change amount of the drive signal output through the drive channel is not greater than the data amount threshold (¶75, “compare whether D1<x> and D2<x> are the same, and if the two are the same, it means there is a little change between the first data and the second data and the slew rate (i.e. the voltage conversion rate) does not need to be boosted”); a control circuit (figs. 3-4, item 10612) configured to receive the first detection signal and the second detection signal (¶79, item 10612 receives a signal that is either the first detection signal: ‘1’ or the second detection signal: ‘0’), and output a first control signal based on the first detection signal and an enable signal (fig. 3, item OENB; ¶80-81; ¶85); and output a second control signal based on the second detection signal and the enable signal (figs. 3-4, item OENB; ¶80; ¶82; ¶85), wherein the first control signal indicates to boost a slew rate of the panel driving circuit (¶81), and the second control signal indicates not to boost the slew rate of the panel driving circuit (¶82), and wherein the enable signal indicates whether to output the first control signal and the second control signal to control a function of adjusting a slew rate (¶85; ¶87; ¶123-124); and an output circuit (fig. 3, items 10613 and 1062) configured to receive the first control signal and the second control signal, and output the drive signal to the display panel through the drive channel at a first slew rate based on the second control signal (¶83; ¶90); and output the drive signal to the display panel through the drive channel at a second slew rate based on the first control signal, wherein the second slew rate is a rate after the first slew rate is boosted (¶83; ¶90); wherein the control circuit comprises a gate circuit (figs. 3-4, item 10612: D flip-flop is composed of logic circuits which are gate circuits); wherein a first input terminal of the gate circuit is coupled with an enable signal terminal and configured to receive the enable signal provided by the enable signal terminal (figs. 3-4, item OENB); a second input terminal of the gate circuit is coupled with the detection circuit and configured to receive the first detection signal or the second detection signal output by the detection circuit (figs. 3-4, item 10612 is coupled to the output of item 10611); and an output terminal of the gate circuit is coupled with the output circuit and configured to output the first control signal based on the first detection signal and the enable signal (figs. 3-4, item 10612 is coupled to items 10613 and 1062); and output the second control signal based on the second detection signal and the enable signal (¶83; ¶90).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display device of Kim, such that the control circuit outputs a first control signal based on the first detection signal and an enable signal; and output a second control signal based on the second detection signal and the enable signal, and wherein the enable signal indicates whether to output the first control signal and the second control signal to control a function of adjusting a slew rate of a corresponding drive channel; wherein the control circuit comprises a gate circuit; wherein a first input terminal of the gate circuit is coupled with an enable signal terminal and configured to receive the enable signal provided by the enable signal terminal; a second input terminal of the gate circuit is coupled with the detection circuit and configured to receive the first detection signal or the second detection signal output by the detection circuit; and an output terminal of the gate circuit is coupled with the output circuit and configured to output the first control signal based on the first detection signal and the enable signal; and output the second control signal based on the second detection signal and the enable signal, as taught by Park so as to adjust the slew rate in a panel to improve image quality (¶2).
Kim and Park combined do not mention wherein the control circuit comprises a plurality of control sub-circuits; wherein a respective control sub-circuit comprises a gate circuit.
Kuei teaches a panel driving circuit (fig. 2; ¶19) for outputting drive signals to a display panel through a plurality of drive channels (fig. 4; ¶24), the panel driving circuit comprising: a detection circuit (fig. 2, item L1’, L2’, and item 208: for each channel; ¶19, “Note that each of the modules illustrated in FIG. 2 refers to a set of modules in a plurality of channels of the source driver 20”; - a plurality of sets of L1’, L2’, and 208 corresponds to a detection circuit; ¶24, “The comparator 208 may compare the data code of the line data n with the corresponding data code of the line data n+1 in each channel”) configured to, for each of the plurality of drive channels, output a first detection signal in a case of detecting that a data change amount of a drive signal output through the drive channel is greater than a data amount threshold (¶24, “a difference value Δch_1 is generated according to the difference between the data code ch_1(n) and the data code ch_1(n+1)”; ¶31, “when the comparator 208 determines that the difference value between the data codes is greater than an upper threshold, the power level of the output driver 206 may be increased” – a first detection signal corresponds to a power level control); and output a second detection signal in a case of detecting that the data change amount of the drive signal output through the drive channel is not greater than the data amount threshold (¶24, “a difference value Δch_1 is generated according to the difference between the data code ch_1(n) and the data code ch_1(n+1)”; ¶31, “When the comparator 208 determines that the difference value between the data codes is less than a lower threshold, the power level of the output driver 206 may be decreased. When the comparator 208 determines that the difference value between the data codes is between the upper threshold and the lower threshold, the power level of the output driver 206 may not change” – a second detection signal corresponds to a different power level control); a control circuit (fig. 2, item 208 functions also as a control circuit; ¶19, “Note that each of the modules illustrated in FIG. 2 refers to a set of modules in a plurality of channels of the source driver 20”; - item 208 collectively for all the channels corresponds to a control circuit;) configured to receive the first detection signal and the second detection signal (received internally via computation), and output a first control signal based on the first detection signal (¶31- a first control signal corresponds to a power level control); and output a second control signal based on the second detection signal (¶31 - a second control signal corresponds to a different power level control), wherein the first control signal indicates to boost a slew rate of the panel driving circuit in the drive channel (¶31, “when the comparator 208 determines that the difference value between the data codes is greater than an upper threshold, the power level of the output driver 206 may be increased”), and the second control signal indicates not to boost the slew rate of the panel driving circuit in the drive channel (¶31, “When the comparator 208 determines that the difference value between the data codes is less than a lower threshold, the power level of the output driver 206 may be decreased. When the comparator 208 determines that the difference value between the data codes is between the upper threshold and the lower threshold, the power level of the output driver 206 may not change”); and an output circuit (fig. 2, item 202, 204, and 206; ¶19, “Note that each of the modules illustrated in FIG. 2 refers to a set of modules in a plurality of channels of the source driver 20”; - a plurality of sets of 202, 204, and 206 corresponds to an output circuit”) configured to receive the first control signal and the second control signal (fig. 2, item 206 receives the first control signal and the second control signal), and output the drive signal to the display panel through the drive channel at a first slew rate based on the second control signal (fig. 5; ¶22; ¶24, “the slew rate or power level of the output driver 206 in the channel ch_1 may be adjusted or controlled according to the difference value Δch_1, so that the output driver 206 may output the data code ch_1(n+1) with an adequate driving capability”); and output the drive signal to the display panel through the drive channel at a second slew rate based on the first control signal (¶22; ¶24, “the slew rate or power level of the output driver 206 in the channel ch_1 may be adjusted or controlled according to the difference value Δch_1, so that the output driver 206 may output the data code ch_1(n+1) with an adequate driving capability”), wherein the second slew rate is a rate after the first slew rate is boosted (fig. 8; ¶22; ¶24; ¶31); wherein the control circuit comprises a plurality of control sub-circuits; wherein a respective control sub-circuit comprises a gate circuit (fig. 2 is a schematic diagram of a source driver where item 208 functions as a control sub-circuit for a channel, therefore item 208 is also considered a gate circuit since it is disposed in the source driver).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the combined display device of Kim and Park, wherein the control circuit comprises a plurality of control sub-circuits; wherein a respective control sub-circuit comprises a gate circuit, as taught by Kuei so as to control a power level of an output driver in a source driver of a display system to allow the output driver to output the line data with adequate power and driving capability in cases where a plurality of source drivers exist (¶6; ¶56).
Kim, Park, and Kuei combined do not mention wherein the gate circuit comprises an AND gate, and only in a case that a potential of the first detection signal received by the second input terminal of the gate circuit, and a potential of the enable signal received by the first input terminal of the gate circuit are both high potential, the control circuit outputs the first control signal based on the first detection signal and the enable signal.
Gu teaches a control circuit (fig. 3, item 42; ¶25) configured to receive a first detection signal and a second detection signal (fig. 3, the output of item 38 is either a first detection signal or a second detection signal; ¶24-25), and output a first control signal based on the first detection signal and an enable signal (¶24, “The data enable signal is used along with the pixel data in the comparator 38 in order to ensure that the first pixel of every scan line is always checked out from the LUT. The comparator 38 outputs a high value if the comparison between the Red_data 1d and the Red_data.sub.--2d is different”); and output a second control signal based on the second detection signal and the enable signal (¶24, “The data enable signal is used along with the pixel data in the comparator 38 in order to ensure that the first pixel of every scan line is always checked out from the LUT. The comparator 38 … outputs a low value if the comparison between Red_data.sub.--1d and Red_data.sub.--2d is the same”), wherein the control circuit comprises a gate circuit (fig. 3, item 42; ¶25, “AND gate 42”); wherein the gate circuit comprises an AND gate (fig. 3, item 42), and only in a case that a potential of the first detection signal received by the second input terminal of the gate circuit, and a potential of the enable signal received by the first input terminal of the gate circuit are both high potential, the control circuit outputs the first control signal based on the first detection signal and the enable signal (¶25, “The first AND gate 42 generates a first comparator output CMP.sub.--1d that is high when the comparison between the Red_data.sub.--1d and the Red_data.sub.--2d is different and the first data enable delay signal DEN.sub.--1d is high”).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the combined display device of Kim, Park, and Kuei by replacing the control circuit of Kim, Park, and Kuei with the teachings of Gu, resulting in wherein the gate circuit comprises an AND gate, and only in a case that a potential of the first detection signal received by the second input terminal of the gate circuit, and a potential of the enable signal received by the first input terminal of the gate circuit are both high potential, the control circuit outputs the first control signal based on the first detection signal and the enable signal, so as to optimize power consumption (¶2; ¶10) and to provide simple logic for the output of the detection circuit to be used as a control signal for an output circuit.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/DONNA V Bocar/ Primary Examiner, Art Unit 2621
